xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/sun4i/sun4i_crtc.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2015 Free Electrons
4*4882a593Smuzhiyun  * Copyright (C) 2015 NextThing Co
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Maxime Ripard <maxime.ripard@free-electrons.com>
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/clk-provider.h>
10*4882a593Smuzhiyun #include <linux/ioport.h>
11*4882a593Smuzhiyun #include <linux/of_address.h>
12*4882a593Smuzhiyun #include <linux/of_graph.h>
13*4882a593Smuzhiyun #include <linux/of_irq.h>
14*4882a593Smuzhiyun #include <linux/regmap.h>
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #include <video/videomode.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
19*4882a593Smuzhiyun #include <drm/drm_crtc.h>
20*4882a593Smuzhiyun #include <drm/drm_modes.h>
21*4882a593Smuzhiyun #include <drm/drm_print.h>
22*4882a593Smuzhiyun #include <drm/drm_probe_helper.h>
23*4882a593Smuzhiyun #include <drm/drm_vblank.h>
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #include "sun4i_backend.h"
26*4882a593Smuzhiyun #include "sun4i_crtc.h"
27*4882a593Smuzhiyun #include "sun4i_drv.h"
28*4882a593Smuzhiyun #include "sunxi_engine.h"
29*4882a593Smuzhiyun #include "sun4i_tcon.h"
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun /*
32*4882a593Smuzhiyun  * While this isn't really working in the DRM theory, in practice we
33*4882a593Smuzhiyun  * can only ever have one encoder per TCON since we have a mux in our
34*4882a593Smuzhiyun  * TCON.
35*4882a593Smuzhiyun  */
sun4i_crtc_get_encoder(struct drm_crtc * crtc)36*4882a593Smuzhiyun static struct drm_encoder *sun4i_crtc_get_encoder(struct drm_crtc *crtc)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun 	struct drm_encoder *encoder;
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun 	drm_for_each_encoder(encoder, crtc->dev)
41*4882a593Smuzhiyun 		if (encoder->crtc == crtc)
42*4882a593Smuzhiyun 			return encoder;
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun 	return NULL;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun 
sun4i_crtc_atomic_check(struct drm_crtc * crtc,struct drm_crtc_state * state)47*4882a593Smuzhiyun static int sun4i_crtc_atomic_check(struct drm_crtc *crtc,
48*4882a593Smuzhiyun 				    struct drm_crtc_state *state)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun 	struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);
51*4882a593Smuzhiyun 	struct sunxi_engine *engine = scrtc->engine;
52*4882a593Smuzhiyun 	int ret = 0;
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun 	if (engine && engine->ops && engine->ops->atomic_check)
55*4882a593Smuzhiyun 		ret = engine->ops->atomic_check(engine, state);
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	return ret;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun 
sun4i_crtc_atomic_begin(struct drm_crtc * crtc,struct drm_crtc_state * old_state)60*4882a593Smuzhiyun static void sun4i_crtc_atomic_begin(struct drm_crtc *crtc,
61*4882a593Smuzhiyun 				    struct drm_crtc_state *old_state)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun 	struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);
64*4882a593Smuzhiyun 	struct drm_device *dev = crtc->dev;
65*4882a593Smuzhiyun 	struct sunxi_engine *engine = scrtc->engine;
66*4882a593Smuzhiyun 	unsigned long flags;
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun 	if (crtc->state->event) {
69*4882a593Smuzhiyun 		WARN_ON(drm_crtc_vblank_get(crtc) != 0);
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 		spin_lock_irqsave(&dev->event_lock, flags);
72*4882a593Smuzhiyun 		scrtc->event = crtc->state->event;
73*4882a593Smuzhiyun 		spin_unlock_irqrestore(&dev->event_lock, flags);
74*4882a593Smuzhiyun 		crtc->state->event = NULL;
75*4882a593Smuzhiyun 	}
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 	if (engine->ops->atomic_begin)
78*4882a593Smuzhiyun 		engine->ops->atomic_begin(engine, old_state);
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun 
sun4i_crtc_atomic_flush(struct drm_crtc * crtc,struct drm_crtc_state * old_state)81*4882a593Smuzhiyun static void sun4i_crtc_atomic_flush(struct drm_crtc *crtc,
82*4882a593Smuzhiyun 				    struct drm_crtc_state *old_state)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun 	struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);
85*4882a593Smuzhiyun 	struct drm_pending_vblank_event *event = crtc->state->event;
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 	DRM_DEBUG_DRIVER("Committing plane changes\n");
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 	sunxi_engine_commit(scrtc->engine);
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	if (event) {
92*4882a593Smuzhiyun 		crtc->state->event = NULL;
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 		spin_lock_irq(&crtc->dev->event_lock);
95*4882a593Smuzhiyun 		if (drm_crtc_vblank_get(crtc) == 0)
96*4882a593Smuzhiyun 			drm_crtc_arm_vblank_event(crtc, event);
97*4882a593Smuzhiyun 		else
98*4882a593Smuzhiyun 			drm_crtc_send_vblank_event(crtc, event);
99*4882a593Smuzhiyun 		spin_unlock_irq(&crtc->dev->event_lock);
100*4882a593Smuzhiyun 	}
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun 
sun4i_crtc_atomic_disable(struct drm_crtc * crtc,struct drm_crtc_state * old_state)103*4882a593Smuzhiyun static void sun4i_crtc_atomic_disable(struct drm_crtc *crtc,
104*4882a593Smuzhiyun 				      struct drm_crtc_state *old_state)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun 	struct drm_encoder *encoder = sun4i_crtc_get_encoder(crtc);
107*4882a593Smuzhiyun 	struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 	DRM_DEBUG_DRIVER("Disabling the CRTC\n");
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 	drm_crtc_vblank_off(crtc);
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	sun4i_tcon_set_status(scrtc->tcon, encoder, false);
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	if (crtc->state->event && !crtc->state->active) {
116*4882a593Smuzhiyun 		spin_lock_irq(&crtc->dev->event_lock);
117*4882a593Smuzhiyun 		drm_crtc_send_vblank_event(crtc, crtc->state->event);
118*4882a593Smuzhiyun 		spin_unlock_irq(&crtc->dev->event_lock);
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 		crtc->state->event = NULL;
121*4882a593Smuzhiyun 	}
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun 
sun4i_crtc_atomic_enable(struct drm_crtc * crtc,struct drm_crtc_state * old_state)124*4882a593Smuzhiyun static void sun4i_crtc_atomic_enable(struct drm_crtc *crtc,
125*4882a593Smuzhiyun 				     struct drm_crtc_state *old_state)
126*4882a593Smuzhiyun {
127*4882a593Smuzhiyun 	struct drm_encoder *encoder = sun4i_crtc_get_encoder(crtc);
128*4882a593Smuzhiyun 	struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	DRM_DEBUG_DRIVER("Enabling the CRTC\n");
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	sun4i_tcon_set_status(scrtc->tcon, encoder, true);
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	drm_crtc_vblank_on(crtc);
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun 
sun4i_crtc_mode_set_nofb(struct drm_crtc * crtc)137*4882a593Smuzhiyun static void sun4i_crtc_mode_set_nofb(struct drm_crtc *crtc)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun 	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
140*4882a593Smuzhiyun 	struct drm_encoder *encoder = sun4i_crtc_get_encoder(crtc);
141*4882a593Smuzhiyun 	struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	sun4i_tcon_mode_set(scrtc->tcon, encoder, mode);
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun static const struct drm_crtc_helper_funcs sun4i_crtc_helper_funcs = {
147*4882a593Smuzhiyun 	.atomic_check	= sun4i_crtc_atomic_check,
148*4882a593Smuzhiyun 	.atomic_begin	= sun4i_crtc_atomic_begin,
149*4882a593Smuzhiyun 	.atomic_flush	= sun4i_crtc_atomic_flush,
150*4882a593Smuzhiyun 	.atomic_enable	= sun4i_crtc_atomic_enable,
151*4882a593Smuzhiyun 	.atomic_disable	= sun4i_crtc_atomic_disable,
152*4882a593Smuzhiyun 	.mode_set_nofb	= sun4i_crtc_mode_set_nofb,
153*4882a593Smuzhiyun };
154*4882a593Smuzhiyun 
sun4i_crtc_enable_vblank(struct drm_crtc * crtc)155*4882a593Smuzhiyun static int sun4i_crtc_enable_vblank(struct drm_crtc *crtc)
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun 	struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	DRM_DEBUG_DRIVER("Enabling VBLANK on crtc %p\n", crtc);
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	sun4i_tcon_enable_vblank(scrtc->tcon, true);
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	return 0;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun 
sun4i_crtc_disable_vblank(struct drm_crtc * crtc)166*4882a593Smuzhiyun static void sun4i_crtc_disable_vblank(struct drm_crtc *crtc)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun 	struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 	DRM_DEBUG_DRIVER("Disabling VBLANK on crtc %p\n", crtc);
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun 	sun4i_tcon_enable_vblank(scrtc->tcon, false);
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun static const struct drm_crtc_funcs sun4i_crtc_funcs = {
176*4882a593Smuzhiyun 	.atomic_destroy_state	= drm_atomic_helper_crtc_destroy_state,
177*4882a593Smuzhiyun 	.atomic_duplicate_state	= drm_atomic_helper_crtc_duplicate_state,
178*4882a593Smuzhiyun 	.destroy		= drm_crtc_cleanup,
179*4882a593Smuzhiyun 	.page_flip		= drm_atomic_helper_page_flip,
180*4882a593Smuzhiyun 	.reset			= drm_atomic_helper_crtc_reset,
181*4882a593Smuzhiyun 	.set_config		= drm_atomic_helper_set_config,
182*4882a593Smuzhiyun 	.enable_vblank		= sun4i_crtc_enable_vblank,
183*4882a593Smuzhiyun 	.disable_vblank		= sun4i_crtc_disable_vblank,
184*4882a593Smuzhiyun };
185*4882a593Smuzhiyun 
sun4i_crtc_init(struct drm_device * drm,struct sunxi_engine * engine,struct sun4i_tcon * tcon)186*4882a593Smuzhiyun struct sun4i_crtc *sun4i_crtc_init(struct drm_device *drm,
187*4882a593Smuzhiyun 				   struct sunxi_engine *engine,
188*4882a593Smuzhiyun 				   struct sun4i_tcon *tcon)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun 	struct sun4i_crtc *scrtc;
191*4882a593Smuzhiyun 	struct drm_plane **planes;
192*4882a593Smuzhiyun 	struct drm_plane *primary = NULL, *cursor = NULL;
193*4882a593Smuzhiyun 	int ret, i;
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	scrtc = devm_kzalloc(drm->dev, sizeof(*scrtc), GFP_KERNEL);
196*4882a593Smuzhiyun 	if (!scrtc)
197*4882a593Smuzhiyun 		return ERR_PTR(-ENOMEM);
198*4882a593Smuzhiyun 	scrtc->engine = engine;
199*4882a593Smuzhiyun 	scrtc->tcon = tcon;
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun 	/* Create our layers */
202*4882a593Smuzhiyun 	planes = sunxi_engine_layers_init(drm, engine);
203*4882a593Smuzhiyun 	if (IS_ERR(planes)) {
204*4882a593Smuzhiyun 		dev_err(drm->dev, "Couldn't create the planes\n");
205*4882a593Smuzhiyun 		return NULL;
206*4882a593Smuzhiyun 	}
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	/* find primary and cursor planes for drm_crtc_init_with_planes */
209*4882a593Smuzhiyun 	for (i = 0; planes[i]; i++) {
210*4882a593Smuzhiyun 		struct drm_plane *plane = planes[i];
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 		switch (plane->type) {
213*4882a593Smuzhiyun 		case DRM_PLANE_TYPE_PRIMARY:
214*4882a593Smuzhiyun 			primary = plane;
215*4882a593Smuzhiyun 			break;
216*4882a593Smuzhiyun 		case DRM_PLANE_TYPE_CURSOR:
217*4882a593Smuzhiyun 			cursor = plane;
218*4882a593Smuzhiyun 			break;
219*4882a593Smuzhiyun 		default:
220*4882a593Smuzhiyun 			break;
221*4882a593Smuzhiyun 		}
222*4882a593Smuzhiyun 	}
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun 	ret = drm_crtc_init_with_planes(drm, &scrtc->crtc,
225*4882a593Smuzhiyun 					primary,
226*4882a593Smuzhiyun 					cursor,
227*4882a593Smuzhiyun 					&sun4i_crtc_funcs,
228*4882a593Smuzhiyun 					NULL);
229*4882a593Smuzhiyun 	if (ret) {
230*4882a593Smuzhiyun 		dev_err(drm->dev, "Couldn't init DRM CRTC\n");
231*4882a593Smuzhiyun 		return ERR_PTR(ret);
232*4882a593Smuzhiyun 	}
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 	drm_crtc_helper_add(&scrtc->crtc, &sun4i_crtc_helper_funcs);
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun 	/* Set crtc.port to output port node of the tcon */
237*4882a593Smuzhiyun 	scrtc->crtc.port = of_graph_get_port_by_id(scrtc->tcon->dev->of_node,
238*4882a593Smuzhiyun 						   1);
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun 	/* Set possible_crtcs to this crtc for overlay planes */
241*4882a593Smuzhiyun 	for (i = 0; planes[i]; i++) {
242*4882a593Smuzhiyun 		uint32_t possible_crtcs = drm_crtc_mask(&scrtc->crtc);
243*4882a593Smuzhiyun 		struct drm_plane *plane = planes[i];
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 		if (plane->type == DRM_PLANE_TYPE_OVERLAY)
246*4882a593Smuzhiyun 			plane->possible_crtcs = possible_crtcs;
247*4882a593Smuzhiyun 	}
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun 	return scrtc;
250*4882a593Smuzhiyun }
251