1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) STMicroelectronics SA 2017 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Authors: Philippe Cornu <philippe.cornu@st.com> 6*4882a593Smuzhiyun * Yannick Fertre <yannick.fertre@st.com> 7*4882a593Smuzhiyun * Fabien Dessenne <fabien.dessenne@st.com> 8*4882a593Smuzhiyun * Mickael Reulier <mickael.reulier@st.com> 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _LTDC_H_ 12*4882a593Smuzhiyun #define _LTDC_H_ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun struct ltdc_caps { 15*4882a593Smuzhiyun u32 hw_version; /* hardware version */ 16*4882a593Smuzhiyun u32 nb_layers; /* number of supported layers */ 17*4882a593Smuzhiyun u32 reg_ofs; /* register offset for applicable regs */ 18*4882a593Smuzhiyun u32 bus_width; /* bus width (32 or 64 bits) */ 19*4882a593Smuzhiyun const u32 *pix_fmt_hw; /* supported pixel formats */ 20*4882a593Smuzhiyun bool non_alpha_only_l1; /* non-native no-alpha formats on layer 1 */ 21*4882a593Smuzhiyun int pad_max_freq_hz; /* max frequency supported by pad */ 22*4882a593Smuzhiyun int nb_irq; /* number of hardware interrupts */ 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define LTDC_MAX_LAYER 4 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun struct fps_info { 28*4882a593Smuzhiyun unsigned int counter; 29*4882a593Smuzhiyun ktime_t last_timestamp; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun struct ltdc_device { 33*4882a593Smuzhiyun void __iomem *regs; 34*4882a593Smuzhiyun struct clk *pixel_clk; /* lcd pixel clock */ 35*4882a593Smuzhiyun struct mutex err_lock; /* protecting error_status */ 36*4882a593Smuzhiyun struct ltdc_caps caps; 37*4882a593Smuzhiyun u32 error_status; 38*4882a593Smuzhiyun u32 irq_status; 39*4882a593Smuzhiyun struct fps_info plane_fpsi[LTDC_MAX_LAYER]; 40*4882a593Smuzhiyun struct drm_atomic_state *suspend_state; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun int ltdc_load(struct drm_device *ddev); 44*4882a593Smuzhiyun void ltdc_unload(struct drm_device *ddev); 45*4882a593Smuzhiyun void ltdc_suspend(struct drm_device *ddev); 46*4882a593Smuzhiyun int ltdc_resume(struct drm_device *ddev); 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #endif 49