1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) STMicroelectronics SA 2014
4*4882a593Smuzhiyun * Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
5*4882a593Smuzhiyun * Vincent Abriou <vincent.abriou@st.com>
6*4882a593Smuzhiyun * for STMicroelectronics.
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/clk.h>
10*4882a593Smuzhiyun #include <linux/component.h>
11*4882a593Smuzhiyun #include <linux/io.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/of_platform.h>
14*4882a593Smuzhiyun #include <linux/platform_device.h>
15*4882a593Smuzhiyun #include <linux/reset.h>
16*4882a593Smuzhiyun #include <linux/seq_file.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
19*4882a593Smuzhiyun #include <drm/drm_debugfs.h>
20*4882a593Smuzhiyun #include <drm/drm_device.h>
21*4882a593Smuzhiyun #include <drm/drm_file.h>
22*4882a593Smuzhiyun #include <drm/drm_print.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #include "sti_crtc.h"
25*4882a593Smuzhiyun #include "sti_drv.h"
26*4882a593Smuzhiyun #include "sti_vtg.h"
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* glue registers */
29*4882a593Smuzhiyun #define TVO_CSC_MAIN_M0 0x000
30*4882a593Smuzhiyun #define TVO_CSC_MAIN_M1 0x004
31*4882a593Smuzhiyun #define TVO_CSC_MAIN_M2 0x008
32*4882a593Smuzhiyun #define TVO_CSC_MAIN_M3 0x00c
33*4882a593Smuzhiyun #define TVO_CSC_MAIN_M4 0x010
34*4882a593Smuzhiyun #define TVO_CSC_MAIN_M5 0x014
35*4882a593Smuzhiyun #define TVO_CSC_MAIN_M6 0x018
36*4882a593Smuzhiyun #define TVO_CSC_MAIN_M7 0x01c
37*4882a593Smuzhiyun #define TVO_MAIN_IN_VID_FORMAT 0x030
38*4882a593Smuzhiyun #define TVO_CSC_AUX_M0 0x100
39*4882a593Smuzhiyun #define TVO_CSC_AUX_M1 0x104
40*4882a593Smuzhiyun #define TVO_CSC_AUX_M2 0x108
41*4882a593Smuzhiyun #define TVO_CSC_AUX_M3 0x10c
42*4882a593Smuzhiyun #define TVO_CSC_AUX_M4 0x110
43*4882a593Smuzhiyun #define TVO_CSC_AUX_M5 0x114
44*4882a593Smuzhiyun #define TVO_CSC_AUX_M6 0x118
45*4882a593Smuzhiyun #define TVO_CSC_AUX_M7 0x11c
46*4882a593Smuzhiyun #define TVO_AUX_IN_VID_FORMAT 0x130
47*4882a593Smuzhiyun #define TVO_VIP_HDF 0x400
48*4882a593Smuzhiyun #define TVO_HD_SYNC_SEL 0x418
49*4882a593Smuzhiyun #define TVO_HD_DAC_CFG_OFF 0x420
50*4882a593Smuzhiyun #define TVO_VIP_HDMI 0x500
51*4882a593Smuzhiyun #define TVO_HDMI_FORCE_COLOR_0 0x504
52*4882a593Smuzhiyun #define TVO_HDMI_FORCE_COLOR_1 0x508
53*4882a593Smuzhiyun #define TVO_HDMI_CLIP_VALUE_B_CB 0x50c
54*4882a593Smuzhiyun #define TVO_HDMI_CLIP_VALUE_Y_G 0x510
55*4882a593Smuzhiyun #define TVO_HDMI_CLIP_VALUE_R_CR 0x514
56*4882a593Smuzhiyun #define TVO_HDMI_SYNC_SEL 0x518
57*4882a593Smuzhiyun #define TVO_HDMI_DFV_OBS 0x540
58*4882a593Smuzhiyun #define TVO_VIP_DVO 0x600
59*4882a593Smuzhiyun #define TVO_DVO_SYNC_SEL 0x618
60*4882a593Smuzhiyun #define TVO_DVO_CONFIG 0x620
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun #define TVO_IN_FMT_SIGNED BIT(0)
63*4882a593Smuzhiyun #define TVO_SYNC_EXT BIT(4)
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun #define TVO_VIP_REORDER_R_SHIFT 24
66*4882a593Smuzhiyun #define TVO_VIP_REORDER_G_SHIFT 20
67*4882a593Smuzhiyun #define TVO_VIP_REORDER_B_SHIFT 16
68*4882a593Smuzhiyun #define TVO_VIP_REORDER_MASK 0x3
69*4882a593Smuzhiyun #define TVO_VIP_REORDER_Y_G_SEL 0
70*4882a593Smuzhiyun #define TVO_VIP_REORDER_CB_B_SEL 1
71*4882a593Smuzhiyun #define TVO_VIP_REORDER_CR_R_SEL 2
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun #define TVO_VIP_CLIP_SHIFT 8
74*4882a593Smuzhiyun #define TVO_VIP_CLIP_MASK 0x7
75*4882a593Smuzhiyun #define TVO_VIP_CLIP_DISABLED 0
76*4882a593Smuzhiyun #define TVO_VIP_CLIP_EAV_SAV 1
77*4882a593Smuzhiyun #define TVO_VIP_CLIP_LIMITED_RANGE_RGB_Y 2
78*4882a593Smuzhiyun #define TVO_VIP_CLIP_LIMITED_RANGE_CB_CR 3
79*4882a593Smuzhiyun #define TVO_VIP_CLIP_PROG_RANGE 4
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun #define TVO_VIP_RND_SHIFT 4
82*4882a593Smuzhiyun #define TVO_VIP_RND_MASK 0x3
83*4882a593Smuzhiyun #define TVO_VIP_RND_8BIT_ROUNDED 0
84*4882a593Smuzhiyun #define TVO_VIP_RND_10BIT_ROUNDED 1
85*4882a593Smuzhiyun #define TVO_VIP_RND_12BIT_ROUNDED 2
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun #define TVO_VIP_SEL_INPUT_MASK 0xf
88*4882a593Smuzhiyun #define TVO_VIP_SEL_INPUT_MAIN 0x0
89*4882a593Smuzhiyun #define TVO_VIP_SEL_INPUT_AUX 0x8
90*4882a593Smuzhiyun #define TVO_VIP_SEL_INPUT_FORCE_COLOR 0xf
91*4882a593Smuzhiyun #define TVO_VIP_SEL_INPUT_BYPASS_MASK 0x1
92*4882a593Smuzhiyun #define TVO_VIP_SEL_INPUT_BYPASSED 1
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun #define TVO_SYNC_MAIN_VTG_SET_REF 0x00
95*4882a593Smuzhiyun #define TVO_SYNC_AUX_VTG_SET_REF 0x10
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun #define TVO_SYNC_HD_DCS_SHIFT 8
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun #define TVO_SYNC_DVO_PAD_HSYNC_SHIFT 8
100*4882a593Smuzhiyun #define TVO_SYNC_DVO_PAD_VSYNC_SHIFT 16
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun #define ENCODER_CRTC_MASK (BIT(0) | BIT(1))
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun #define TVO_MIN_HD_HEIGHT 720
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun /* enum listing the supported output data format */
107*4882a593Smuzhiyun enum sti_tvout_video_out_type {
108*4882a593Smuzhiyun STI_TVOUT_VIDEO_OUT_RGB,
109*4882a593Smuzhiyun STI_TVOUT_VIDEO_OUT_YUV,
110*4882a593Smuzhiyun };
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun struct sti_tvout {
113*4882a593Smuzhiyun struct device *dev;
114*4882a593Smuzhiyun struct drm_device *drm_dev;
115*4882a593Smuzhiyun void __iomem *regs;
116*4882a593Smuzhiyun struct reset_control *reset;
117*4882a593Smuzhiyun struct drm_encoder *hdmi;
118*4882a593Smuzhiyun struct drm_encoder *hda;
119*4882a593Smuzhiyun struct drm_encoder *dvo;
120*4882a593Smuzhiyun bool debugfs_registered;
121*4882a593Smuzhiyun };
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun struct sti_tvout_encoder {
124*4882a593Smuzhiyun struct drm_encoder encoder;
125*4882a593Smuzhiyun struct sti_tvout *tvout;
126*4882a593Smuzhiyun };
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun #define to_sti_tvout_encoder(x) \
129*4882a593Smuzhiyun container_of(x, struct sti_tvout_encoder, encoder)
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun #define to_sti_tvout(x) to_sti_tvout_encoder(x)->tvout
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun /* preformatter conversion matrix */
134*4882a593Smuzhiyun static const u32 rgb_to_ycbcr_601[8] = {
135*4882a593Smuzhiyun 0xF927082E, 0x04C9FEAB, 0x01D30964, 0xFA95FD3D,
136*4882a593Smuzhiyun 0x0000082E, 0x00002000, 0x00002000, 0x00000000
137*4882a593Smuzhiyun };
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun /* 709 RGB to YCbCr */
140*4882a593Smuzhiyun static const u32 rgb_to_ycbcr_709[8] = {
141*4882a593Smuzhiyun 0xF891082F, 0x0367FF40, 0x01280B71, 0xF9B1FE20,
142*4882a593Smuzhiyun 0x0000082F, 0x00002000, 0x00002000, 0x00000000
143*4882a593Smuzhiyun };
144*4882a593Smuzhiyun
tvout_read(struct sti_tvout * tvout,int offset)145*4882a593Smuzhiyun static u32 tvout_read(struct sti_tvout *tvout, int offset)
146*4882a593Smuzhiyun {
147*4882a593Smuzhiyun return readl(tvout->regs + offset);
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
tvout_write(struct sti_tvout * tvout,u32 val,int offset)150*4882a593Smuzhiyun static void tvout_write(struct sti_tvout *tvout, u32 val, int offset)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun writel(val, tvout->regs + offset);
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun /**
156*4882a593Smuzhiyun * Set the clipping mode of a VIP
157*4882a593Smuzhiyun *
158*4882a593Smuzhiyun * @tvout: tvout structure
159*4882a593Smuzhiyun * @reg: register to set
160*4882a593Smuzhiyun * @cr_r: red chroma or red order
161*4882a593Smuzhiyun * @y_g: y or green order
162*4882a593Smuzhiyun * @cb_b: blue chroma or blue order
163*4882a593Smuzhiyun */
tvout_vip_set_color_order(struct sti_tvout * tvout,int reg,u32 cr_r,u32 y_g,u32 cb_b)164*4882a593Smuzhiyun static void tvout_vip_set_color_order(struct sti_tvout *tvout, int reg,
165*4882a593Smuzhiyun u32 cr_r, u32 y_g, u32 cb_b)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun u32 val = tvout_read(tvout, reg);
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun val &= ~(TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_R_SHIFT);
170*4882a593Smuzhiyun val &= ~(TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_G_SHIFT);
171*4882a593Smuzhiyun val &= ~(TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_B_SHIFT);
172*4882a593Smuzhiyun val |= cr_r << TVO_VIP_REORDER_R_SHIFT;
173*4882a593Smuzhiyun val |= y_g << TVO_VIP_REORDER_G_SHIFT;
174*4882a593Smuzhiyun val |= cb_b << TVO_VIP_REORDER_B_SHIFT;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun tvout_write(tvout, val, reg);
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun /**
180*4882a593Smuzhiyun * Set the clipping mode of a VIP
181*4882a593Smuzhiyun *
182*4882a593Smuzhiyun * @tvout: tvout structure
183*4882a593Smuzhiyun * @reg: register to set
184*4882a593Smuzhiyun * @range: clipping range
185*4882a593Smuzhiyun */
tvout_vip_set_clip_mode(struct sti_tvout * tvout,int reg,u32 range)186*4882a593Smuzhiyun static void tvout_vip_set_clip_mode(struct sti_tvout *tvout, int reg, u32 range)
187*4882a593Smuzhiyun {
188*4882a593Smuzhiyun u32 val = tvout_read(tvout, reg);
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun val &= ~(TVO_VIP_CLIP_MASK << TVO_VIP_CLIP_SHIFT);
191*4882a593Smuzhiyun val |= range << TVO_VIP_CLIP_SHIFT;
192*4882a593Smuzhiyun tvout_write(tvout, val, reg);
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun /**
196*4882a593Smuzhiyun * Set the rounded value of a VIP
197*4882a593Smuzhiyun *
198*4882a593Smuzhiyun * @tvout: tvout structure
199*4882a593Smuzhiyun * @reg: register to set
200*4882a593Smuzhiyun * @rnd: rounded val per component
201*4882a593Smuzhiyun */
tvout_vip_set_rnd(struct sti_tvout * tvout,int reg,u32 rnd)202*4882a593Smuzhiyun static void tvout_vip_set_rnd(struct sti_tvout *tvout, int reg, u32 rnd)
203*4882a593Smuzhiyun {
204*4882a593Smuzhiyun u32 val = tvout_read(tvout, reg);
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun val &= ~(TVO_VIP_RND_MASK << TVO_VIP_RND_SHIFT);
207*4882a593Smuzhiyun val |= rnd << TVO_VIP_RND_SHIFT;
208*4882a593Smuzhiyun tvout_write(tvout, val, reg);
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun /**
212*4882a593Smuzhiyun * Select the VIP input
213*4882a593Smuzhiyun *
214*4882a593Smuzhiyun * @tvout: tvout structure
215*4882a593Smuzhiyun * @reg: register to set
216*4882a593Smuzhiyun * @main_path: main or auxiliary path
217*4882a593Smuzhiyun * @video_out: selected_input (main/aux + conv)
218*4882a593Smuzhiyun */
tvout_vip_set_sel_input(struct sti_tvout * tvout,int reg,bool main_path,enum sti_tvout_video_out_type video_out)219*4882a593Smuzhiyun static void tvout_vip_set_sel_input(struct sti_tvout *tvout,
220*4882a593Smuzhiyun int reg,
221*4882a593Smuzhiyun bool main_path,
222*4882a593Smuzhiyun enum sti_tvout_video_out_type video_out)
223*4882a593Smuzhiyun {
224*4882a593Smuzhiyun u32 sel_input;
225*4882a593Smuzhiyun u32 val = tvout_read(tvout, reg);
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun if (main_path)
228*4882a593Smuzhiyun sel_input = TVO_VIP_SEL_INPUT_MAIN;
229*4882a593Smuzhiyun else
230*4882a593Smuzhiyun sel_input = TVO_VIP_SEL_INPUT_AUX;
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun switch (video_out) {
233*4882a593Smuzhiyun case STI_TVOUT_VIDEO_OUT_RGB:
234*4882a593Smuzhiyun sel_input |= TVO_VIP_SEL_INPUT_BYPASSED;
235*4882a593Smuzhiyun break;
236*4882a593Smuzhiyun case STI_TVOUT_VIDEO_OUT_YUV:
237*4882a593Smuzhiyun sel_input &= ~TVO_VIP_SEL_INPUT_BYPASSED;
238*4882a593Smuzhiyun break;
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun /* on stih407 chip the sel_input bypass mode logic is inverted */
242*4882a593Smuzhiyun sel_input = sel_input ^ TVO_VIP_SEL_INPUT_BYPASS_MASK;
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun val &= ~TVO_VIP_SEL_INPUT_MASK;
245*4882a593Smuzhiyun val |= sel_input;
246*4882a593Smuzhiyun tvout_write(tvout, val, reg);
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun /**
250*4882a593Smuzhiyun * Select the input video signed or unsigned
251*4882a593Smuzhiyun *
252*4882a593Smuzhiyun * @tvout: tvout structure
253*4882a593Smuzhiyun * @reg: register to set
254*4882a593Smuzhiyun * @in_vid_fmt: used video input format
255*4882a593Smuzhiyun */
tvout_vip_set_in_vid_fmt(struct sti_tvout * tvout,int reg,u32 in_vid_fmt)256*4882a593Smuzhiyun static void tvout_vip_set_in_vid_fmt(struct sti_tvout *tvout,
257*4882a593Smuzhiyun int reg, u32 in_vid_fmt)
258*4882a593Smuzhiyun {
259*4882a593Smuzhiyun u32 val = tvout_read(tvout, reg);
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun val &= ~TVO_IN_FMT_SIGNED;
262*4882a593Smuzhiyun val |= in_vid_fmt;
263*4882a593Smuzhiyun tvout_write(tvout, val, reg);
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun /**
267*4882a593Smuzhiyun * Set preformatter matrix
268*4882a593Smuzhiyun *
269*4882a593Smuzhiyun * @tvout: tvout structure
270*4882a593Smuzhiyun * @mode: display mode structure
271*4882a593Smuzhiyun */
tvout_preformatter_set_matrix(struct sti_tvout * tvout,struct drm_display_mode * mode)272*4882a593Smuzhiyun static void tvout_preformatter_set_matrix(struct sti_tvout *tvout,
273*4882a593Smuzhiyun struct drm_display_mode *mode)
274*4882a593Smuzhiyun {
275*4882a593Smuzhiyun unsigned int i;
276*4882a593Smuzhiyun const u32 *pf_matrix;
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun if (mode->vdisplay >= TVO_MIN_HD_HEIGHT)
279*4882a593Smuzhiyun pf_matrix = rgb_to_ycbcr_709;
280*4882a593Smuzhiyun else
281*4882a593Smuzhiyun pf_matrix = rgb_to_ycbcr_601;
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun for (i = 0; i < 8; i++) {
284*4882a593Smuzhiyun tvout_write(tvout, *(pf_matrix + i),
285*4882a593Smuzhiyun TVO_CSC_MAIN_M0 + (i * 4));
286*4882a593Smuzhiyun tvout_write(tvout, *(pf_matrix + i),
287*4882a593Smuzhiyun TVO_CSC_AUX_M0 + (i * 4));
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun }
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun /**
292*4882a593Smuzhiyun * Start VIP block for DVO output
293*4882a593Smuzhiyun *
294*4882a593Smuzhiyun * @tvout: pointer on tvout structure
295*4882a593Smuzhiyun * @main_path: true if main path has to be used in the vip configuration
296*4882a593Smuzhiyun * else aux path is used.
297*4882a593Smuzhiyun */
tvout_dvo_start(struct sti_tvout * tvout,bool main_path)298*4882a593Smuzhiyun static void tvout_dvo_start(struct sti_tvout *tvout, bool main_path)
299*4882a593Smuzhiyun {
300*4882a593Smuzhiyun u32 tvo_in_vid_format;
301*4882a593Smuzhiyun int val, tmp;
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun dev_dbg(tvout->dev, "%s\n", __func__);
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun if (main_path) {
306*4882a593Smuzhiyun DRM_DEBUG_DRIVER("main vip for DVO\n");
307*4882a593Smuzhiyun /* Select the input sync for dvo */
308*4882a593Smuzhiyun tmp = TVO_SYNC_MAIN_VTG_SET_REF | VTG_SYNC_ID_DVO;
309*4882a593Smuzhiyun val = tmp << TVO_SYNC_DVO_PAD_VSYNC_SHIFT;
310*4882a593Smuzhiyun val |= tmp << TVO_SYNC_DVO_PAD_HSYNC_SHIFT;
311*4882a593Smuzhiyun val |= tmp;
312*4882a593Smuzhiyun tvout_write(tvout, val, TVO_DVO_SYNC_SEL);
313*4882a593Smuzhiyun tvo_in_vid_format = TVO_MAIN_IN_VID_FORMAT;
314*4882a593Smuzhiyun } else {
315*4882a593Smuzhiyun DRM_DEBUG_DRIVER("aux vip for DVO\n");
316*4882a593Smuzhiyun /* Select the input sync for dvo */
317*4882a593Smuzhiyun tmp = TVO_SYNC_AUX_VTG_SET_REF | VTG_SYNC_ID_DVO;
318*4882a593Smuzhiyun val = tmp << TVO_SYNC_DVO_PAD_VSYNC_SHIFT;
319*4882a593Smuzhiyun val |= tmp << TVO_SYNC_DVO_PAD_HSYNC_SHIFT;
320*4882a593Smuzhiyun val |= tmp;
321*4882a593Smuzhiyun tvout_write(tvout, val, TVO_DVO_SYNC_SEL);
322*4882a593Smuzhiyun tvo_in_vid_format = TVO_AUX_IN_VID_FORMAT;
323*4882a593Smuzhiyun }
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun /* Set color channel order */
326*4882a593Smuzhiyun tvout_vip_set_color_order(tvout, TVO_VIP_DVO,
327*4882a593Smuzhiyun TVO_VIP_REORDER_CR_R_SEL,
328*4882a593Smuzhiyun TVO_VIP_REORDER_Y_G_SEL,
329*4882a593Smuzhiyun TVO_VIP_REORDER_CB_B_SEL);
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun /* Set clipping mode */
332*4882a593Smuzhiyun tvout_vip_set_clip_mode(tvout, TVO_VIP_DVO, TVO_VIP_CLIP_DISABLED);
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun /* Set round mode (rounded to 8-bit per component) */
335*4882a593Smuzhiyun tvout_vip_set_rnd(tvout, TVO_VIP_DVO, TVO_VIP_RND_8BIT_ROUNDED);
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun /* Set input video format */
338*4882a593Smuzhiyun tvout_vip_set_in_vid_fmt(tvout, tvo_in_vid_format, TVO_IN_FMT_SIGNED);
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun /* Input selection */
341*4882a593Smuzhiyun tvout_vip_set_sel_input(tvout, TVO_VIP_DVO, main_path,
342*4882a593Smuzhiyun STI_TVOUT_VIDEO_OUT_RGB);
343*4882a593Smuzhiyun }
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun /**
346*4882a593Smuzhiyun * Start VIP block for HDMI output
347*4882a593Smuzhiyun *
348*4882a593Smuzhiyun * @tvout: pointer on tvout structure
349*4882a593Smuzhiyun * @main_path: true if main path has to be used in the vip configuration
350*4882a593Smuzhiyun * else aux path is used.
351*4882a593Smuzhiyun */
tvout_hdmi_start(struct sti_tvout * tvout,bool main_path)352*4882a593Smuzhiyun static void tvout_hdmi_start(struct sti_tvout *tvout, bool main_path)
353*4882a593Smuzhiyun {
354*4882a593Smuzhiyun u32 tvo_in_vid_format;
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun dev_dbg(tvout->dev, "%s\n", __func__);
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun if (main_path) {
359*4882a593Smuzhiyun DRM_DEBUG_DRIVER("main vip for hdmi\n");
360*4882a593Smuzhiyun /* select the input sync for hdmi */
361*4882a593Smuzhiyun tvout_write(tvout,
362*4882a593Smuzhiyun TVO_SYNC_MAIN_VTG_SET_REF | VTG_SYNC_ID_HDMI,
363*4882a593Smuzhiyun TVO_HDMI_SYNC_SEL);
364*4882a593Smuzhiyun tvo_in_vid_format = TVO_MAIN_IN_VID_FORMAT;
365*4882a593Smuzhiyun } else {
366*4882a593Smuzhiyun DRM_DEBUG_DRIVER("aux vip for hdmi\n");
367*4882a593Smuzhiyun /* select the input sync for hdmi */
368*4882a593Smuzhiyun tvout_write(tvout,
369*4882a593Smuzhiyun TVO_SYNC_AUX_VTG_SET_REF | VTG_SYNC_ID_HDMI,
370*4882a593Smuzhiyun TVO_HDMI_SYNC_SEL);
371*4882a593Smuzhiyun tvo_in_vid_format = TVO_AUX_IN_VID_FORMAT;
372*4882a593Smuzhiyun }
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun /* set color channel order */
375*4882a593Smuzhiyun tvout_vip_set_color_order(tvout, TVO_VIP_HDMI,
376*4882a593Smuzhiyun TVO_VIP_REORDER_CR_R_SEL,
377*4882a593Smuzhiyun TVO_VIP_REORDER_Y_G_SEL,
378*4882a593Smuzhiyun TVO_VIP_REORDER_CB_B_SEL);
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun /* set clipping mode */
381*4882a593Smuzhiyun tvout_vip_set_clip_mode(tvout, TVO_VIP_HDMI, TVO_VIP_CLIP_DISABLED);
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun /* set round mode (rounded to 8-bit per component) */
384*4882a593Smuzhiyun tvout_vip_set_rnd(tvout, TVO_VIP_HDMI, TVO_VIP_RND_8BIT_ROUNDED);
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun /* set input video format */
387*4882a593Smuzhiyun tvout_vip_set_in_vid_fmt(tvout, tvo_in_vid_format, TVO_IN_FMT_SIGNED);
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun /* input selection */
390*4882a593Smuzhiyun tvout_vip_set_sel_input(tvout, TVO_VIP_HDMI, main_path,
391*4882a593Smuzhiyun STI_TVOUT_VIDEO_OUT_RGB);
392*4882a593Smuzhiyun }
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun /**
395*4882a593Smuzhiyun * Start HDF VIP and HD DAC
396*4882a593Smuzhiyun *
397*4882a593Smuzhiyun * @tvout: pointer on tvout structure
398*4882a593Smuzhiyun * @main_path: true if main path has to be used in the vip configuration
399*4882a593Smuzhiyun * else aux path is used.
400*4882a593Smuzhiyun */
tvout_hda_start(struct sti_tvout * tvout,bool main_path)401*4882a593Smuzhiyun static void tvout_hda_start(struct sti_tvout *tvout, bool main_path)
402*4882a593Smuzhiyun {
403*4882a593Smuzhiyun u32 tvo_in_vid_format;
404*4882a593Smuzhiyun int val;
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun dev_dbg(tvout->dev, "%s\n", __func__);
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun if (main_path) {
409*4882a593Smuzhiyun DRM_DEBUG_DRIVER("main vip for HDF\n");
410*4882a593Smuzhiyun /* Select the input sync for HD analog and HD DCS */
411*4882a593Smuzhiyun val = TVO_SYNC_MAIN_VTG_SET_REF | VTG_SYNC_ID_HDDCS;
412*4882a593Smuzhiyun val = val << TVO_SYNC_HD_DCS_SHIFT;
413*4882a593Smuzhiyun val |= TVO_SYNC_MAIN_VTG_SET_REF | VTG_SYNC_ID_HDF;
414*4882a593Smuzhiyun tvout_write(tvout, val, TVO_HD_SYNC_SEL);
415*4882a593Smuzhiyun tvo_in_vid_format = TVO_MAIN_IN_VID_FORMAT;
416*4882a593Smuzhiyun } else {
417*4882a593Smuzhiyun DRM_DEBUG_DRIVER("aux vip for HDF\n");
418*4882a593Smuzhiyun /* Select the input sync for HD analog and HD DCS */
419*4882a593Smuzhiyun val = TVO_SYNC_AUX_VTG_SET_REF | VTG_SYNC_ID_HDDCS;
420*4882a593Smuzhiyun val = val << TVO_SYNC_HD_DCS_SHIFT;
421*4882a593Smuzhiyun val |= TVO_SYNC_AUX_VTG_SET_REF | VTG_SYNC_ID_HDF;
422*4882a593Smuzhiyun tvout_write(tvout, val, TVO_HD_SYNC_SEL);
423*4882a593Smuzhiyun tvo_in_vid_format = TVO_AUX_IN_VID_FORMAT;
424*4882a593Smuzhiyun }
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun /* set color channel order */
427*4882a593Smuzhiyun tvout_vip_set_color_order(tvout, TVO_VIP_HDF,
428*4882a593Smuzhiyun TVO_VIP_REORDER_CR_R_SEL,
429*4882a593Smuzhiyun TVO_VIP_REORDER_Y_G_SEL,
430*4882a593Smuzhiyun TVO_VIP_REORDER_CB_B_SEL);
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun /* set clipping mode */
433*4882a593Smuzhiyun tvout_vip_set_clip_mode(tvout, TVO_VIP_HDF, TVO_VIP_CLIP_DISABLED);
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun /* set round mode (rounded to 10-bit per component) */
436*4882a593Smuzhiyun tvout_vip_set_rnd(tvout, TVO_VIP_HDF, TVO_VIP_RND_10BIT_ROUNDED);
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun /* Set input video format */
439*4882a593Smuzhiyun tvout_vip_set_in_vid_fmt(tvout, tvo_in_vid_format, TVO_IN_FMT_SIGNED);
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun /* Input selection */
442*4882a593Smuzhiyun tvout_vip_set_sel_input(tvout, TVO_VIP_HDF, main_path,
443*4882a593Smuzhiyun STI_TVOUT_VIDEO_OUT_YUV);
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun /* power up HD DAC */
446*4882a593Smuzhiyun tvout_write(tvout, 0, TVO_HD_DAC_CFG_OFF);
447*4882a593Smuzhiyun }
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \
450*4882a593Smuzhiyun readl(tvout->regs + reg))
451*4882a593Smuzhiyun
tvout_dbg_vip(struct seq_file * s,int val)452*4882a593Smuzhiyun static void tvout_dbg_vip(struct seq_file *s, int val)
453*4882a593Smuzhiyun {
454*4882a593Smuzhiyun int r, g, b, tmp, mask;
455*4882a593Smuzhiyun char *const reorder[] = {"Y_G", "Cb_B", "Cr_R"};
456*4882a593Smuzhiyun char *const clipping[] = {"No", "EAV/SAV", "Limited range RGB/Y",
457*4882a593Smuzhiyun "Limited range Cb/Cr", "decided by register"};
458*4882a593Smuzhiyun char *const round[] = {"8-bit", "10-bit", "12-bit"};
459*4882a593Smuzhiyun char *const input_sel[] = {"Main (color matrix enabled)",
460*4882a593Smuzhiyun "Main (color matrix by-passed)",
461*4882a593Smuzhiyun "", "", "", "", "", "",
462*4882a593Smuzhiyun "Aux (color matrix enabled)",
463*4882a593Smuzhiyun "Aux (color matrix by-passed)",
464*4882a593Smuzhiyun "", "", "", "", "", "Force value"};
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun seq_putc(s, '\t');
467*4882a593Smuzhiyun mask = TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_R_SHIFT;
468*4882a593Smuzhiyun r = (val & mask) >> TVO_VIP_REORDER_R_SHIFT;
469*4882a593Smuzhiyun mask = TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_G_SHIFT;
470*4882a593Smuzhiyun g = (val & mask) >> TVO_VIP_REORDER_G_SHIFT;
471*4882a593Smuzhiyun mask = TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_B_SHIFT;
472*4882a593Smuzhiyun b = (val & mask) >> TVO_VIP_REORDER_B_SHIFT;
473*4882a593Smuzhiyun seq_printf(s, "%-24s %s->%s %s->%s %s->%s\n", "Reorder:",
474*4882a593Smuzhiyun reorder[r], reorder[TVO_VIP_REORDER_CR_R_SEL],
475*4882a593Smuzhiyun reorder[g], reorder[TVO_VIP_REORDER_Y_G_SEL],
476*4882a593Smuzhiyun reorder[b], reorder[TVO_VIP_REORDER_CB_B_SEL]);
477*4882a593Smuzhiyun seq_puts(s, "\t\t\t\t\t");
478*4882a593Smuzhiyun mask = TVO_VIP_CLIP_MASK << TVO_VIP_CLIP_SHIFT;
479*4882a593Smuzhiyun tmp = (val & mask) >> TVO_VIP_CLIP_SHIFT;
480*4882a593Smuzhiyun seq_printf(s, "%-24s %s\n", "Clipping:", clipping[tmp]);
481*4882a593Smuzhiyun seq_puts(s, "\t\t\t\t\t");
482*4882a593Smuzhiyun mask = TVO_VIP_RND_MASK << TVO_VIP_RND_SHIFT;
483*4882a593Smuzhiyun tmp = (val & mask) >> TVO_VIP_RND_SHIFT;
484*4882a593Smuzhiyun seq_printf(s, "%-24s input data rounded to %s per component\n",
485*4882a593Smuzhiyun "Round:", round[tmp]);
486*4882a593Smuzhiyun seq_puts(s, "\t\t\t\t\t");
487*4882a593Smuzhiyun tmp = (val & TVO_VIP_SEL_INPUT_MASK);
488*4882a593Smuzhiyun seq_printf(s, "%-24s %s", "Input selection:", input_sel[tmp]);
489*4882a593Smuzhiyun }
490*4882a593Smuzhiyun
tvout_dbg_hd_dac_cfg(struct seq_file * s,int val)491*4882a593Smuzhiyun static void tvout_dbg_hd_dac_cfg(struct seq_file *s, int val)
492*4882a593Smuzhiyun {
493*4882a593Smuzhiyun seq_printf(s, "\t%-24s %s", "HD DAC:",
494*4882a593Smuzhiyun val & 1 ? "disabled" : "enabled");
495*4882a593Smuzhiyun }
496*4882a593Smuzhiyun
tvout_dbg_show(struct seq_file * s,void * data)497*4882a593Smuzhiyun static int tvout_dbg_show(struct seq_file *s, void *data)
498*4882a593Smuzhiyun {
499*4882a593Smuzhiyun struct drm_info_node *node = s->private;
500*4882a593Smuzhiyun struct sti_tvout *tvout = (struct sti_tvout *)node->info_ent->data;
501*4882a593Smuzhiyun struct drm_crtc *crtc;
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun seq_printf(s, "TVOUT: (vaddr = 0x%p)", tvout->regs);
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun seq_puts(s, "\n\n HDMI encoder: ");
506*4882a593Smuzhiyun crtc = tvout->hdmi->crtc;
507*4882a593Smuzhiyun if (crtc) {
508*4882a593Smuzhiyun seq_printf(s, "connected to %s path",
509*4882a593Smuzhiyun sti_crtc_is_main(crtc) ? "main" : "aux");
510*4882a593Smuzhiyun DBGFS_DUMP(TVO_HDMI_SYNC_SEL);
511*4882a593Smuzhiyun DBGFS_DUMP(TVO_VIP_HDMI);
512*4882a593Smuzhiyun tvout_dbg_vip(s, readl(tvout->regs + TVO_VIP_HDMI));
513*4882a593Smuzhiyun } else {
514*4882a593Smuzhiyun seq_puts(s, "disabled");
515*4882a593Smuzhiyun }
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun seq_puts(s, "\n\n DVO encoder: ");
518*4882a593Smuzhiyun crtc = tvout->dvo->crtc;
519*4882a593Smuzhiyun if (crtc) {
520*4882a593Smuzhiyun seq_printf(s, "connected to %s path",
521*4882a593Smuzhiyun sti_crtc_is_main(crtc) ? "main" : "aux");
522*4882a593Smuzhiyun DBGFS_DUMP(TVO_DVO_SYNC_SEL);
523*4882a593Smuzhiyun DBGFS_DUMP(TVO_DVO_CONFIG);
524*4882a593Smuzhiyun DBGFS_DUMP(TVO_VIP_DVO);
525*4882a593Smuzhiyun tvout_dbg_vip(s, readl(tvout->regs + TVO_VIP_DVO));
526*4882a593Smuzhiyun } else {
527*4882a593Smuzhiyun seq_puts(s, "disabled");
528*4882a593Smuzhiyun }
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun seq_puts(s, "\n\n HDA encoder: ");
531*4882a593Smuzhiyun crtc = tvout->hda->crtc;
532*4882a593Smuzhiyun if (crtc) {
533*4882a593Smuzhiyun seq_printf(s, "connected to %s path",
534*4882a593Smuzhiyun sti_crtc_is_main(crtc) ? "main" : "aux");
535*4882a593Smuzhiyun DBGFS_DUMP(TVO_HD_SYNC_SEL);
536*4882a593Smuzhiyun DBGFS_DUMP(TVO_HD_DAC_CFG_OFF);
537*4882a593Smuzhiyun tvout_dbg_hd_dac_cfg(s,
538*4882a593Smuzhiyun readl(tvout->regs + TVO_HD_DAC_CFG_OFF));
539*4882a593Smuzhiyun DBGFS_DUMP(TVO_VIP_HDF);
540*4882a593Smuzhiyun tvout_dbg_vip(s, readl(tvout->regs + TVO_VIP_HDF));
541*4882a593Smuzhiyun } else {
542*4882a593Smuzhiyun seq_puts(s, "disabled");
543*4882a593Smuzhiyun }
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun seq_puts(s, "\n\n main path configuration");
546*4882a593Smuzhiyun DBGFS_DUMP(TVO_CSC_MAIN_M0);
547*4882a593Smuzhiyun DBGFS_DUMP(TVO_CSC_MAIN_M1);
548*4882a593Smuzhiyun DBGFS_DUMP(TVO_CSC_MAIN_M2);
549*4882a593Smuzhiyun DBGFS_DUMP(TVO_CSC_MAIN_M3);
550*4882a593Smuzhiyun DBGFS_DUMP(TVO_CSC_MAIN_M4);
551*4882a593Smuzhiyun DBGFS_DUMP(TVO_CSC_MAIN_M5);
552*4882a593Smuzhiyun DBGFS_DUMP(TVO_CSC_MAIN_M6);
553*4882a593Smuzhiyun DBGFS_DUMP(TVO_CSC_MAIN_M7);
554*4882a593Smuzhiyun DBGFS_DUMP(TVO_MAIN_IN_VID_FORMAT);
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun seq_puts(s, "\n\n auxiliary path configuration");
557*4882a593Smuzhiyun DBGFS_DUMP(TVO_CSC_AUX_M0);
558*4882a593Smuzhiyun DBGFS_DUMP(TVO_CSC_AUX_M2);
559*4882a593Smuzhiyun DBGFS_DUMP(TVO_CSC_AUX_M3);
560*4882a593Smuzhiyun DBGFS_DUMP(TVO_CSC_AUX_M4);
561*4882a593Smuzhiyun DBGFS_DUMP(TVO_CSC_AUX_M5);
562*4882a593Smuzhiyun DBGFS_DUMP(TVO_CSC_AUX_M6);
563*4882a593Smuzhiyun DBGFS_DUMP(TVO_CSC_AUX_M7);
564*4882a593Smuzhiyun DBGFS_DUMP(TVO_AUX_IN_VID_FORMAT);
565*4882a593Smuzhiyun seq_putc(s, '\n');
566*4882a593Smuzhiyun return 0;
567*4882a593Smuzhiyun }
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun static struct drm_info_list tvout_debugfs_files[] = {
570*4882a593Smuzhiyun { "tvout", tvout_dbg_show, 0, NULL },
571*4882a593Smuzhiyun };
572*4882a593Smuzhiyun
tvout_debugfs_init(struct sti_tvout * tvout,struct drm_minor * minor)573*4882a593Smuzhiyun static void tvout_debugfs_init(struct sti_tvout *tvout, struct drm_minor *minor)
574*4882a593Smuzhiyun {
575*4882a593Smuzhiyun unsigned int i;
576*4882a593Smuzhiyun
577*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(tvout_debugfs_files); i++)
578*4882a593Smuzhiyun tvout_debugfs_files[i].data = tvout;
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun drm_debugfs_create_files(tvout_debugfs_files,
581*4882a593Smuzhiyun ARRAY_SIZE(tvout_debugfs_files),
582*4882a593Smuzhiyun minor->debugfs_root, minor);
583*4882a593Smuzhiyun }
584*4882a593Smuzhiyun
sti_tvout_encoder_dpms(struct drm_encoder * encoder,int mode)585*4882a593Smuzhiyun static void sti_tvout_encoder_dpms(struct drm_encoder *encoder, int mode)
586*4882a593Smuzhiyun {
587*4882a593Smuzhiyun }
588*4882a593Smuzhiyun
sti_tvout_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)589*4882a593Smuzhiyun static void sti_tvout_encoder_mode_set(struct drm_encoder *encoder,
590*4882a593Smuzhiyun struct drm_display_mode *mode,
591*4882a593Smuzhiyun struct drm_display_mode *adjusted_mode)
592*4882a593Smuzhiyun {
593*4882a593Smuzhiyun }
594*4882a593Smuzhiyun
sti_tvout_encoder_destroy(struct drm_encoder * encoder)595*4882a593Smuzhiyun static void sti_tvout_encoder_destroy(struct drm_encoder *encoder)
596*4882a593Smuzhiyun {
597*4882a593Smuzhiyun struct sti_tvout_encoder *sti_encoder = to_sti_tvout_encoder(encoder);
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun drm_encoder_cleanup(encoder);
600*4882a593Smuzhiyun kfree(sti_encoder);
601*4882a593Smuzhiyun }
602*4882a593Smuzhiyun
sti_tvout_late_register(struct drm_encoder * encoder)603*4882a593Smuzhiyun static int sti_tvout_late_register(struct drm_encoder *encoder)
604*4882a593Smuzhiyun {
605*4882a593Smuzhiyun struct sti_tvout *tvout = to_sti_tvout(encoder);
606*4882a593Smuzhiyun
607*4882a593Smuzhiyun if (tvout->debugfs_registered)
608*4882a593Smuzhiyun return 0;
609*4882a593Smuzhiyun
610*4882a593Smuzhiyun tvout_debugfs_init(tvout, encoder->dev->primary);
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun tvout->debugfs_registered = true;
613*4882a593Smuzhiyun return 0;
614*4882a593Smuzhiyun }
615*4882a593Smuzhiyun
sti_tvout_early_unregister(struct drm_encoder * encoder)616*4882a593Smuzhiyun static void sti_tvout_early_unregister(struct drm_encoder *encoder)
617*4882a593Smuzhiyun {
618*4882a593Smuzhiyun struct sti_tvout *tvout = to_sti_tvout(encoder);
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun if (!tvout->debugfs_registered)
621*4882a593Smuzhiyun return;
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun tvout->debugfs_registered = false;
624*4882a593Smuzhiyun }
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun static const struct drm_encoder_funcs sti_tvout_encoder_funcs = {
627*4882a593Smuzhiyun .destroy = sti_tvout_encoder_destroy,
628*4882a593Smuzhiyun .late_register = sti_tvout_late_register,
629*4882a593Smuzhiyun .early_unregister = sti_tvout_early_unregister,
630*4882a593Smuzhiyun };
631*4882a593Smuzhiyun
sti_dvo_encoder_enable(struct drm_encoder * encoder)632*4882a593Smuzhiyun static void sti_dvo_encoder_enable(struct drm_encoder *encoder)
633*4882a593Smuzhiyun {
634*4882a593Smuzhiyun struct sti_tvout *tvout = to_sti_tvout(encoder);
635*4882a593Smuzhiyun
636*4882a593Smuzhiyun tvout_preformatter_set_matrix(tvout, &encoder->crtc->mode);
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun tvout_dvo_start(tvout, sti_crtc_is_main(encoder->crtc));
639*4882a593Smuzhiyun }
640*4882a593Smuzhiyun
sti_dvo_encoder_disable(struct drm_encoder * encoder)641*4882a593Smuzhiyun static void sti_dvo_encoder_disable(struct drm_encoder *encoder)
642*4882a593Smuzhiyun {
643*4882a593Smuzhiyun struct sti_tvout *tvout = to_sti_tvout(encoder);
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun /* Reset VIP register */
646*4882a593Smuzhiyun tvout_write(tvout, 0x0, TVO_VIP_DVO);
647*4882a593Smuzhiyun }
648*4882a593Smuzhiyun
649*4882a593Smuzhiyun static const struct drm_encoder_helper_funcs sti_dvo_encoder_helper_funcs = {
650*4882a593Smuzhiyun .dpms = sti_tvout_encoder_dpms,
651*4882a593Smuzhiyun .mode_set = sti_tvout_encoder_mode_set,
652*4882a593Smuzhiyun .enable = sti_dvo_encoder_enable,
653*4882a593Smuzhiyun .disable = sti_dvo_encoder_disable,
654*4882a593Smuzhiyun };
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun static struct drm_encoder *
sti_tvout_create_dvo_encoder(struct drm_device * dev,struct sti_tvout * tvout)657*4882a593Smuzhiyun sti_tvout_create_dvo_encoder(struct drm_device *dev,
658*4882a593Smuzhiyun struct sti_tvout *tvout)
659*4882a593Smuzhiyun {
660*4882a593Smuzhiyun struct sti_tvout_encoder *encoder;
661*4882a593Smuzhiyun struct drm_encoder *drm_encoder;
662*4882a593Smuzhiyun
663*4882a593Smuzhiyun encoder = devm_kzalloc(tvout->dev, sizeof(*encoder), GFP_KERNEL);
664*4882a593Smuzhiyun if (!encoder)
665*4882a593Smuzhiyun return NULL;
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun encoder->tvout = tvout;
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun drm_encoder = &encoder->encoder;
670*4882a593Smuzhiyun
671*4882a593Smuzhiyun drm_encoder->possible_crtcs = ENCODER_CRTC_MASK;
672*4882a593Smuzhiyun
673*4882a593Smuzhiyun drm_encoder_init(dev, drm_encoder,
674*4882a593Smuzhiyun &sti_tvout_encoder_funcs, DRM_MODE_ENCODER_LVDS,
675*4882a593Smuzhiyun NULL);
676*4882a593Smuzhiyun
677*4882a593Smuzhiyun drm_encoder_helper_add(drm_encoder, &sti_dvo_encoder_helper_funcs);
678*4882a593Smuzhiyun
679*4882a593Smuzhiyun return drm_encoder;
680*4882a593Smuzhiyun }
681*4882a593Smuzhiyun
sti_hda_encoder_enable(struct drm_encoder * encoder)682*4882a593Smuzhiyun static void sti_hda_encoder_enable(struct drm_encoder *encoder)
683*4882a593Smuzhiyun {
684*4882a593Smuzhiyun struct sti_tvout *tvout = to_sti_tvout(encoder);
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun tvout_preformatter_set_matrix(tvout, &encoder->crtc->mode);
687*4882a593Smuzhiyun
688*4882a593Smuzhiyun tvout_hda_start(tvout, sti_crtc_is_main(encoder->crtc));
689*4882a593Smuzhiyun }
690*4882a593Smuzhiyun
sti_hda_encoder_disable(struct drm_encoder * encoder)691*4882a593Smuzhiyun static void sti_hda_encoder_disable(struct drm_encoder *encoder)
692*4882a593Smuzhiyun {
693*4882a593Smuzhiyun struct sti_tvout *tvout = to_sti_tvout(encoder);
694*4882a593Smuzhiyun
695*4882a593Smuzhiyun /* reset VIP register */
696*4882a593Smuzhiyun tvout_write(tvout, 0x0, TVO_VIP_HDF);
697*4882a593Smuzhiyun
698*4882a593Smuzhiyun /* power down HD DAC */
699*4882a593Smuzhiyun tvout_write(tvout, 1, TVO_HD_DAC_CFG_OFF);
700*4882a593Smuzhiyun }
701*4882a593Smuzhiyun
702*4882a593Smuzhiyun static const struct drm_encoder_helper_funcs sti_hda_encoder_helper_funcs = {
703*4882a593Smuzhiyun .dpms = sti_tvout_encoder_dpms,
704*4882a593Smuzhiyun .mode_set = sti_tvout_encoder_mode_set,
705*4882a593Smuzhiyun .commit = sti_hda_encoder_enable,
706*4882a593Smuzhiyun .disable = sti_hda_encoder_disable,
707*4882a593Smuzhiyun };
708*4882a593Smuzhiyun
sti_tvout_create_hda_encoder(struct drm_device * dev,struct sti_tvout * tvout)709*4882a593Smuzhiyun static struct drm_encoder *sti_tvout_create_hda_encoder(struct drm_device *dev,
710*4882a593Smuzhiyun struct sti_tvout *tvout)
711*4882a593Smuzhiyun {
712*4882a593Smuzhiyun struct sti_tvout_encoder *encoder;
713*4882a593Smuzhiyun struct drm_encoder *drm_encoder;
714*4882a593Smuzhiyun
715*4882a593Smuzhiyun encoder = devm_kzalloc(tvout->dev, sizeof(*encoder), GFP_KERNEL);
716*4882a593Smuzhiyun if (!encoder)
717*4882a593Smuzhiyun return NULL;
718*4882a593Smuzhiyun
719*4882a593Smuzhiyun encoder->tvout = tvout;
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun drm_encoder = &encoder->encoder;
722*4882a593Smuzhiyun
723*4882a593Smuzhiyun drm_encoder->possible_crtcs = ENCODER_CRTC_MASK;
724*4882a593Smuzhiyun
725*4882a593Smuzhiyun drm_encoder_init(dev, drm_encoder,
726*4882a593Smuzhiyun &sti_tvout_encoder_funcs, DRM_MODE_ENCODER_DAC, NULL);
727*4882a593Smuzhiyun
728*4882a593Smuzhiyun drm_encoder_helper_add(drm_encoder, &sti_hda_encoder_helper_funcs);
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun return drm_encoder;
731*4882a593Smuzhiyun }
732*4882a593Smuzhiyun
sti_hdmi_encoder_enable(struct drm_encoder * encoder)733*4882a593Smuzhiyun static void sti_hdmi_encoder_enable(struct drm_encoder *encoder)
734*4882a593Smuzhiyun {
735*4882a593Smuzhiyun struct sti_tvout *tvout = to_sti_tvout(encoder);
736*4882a593Smuzhiyun
737*4882a593Smuzhiyun tvout_preformatter_set_matrix(tvout, &encoder->crtc->mode);
738*4882a593Smuzhiyun
739*4882a593Smuzhiyun tvout_hdmi_start(tvout, sti_crtc_is_main(encoder->crtc));
740*4882a593Smuzhiyun }
741*4882a593Smuzhiyun
sti_hdmi_encoder_disable(struct drm_encoder * encoder)742*4882a593Smuzhiyun static void sti_hdmi_encoder_disable(struct drm_encoder *encoder)
743*4882a593Smuzhiyun {
744*4882a593Smuzhiyun struct sti_tvout *tvout = to_sti_tvout(encoder);
745*4882a593Smuzhiyun
746*4882a593Smuzhiyun /* reset VIP register */
747*4882a593Smuzhiyun tvout_write(tvout, 0x0, TVO_VIP_HDMI);
748*4882a593Smuzhiyun }
749*4882a593Smuzhiyun
750*4882a593Smuzhiyun static const struct drm_encoder_helper_funcs sti_hdmi_encoder_helper_funcs = {
751*4882a593Smuzhiyun .dpms = sti_tvout_encoder_dpms,
752*4882a593Smuzhiyun .mode_set = sti_tvout_encoder_mode_set,
753*4882a593Smuzhiyun .commit = sti_hdmi_encoder_enable,
754*4882a593Smuzhiyun .disable = sti_hdmi_encoder_disable,
755*4882a593Smuzhiyun };
756*4882a593Smuzhiyun
sti_tvout_create_hdmi_encoder(struct drm_device * dev,struct sti_tvout * tvout)757*4882a593Smuzhiyun static struct drm_encoder *sti_tvout_create_hdmi_encoder(struct drm_device *dev,
758*4882a593Smuzhiyun struct sti_tvout *tvout)
759*4882a593Smuzhiyun {
760*4882a593Smuzhiyun struct sti_tvout_encoder *encoder;
761*4882a593Smuzhiyun struct drm_encoder *drm_encoder;
762*4882a593Smuzhiyun
763*4882a593Smuzhiyun encoder = devm_kzalloc(tvout->dev, sizeof(*encoder), GFP_KERNEL);
764*4882a593Smuzhiyun if (!encoder)
765*4882a593Smuzhiyun return NULL;
766*4882a593Smuzhiyun
767*4882a593Smuzhiyun encoder->tvout = tvout;
768*4882a593Smuzhiyun
769*4882a593Smuzhiyun drm_encoder = &encoder->encoder;
770*4882a593Smuzhiyun
771*4882a593Smuzhiyun drm_encoder->possible_crtcs = ENCODER_CRTC_MASK;
772*4882a593Smuzhiyun
773*4882a593Smuzhiyun drm_encoder_init(dev, drm_encoder,
774*4882a593Smuzhiyun &sti_tvout_encoder_funcs, DRM_MODE_ENCODER_TMDS, NULL);
775*4882a593Smuzhiyun
776*4882a593Smuzhiyun drm_encoder_helper_add(drm_encoder, &sti_hdmi_encoder_helper_funcs);
777*4882a593Smuzhiyun
778*4882a593Smuzhiyun return drm_encoder;
779*4882a593Smuzhiyun }
780*4882a593Smuzhiyun
sti_tvout_create_encoders(struct drm_device * dev,struct sti_tvout * tvout)781*4882a593Smuzhiyun static void sti_tvout_create_encoders(struct drm_device *dev,
782*4882a593Smuzhiyun struct sti_tvout *tvout)
783*4882a593Smuzhiyun {
784*4882a593Smuzhiyun tvout->hdmi = sti_tvout_create_hdmi_encoder(dev, tvout);
785*4882a593Smuzhiyun tvout->hda = sti_tvout_create_hda_encoder(dev, tvout);
786*4882a593Smuzhiyun tvout->dvo = sti_tvout_create_dvo_encoder(dev, tvout);
787*4882a593Smuzhiyun
788*4882a593Smuzhiyun tvout->hdmi->possible_clones = drm_encoder_mask(tvout->hdmi) |
789*4882a593Smuzhiyun drm_encoder_mask(tvout->hda) | drm_encoder_mask(tvout->dvo);
790*4882a593Smuzhiyun tvout->hda->possible_clones = drm_encoder_mask(tvout->hdmi) |
791*4882a593Smuzhiyun drm_encoder_mask(tvout->hda) | drm_encoder_mask(tvout->dvo);
792*4882a593Smuzhiyun tvout->dvo->possible_clones = drm_encoder_mask(tvout->hdmi) |
793*4882a593Smuzhiyun drm_encoder_mask(tvout->hda) | drm_encoder_mask(tvout->dvo);
794*4882a593Smuzhiyun }
795*4882a593Smuzhiyun
sti_tvout_destroy_encoders(struct sti_tvout * tvout)796*4882a593Smuzhiyun static void sti_tvout_destroy_encoders(struct sti_tvout *tvout)
797*4882a593Smuzhiyun {
798*4882a593Smuzhiyun if (tvout->hdmi)
799*4882a593Smuzhiyun drm_encoder_cleanup(tvout->hdmi);
800*4882a593Smuzhiyun tvout->hdmi = NULL;
801*4882a593Smuzhiyun
802*4882a593Smuzhiyun if (tvout->hda)
803*4882a593Smuzhiyun drm_encoder_cleanup(tvout->hda);
804*4882a593Smuzhiyun tvout->hda = NULL;
805*4882a593Smuzhiyun
806*4882a593Smuzhiyun if (tvout->dvo)
807*4882a593Smuzhiyun drm_encoder_cleanup(tvout->dvo);
808*4882a593Smuzhiyun tvout->dvo = NULL;
809*4882a593Smuzhiyun }
810*4882a593Smuzhiyun
sti_tvout_bind(struct device * dev,struct device * master,void * data)811*4882a593Smuzhiyun static int sti_tvout_bind(struct device *dev, struct device *master, void *data)
812*4882a593Smuzhiyun {
813*4882a593Smuzhiyun struct sti_tvout *tvout = dev_get_drvdata(dev);
814*4882a593Smuzhiyun struct drm_device *drm_dev = data;
815*4882a593Smuzhiyun
816*4882a593Smuzhiyun tvout->drm_dev = drm_dev;
817*4882a593Smuzhiyun
818*4882a593Smuzhiyun sti_tvout_create_encoders(drm_dev, tvout);
819*4882a593Smuzhiyun
820*4882a593Smuzhiyun return 0;
821*4882a593Smuzhiyun }
822*4882a593Smuzhiyun
sti_tvout_unbind(struct device * dev,struct device * master,void * data)823*4882a593Smuzhiyun static void sti_tvout_unbind(struct device *dev, struct device *master,
824*4882a593Smuzhiyun void *data)
825*4882a593Smuzhiyun {
826*4882a593Smuzhiyun struct sti_tvout *tvout = dev_get_drvdata(dev);
827*4882a593Smuzhiyun
828*4882a593Smuzhiyun sti_tvout_destroy_encoders(tvout);
829*4882a593Smuzhiyun }
830*4882a593Smuzhiyun
831*4882a593Smuzhiyun static const struct component_ops sti_tvout_ops = {
832*4882a593Smuzhiyun .bind = sti_tvout_bind,
833*4882a593Smuzhiyun .unbind = sti_tvout_unbind,
834*4882a593Smuzhiyun };
835*4882a593Smuzhiyun
sti_tvout_probe(struct platform_device * pdev)836*4882a593Smuzhiyun static int sti_tvout_probe(struct platform_device *pdev)
837*4882a593Smuzhiyun {
838*4882a593Smuzhiyun struct device *dev = &pdev->dev;
839*4882a593Smuzhiyun struct device_node *node = dev->of_node;
840*4882a593Smuzhiyun struct sti_tvout *tvout;
841*4882a593Smuzhiyun struct resource *res;
842*4882a593Smuzhiyun
843*4882a593Smuzhiyun DRM_INFO("%s\n", __func__);
844*4882a593Smuzhiyun
845*4882a593Smuzhiyun if (!node)
846*4882a593Smuzhiyun return -ENODEV;
847*4882a593Smuzhiyun
848*4882a593Smuzhiyun tvout = devm_kzalloc(dev, sizeof(*tvout), GFP_KERNEL);
849*4882a593Smuzhiyun if (!tvout)
850*4882a593Smuzhiyun return -ENOMEM;
851*4882a593Smuzhiyun
852*4882a593Smuzhiyun tvout->dev = dev;
853*4882a593Smuzhiyun
854*4882a593Smuzhiyun /* get memory resources */
855*4882a593Smuzhiyun res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tvout-reg");
856*4882a593Smuzhiyun if (!res) {
857*4882a593Smuzhiyun DRM_ERROR("Invalid glue resource\n");
858*4882a593Smuzhiyun return -ENOMEM;
859*4882a593Smuzhiyun }
860*4882a593Smuzhiyun tvout->regs = devm_ioremap(dev, res->start, resource_size(res));
861*4882a593Smuzhiyun if (!tvout->regs)
862*4882a593Smuzhiyun return -ENOMEM;
863*4882a593Smuzhiyun
864*4882a593Smuzhiyun /* get reset resources */
865*4882a593Smuzhiyun tvout->reset = devm_reset_control_get(dev, "tvout");
866*4882a593Smuzhiyun /* take tvout out of reset */
867*4882a593Smuzhiyun if (!IS_ERR(tvout->reset))
868*4882a593Smuzhiyun reset_control_deassert(tvout->reset);
869*4882a593Smuzhiyun
870*4882a593Smuzhiyun platform_set_drvdata(pdev, tvout);
871*4882a593Smuzhiyun
872*4882a593Smuzhiyun return component_add(dev, &sti_tvout_ops);
873*4882a593Smuzhiyun }
874*4882a593Smuzhiyun
sti_tvout_remove(struct platform_device * pdev)875*4882a593Smuzhiyun static int sti_tvout_remove(struct platform_device *pdev)
876*4882a593Smuzhiyun {
877*4882a593Smuzhiyun component_del(&pdev->dev, &sti_tvout_ops);
878*4882a593Smuzhiyun return 0;
879*4882a593Smuzhiyun }
880*4882a593Smuzhiyun
881*4882a593Smuzhiyun static const struct of_device_id tvout_of_match[] = {
882*4882a593Smuzhiyun { .compatible = "st,stih407-tvout", },
883*4882a593Smuzhiyun { /* end node */ }
884*4882a593Smuzhiyun };
885*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, tvout_of_match);
886*4882a593Smuzhiyun
887*4882a593Smuzhiyun struct platform_driver sti_tvout_driver = {
888*4882a593Smuzhiyun .driver = {
889*4882a593Smuzhiyun .name = "sti-tvout",
890*4882a593Smuzhiyun .owner = THIS_MODULE,
891*4882a593Smuzhiyun .of_match_table = tvout_of_match,
892*4882a593Smuzhiyun },
893*4882a593Smuzhiyun .probe = sti_tvout_probe,
894*4882a593Smuzhiyun .remove = sti_tvout_remove,
895*4882a593Smuzhiyun };
896*4882a593Smuzhiyun
897*4882a593Smuzhiyun MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
898*4882a593Smuzhiyun MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
899*4882a593Smuzhiyun MODULE_LICENSE("GPL");
900