1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) STMicroelectronics SA 2014 4*4882a593Smuzhiyun * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _STI_HDMI_H_ 8*4882a593Smuzhiyun #define _STI_HDMI_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/hdmi.h> 11*4882a593Smuzhiyun #include <linux/platform_device.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <media/cec-notifier.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include <drm/drm_modes.h> 16*4882a593Smuzhiyun #include <drm/drm_property.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define HDMI_STA 0x0010 19*4882a593Smuzhiyun #define HDMI_STA_DLL_LCK BIT(5) 20*4882a593Smuzhiyun #define HDMI_STA_HOT_PLUG BIT(4) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun struct sti_hdmi; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun struct hdmi_phy_ops { 25*4882a593Smuzhiyun bool (*start)(struct sti_hdmi *hdmi); 26*4882a593Smuzhiyun void (*stop)(struct sti_hdmi *hdmi); 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun struct hdmi_audio_params { 30*4882a593Smuzhiyun bool enabled; 31*4882a593Smuzhiyun unsigned int sample_width; 32*4882a593Smuzhiyun unsigned int sample_rate; 33*4882a593Smuzhiyun struct hdmi_audio_infoframe cea; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun static const struct drm_prop_enum_list colorspace_mode_names[] = { 37*4882a593Smuzhiyun { HDMI_COLORSPACE_RGB, "rgb" }, 38*4882a593Smuzhiyun { HDMI_COLORSPACE_YUV422, "yuv422" }, 39*4882a593Smuzhiyun { HDMI_COLORSPACE_YUV444, "yuv444" }, 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define DEFAULT_COLORSPACE_MODE HDMI_COLORSPACE_RGB 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /** 45*4882a593Smuzhiyun * STI hdmi structure 46*4882a593Smuzhiyun * 47*4882a593Smuzhiyun * @dev: driver device 48*4882a593Smuzhiyun * @drm_dev: pointer to drm device 49*4882a593Smuzhiyun * @mode: current display mode selected 50*4882a593Smuzhiyun * @regs: hdmi register 51*4882a593Smuzhiyun * @syscfg: syscfg register for pll rejection configuration 52*4882a593Smuzhiyun * @clk_pix: hdmi pixel clock 53*4882a593Smuzhiyun * @clk_tmds: hdmi tmds clock 54*4882a593Smuzhiyun * @clk_phy: hdmi phy clock 55*4882a593Smuzhiyun * @clk_audio: hdmi audio clock 56*4882a593Smuzhiyun * @irq: hdmi interrupt number 57*4882a593Smuzhiyun * @irq_status: interrupt status register 58*4882a593Smuzhiyun * @phy_ops: phy start/stop operations 59*4882a593Smuzhiyun * @enabled: true if hdmi is enabled else false 60*4882a593Smuzhiyun * @hpd: hot plug detect status 61*4882a593Smuzhiyun * @wait_event: wait event 62*4882a593Smuzhiyun * @event_received: wait event status 63*4882a593Smuzhiyun * @reset: reset control of the hdmi phy 64*4882a593Smuzhiyun * @ddc_adapt: i2c ddc adapter 65*4882a593Smuzhiyun * @colorspace: current colorspace selected 66*4882a593Smuzhiyun * @hdmi_monitor: true if HDMI monitor detected else DVI monitor assumed 67*4882a593Smuzhiyun * @audio_pdev: ASoC hdmi-codec platform device 68*4882a593Smuzhiyun * @audio: hdmi audio parameters. 69*4882a593Smuzhiyun * @drm_connector: hdmi connector 70*4882a593Smuzhiyun * @notifier: hotplug detect notifier 71*4882a593Smuzhiyun */ 72*4882a593Smuzhiyun struct sti_hdmi { 73*4882a593Smuzhiyun struct device dev; 74*4882a593Smuzhiyun struct drm_device *drm_dev; 75*4882a593Smuzhiyun struct drm_display_mode mode; 76*4882a593Smuzhiyun void __iomem *regs; 77*4882a593Smuzhiyun void __iomem *syscfg; 78*4882a593Smuzhiyun struct clk *clk_pix; 79*4882a593Smuzhiyun struct clk *clk_tmds; 80*4882a593Smuzhiyun struct clk *clk_phy; 81*4882a593Smuzhiyun struct clk *clk_audio; 82*4882a593Smuzhiyun int irq; 83*4882a593Smuzhiyun u32 irq_status; 84*4882a593Smuzhiyun struct hdmi_phy_ops *phy_ops; 85*4882a593Smuzhiyun bool enabled; 86*4882a593Smuzhiyun bool hpd; 87*4882a593Smuzhiyun wait_queue_head_t wait_event; 88*4882a593Smuzhiyun bool event_received; 89*4882a593Smuzhiyun struct reset_control *reset; 90*4882a593Smuzhiyun struct i2c_adapter *ddc_adapt; 91*4882a593Smuzhiyun enum hdmi_colorspace colorspace; 92*4882a593Smuzhiyun bool hdmi_monitor; 93*4882a593Smuzhiyun struct platform_device *audio_pdev; 94*4882a593Smuzhiyun struct hdmi_audio_params audio; 95*4882a593Smuzhiyun struct drm_connector *drm_connector; 96*4882a593Smuzhiyun struct cec_notifier *notifier; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun u32 hdmi_read(struct sti_hdmi *hdmi, int offset); 100*4882a593Smuzhiyun void hdmi_write(struct sti_hdmi *hdmi, u32 val, int offset); 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /** 103*4882a593Smuzhiyun * hdmi phy config structure 104*4882a593Smuzhiyun * 105*4882a593Smuzhiyun * A pointer to an array of these structures is passed to a TMDS (HDMI) output 106*4882a593Smuzhiyun * via the control interface to provide board and SoC specific 107*4882a593Smuzhiyun * configurations of the HDMI PHY. Each entry in the array specifies a hardware 108*4882a593Smuzhiyun * specific configuration for a given TMDS clock frequency range. 109*4882a593Smuzhiyun * 110*4882a593Smuzhiyun * @min_tmds_freq: Lower bound of TMDS clock frequency this entry applies to 111*4882a593Smuzhiyun * @max_tmds_freq: Upper bound of TMDS clock frequency this entry applies to 112*4882a593Smuzhiyun * @config: SoC specific register configuration 113*4882a593Smuzhiyun */ 114*4882a593Smuzhiyun struct hdmi_phy_config { 115*4882a593Smuzhiyun u32 min_tmds_freq; 116*4882a593Smuzhiyun u32 max_tmds_freq; 117*4882a593Smuzhiyun u32 config[4]; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #endif 121