xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/sti/sti_crtc.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) STMicroelectronics SA 2014
4*4882a593Smuzhiyun  * Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
5*4882a593Smuzhiyun  *          Fabien Dessenne <fabien.dessenne@st.com>
6*4882a593Smuzhiyun  *          for STMicroelectronics.
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/clk.h>
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <drm/drm_atomic.h>
12*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
13*4882a593Smuzhiyun #include <drm/drm_device.h>
14*4882a593Smuzhiyun #include <drm/drm_plane_helper.h>
15*4882a593Smuzhiyun #include <drm/drm_print.h>
16*4882a593Smuzhiyun #include <drm/drm_probe_helper.h>
17*4882a593Smuzhiyun #include <drm/drm_vblank.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #include "sti_compositor.h"
20*4882a593Smuzhiyun #include "sti_crtc.h"
21*4882a593Smuzhiyun #include "sti_drv.h"
22*4882a593Smuzhiyun #include "sti_vid.h"
23*4882a593Smuzhiyun #include "sti_vtg.h"
24*4882a593Smuzhiyun 
sti_crtc_atomic_enable(struct drm_crtc * crtc,struct drm_crtc_state * old_state)25*4882a593Smuzhiyun static void sti_crtc_atomic_enable(struct drm_crtc *crtc,
26*4882a593Smuzhiyun 				   struct drm_crtc_state *old_state)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun 	struct sti_mixer *mixer = to_sti_mixer(crtc);
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun 	DRM_DEBUG_DRIVER("\n");
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun 	mixer->status = STI_MIXER_READY;
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun 	drm_crtc_vblank_on(crtc);
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun 
sti_crtc_atomic_disable(struct drm_crtc * crtc,struct drm_crtc_state * old_state)37*4882a593Smuzhiyun static void sti_crtc_atomic_disable(struct drm_crtc *crtc,
38*4882a593Smuzhiyun 				    struct drm_crtc_state *old_state)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun 	struct sti_mixer *mixer = to_sti_mixer(crtc);
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun 	DRM_DEBUG_DRIVER("\n");
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun 	mixer->status = STI_MIXER_DISABLING;
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 	drm_crtc_wait_one_vblank(crtc);
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun static int
sti_crtc_mode_set(struct drm_crtc * crtc,struct drm_display_mode * mode)50*4882a593Smuzhiyun sti_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun 	struct sti_mixer *mixer = to_sti_mixer(crtc);
53*4882a593Smuzhiyun 	struct device *dev = mixer->dev;
54*4882a593Smuzhiyun 	struct sti_compositor *compo = dev_get_drvdata(dev);
55*4882a593Smuzhiyun 	struct clk *compo_clk, *pix_clk;
56*4882a593Smuzhiyun 	int rate = mode->clock * 1000;
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 	DRM_DEBUG_KMS("CRTC:%d (%s) mode: (%s)\n",
59*4882a593Smuzhiyun 		      crtc->base.id, sti_mixer_to_str(mixer), mode->name);
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 	DRM_DEBUG_KMS(DRM_MODE_FMT "\n", DRM_MODE_ARG(mode));
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun 	if (mixer->id == STI_MIXER_MAIN) {
64*4882a593Smuzhiyun 		compo_clk = compo->clk_compo_main;
65*4882a593Smuzhiyun 		pix_clk = compo->clk_pix_main;
66*4882a593Smuzhiyun 	} else {
67*4882a593Smuzhiyun 		compo_clk = compo->clk_compo_aux;
68*4882a593Smuzhiyun 		pix_clk = compo->clk_pix_aux;
69*4882a593Smuzhiyun 	}
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 	/* Prepare and enable the compo IP clock */
72*4882a593Smuzhiyun 	if (clk_prepare_enable(compo_clk)) {
73*4882a593Smuzhiyun 		DRM_INFO("Failed to prepare/enable compositor clk\n");
74*4882a593Smuzhiyun 		goto compo_error;
75*4882a593Smuzhiyun 	}
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 	/* Set rate and prepare/enable pixel clock */
78*4882a593Smuzhiyun 	if (clk_set_rate(pix_clk, rate) < 0) {
79*4882a593Smuzhiyun 		DRM_ERROR("Cannot set rate (%dHz) for pix clk\n", rate);
80*4882a593Smuzhiyun 		goto pix_error;
81*4882a593Smuzhiyun 	}
82*4882a593Smuzhiyun 	if (clk_prepare_enable(pix_clk)) {
83*4882a593Smuzhiyun 		DRM_ERROR("Failed to prepare/enable pix clk\n");
84*4882a593Smuzhiyun 		goto pix_error;
85*4882a593Smuzhiyun 	}
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 	sti_vtg_set_config(compo->vtg[mixer->id], &crtc->mode);
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 	if (sti_mixer_active_video_area(mixer, &crtc->mode)) {
90*4882a593Smuzhiyun 		DRM_ERROR("Can't set active video area\n");
91*4882a593Smuzhiyun 		goto mixer_error;
92*4882a593Smuzhiyun 	}
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	return 0;
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun mixer_error:
97*4882a593Smuzhiyun 	clk_disable_unprepare(pix_clk);
98*4882a593Smuzhiyun pix_error:
99*4882a593Smuzhiyun 	clk_disable_unprepare(compo_clk);
100*4882a593Smuzhiyun compo_error:
101*4882a593Smuzhiyun 	return -EINVAL;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun 
sti_crtc_disable(struct drm_crtc * crtc)104*4882a593Smuzhiyun static void sti_crtc_disable(struct drm_crtc *crtc)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun 	struct sti_mixer *mixer = to_sti_mixer(crtc);
107*4882a593Smuzhiyun 	struct device *dev = mixer->dev;
108*4882a593Smuzhiyun 	struct sti_compositor *compo = dev_get_drvdata(dev);
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	DRM_DEBUG_KMS("CRTC:%d (%s)\n", crtc->base.id, sti_mixer_to_str(mixer));
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	/* Disable Background */
113*4882a593Smuzhiyun 	sti_mixer_set_background_status(mixer, false);
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	drm_crtc_vblank_off(crtc);
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	/* Disable pixel clock and compo IP clocks */
118*4882a593Smuzhiyun 	if (mixer->id == STI_MIXER_MAIN) {
119*4882a593Smuzhiyun 		clk_disable_unprepare(compo->clk_pix_main);
120*4882a593Smuzhiyun 		clk_disable_unprepare(compo->clk_compo_main);
121*4882a593Smuzhiyun 	} else {
122*4882a593Smuzhiyun 		clk_disable_unprepare(compo->clk_pix_aux);
123*4882a593Smuzhiyun 		clk_disable_unprepare(compo->clk_compo_aux);
124*4882a593Smuzhiyun 	}
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	mixer->status = STI_MIXER_DISABLED;
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun static void
sti_crtc_mode_set_nofb(struct drm_crtc * crtc)130*4882a593Smuzhiyun sti_crtc_mode_set_nofb(struct drm_crtc *crtc)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun 	sti_crtc_mode_set(crtc, &crtc->state->adjusted_mode);
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun 
sti_crtc_atomic_flush(struct drm_crtc * crtc,struct drm_crtc_state * old_crtc_state)135*4882a593Smuzhiyun static void sti_crtc_atomic_flush(struct drm_crtc *crtc,
136*4882a593Smuzhiyun 				  struct drm_crtc_state *old_crtc_state)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun 	struct drm_device *drm_dev = crtc->dev;
139*4882a593Smuzhiyun 	struct sti_mixer *mixer = to_sti_mixer(crtc);
140*4882a593Smuzhiyun 	struct sti_compositor *compo = dev_get_drvdata(mixer->dev);
141*4882a593Smuzhiyun 	struct drm_plane *p;
142*4882a593Smuzhiyun 	struct drm_pending_vblank_event *event;
143*4882a593Smuzhiyun 	unsigned long flags;
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	DRM_DEBUG_DRIVER("\n");
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	/* perform plane actions */
148*4882a593Smuzhiyun 	list_for_each_entry(p, &drm_dev->mode_config.plane_list, head) {
149*4882a593Smuzhiyun 		struct sti_plane *plane = to_sti_plane(p);
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 		switch (plane->status) {
152*4882a593Smuzhiyun 		case STI_PLANE_UPDATED:
153*4882a593Smuzhiyun 			/* ignore update for other CRTC */
154*4882a593Smuzhiyun 			if (p->state->crtc != crtc)
155*4882a593Smuzhiyun 				continue;
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 			/* update planes tag as updated */
158*4882a593Smuzhiyun 			DRM_DEBUG_DRIVER("update plane %s\n",
159*4882a593Smuzhiyun 					 sti_plane_to_str(plane));
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 			if (sti_mixer_set_plane_depth(mixer, plane)) {
162*4882a593Smuzhiyun 				DRM_ERROR("Cannot set plane %s depth\n",
163*4882a593Smuzhiyun 					  sti_plane_to_str(plane));
164*4882a593Smuzhiyun 				break;
165*4882a593Smuzhiyun 			}
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 			if (sti_mixer_set_plane_status(mixer, plane, true)) {
168*4882a593Smuzhiyun 				DRM_ERROR("Cannot enable plane %s at mixer\n",
169*4882a593Smuzhiyun 					  sti_plane_to_str(plane));
170*4882a593Smuzhiyun 				break;
171*4882a593Smuzhiyun 			}
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 			/* if plane is HQVDP_0 then commit the vid[0] */
174*4882a593Smuzhiyun 			if (plane->desc == STI_HQVDP_0)
175*4882a593Smuzhiyun 				sti_vid_commit(compo->vid[0], p->state);
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 			plane->status = STI_PLANE_READY;
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 			break;
180*4882a593Smuzhiyun 		case STI_PLANE_DISABLING:
181*4882a593Smuzhiyun 			/* disabling sequence for planes tag as disabling */
182*4882a593Smuzhiyun 			DRM_DEBUG_DRIVER("disable plane %s from mixer\n",
183*4882a593Smuzhiyun 					 sti_plane_to_str(plane));
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 			if (sti_mixer_set_plane_status(mixer, plane, false)) {
186*4882a593Smuzhiyun 				DRM_ERROR("Cannot disable plane %s at mixer\n",
187*4882a593Smuzhiyun 					  sti_plane_to_str(plane));
188*4882a593Smuzhiyun 				continue;
189*4882a593Smuzhiyun 			}
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 			if (plane->desc == STI_CURSOR)
192*4882a593Smuzhiyun 				/* tag plane status for disabled */
193*4882a593Smuzhiyun 				plane->status = STI_PLANE_DISABLED;
194*4882a593Smuzhiyun 			else
195*4882a593Smuzhiyun 				/* tag plane status for flushing */
196*4882a593Smuzhiyun 				plane->status = STI_PLANE_FLUSHING;
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 			/* if plane is HQVDP_0 then disable the vid[0] */
199*4882a593Smuzhiyun 			if (plane->desc == STI_HQVDP_0)
200*4882a593Smuzhiyun 				sti_vid_disable(compo->vid[0]);
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 			break;
203*4882a593Smuzhiyun 		default:
204*4882a593Smuzhiyun 			/* Other status case are not handled */
205*4882a593Smuzhiyun 			break;
206*4882a593Smuzhiyun 		}
207*4882a593Smuzhiyun 	}
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 	event = crtc->state->event;
210*4882a593Smuzhiyun 	if (event) {
211*4882a593Smuzhiyun 		crtc->state->event = NULL;
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun 		spin_lock_irqsave(&crtc->dev->event_lock, flags);
214*4882a593Smuzhiyun 		if (drm_crtc_vblank_get(crtc) == 0)
215*4882a593Smuzhiyun 			drm_crtc_arm_vblank_event(crtc, event);
216*4882a593Smuzhiyun 		else
217*4882a593Smuzhiyun 			drm_crtc_send_vblank_event(crtc, event);
218*4882a593Smuzhiyun 		spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
219*4882a593Smuzhiyun 	}
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun static const struct drm_crtc_helper_funcs sti_crtc_helper_funcs = {
223*4882a593Smuzhiyun 	.mode_set_nofb = sti_crtc_mode_set_nofb,
224*4882a593Smuzhiyun 	.atomic_flush = sti_crtc_atomic_flush,
225*4882a593Smuzhiyun 	.atomic_enable = sti_crtc_atomic_enable,
226*4882a593Smuzhiyun 	.atomic_disable = sti_crtc_atomic_disable,
227*4882a593Smuzhiyun };
228*4882a593Smuzhiyun 
sti_crtc_destroy(struct drm_crtc * crtc)229*4882a593Smuzhiyun static void sti_crtc_destroy(struct drm_crtc *crtc)
230*4882a593Smuzhiyun {
231*4882a593Smuzhiyun 	DRM_DEBUG_KMS("\n");
232*4882a593Smuzhiyun 	drm_crtc_cleanup(crtc);
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun 
sti_crtc_set_property(struct drm_crtc * crtc,struct drm_property * property,uint64_t val)235*4882a593Smuzhiyun static int sti_crtc_set_property(struct drm_crtc *crtc,
236*4882a593Smuzhiyun 				 struct drm_property *property,
237*4882a593Smuzhiyun 				 uint64_t val)
238*4882a593Smuzhiyun {
239*4882a593Smuzhiyun 	DRM_DEBUG_KMS("\n");
240*4882a593Smuzhiyun 	return 0;
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun 
sti_crtc_vblank_cb(struct notifier_block * nb,unsigned long event,void * data)243*4882a593Smuzhiyun int sti_crtc_vblank_cb(struct notifier_block *nb,
244*4882a593Smuzhiyun 		       unsigned long event, void *data)
245*4882a593Smuzhiyun {
246*4882a593Smuzhiyun 	struct sti_compositor *compo;
247*4882a593Smuzhiyun 	struct drm_crtc *crtc = data;
248*4882a593Smuzhiyun 	struct sti_mixer *mixer;
249*4882a593Smuzhiyun 	unsigned int pipe;
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 	pipe = drm_crtc_index(crtc);
252*4882a593Smuzhiyun 	compo = container_of(nb, struct sti_compositor, vtg_vblank_nb[pipe]);
253*4882a593Smuzhiyun 	mixer = compo->mixer[pipe];
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 	if ((event != VTG_TOP_FIELD_EVENT) &&
256*4882a593Smuzhiyun 	    (event != VTG_BOTTOM_FIELD_EVENT)) {
257*4882a593Smuzhiyun 		DRM_ERROR("unknown event: %lu\n", event);
258*4882a593Smuzhiyun 		return -EINVAL;
259*4882a593Smuzhiyun 	}
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun 	drm_crtc_handle_vblank(crtc);
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	if (mixer->status == STI_MIXER_DISABLING) {
264*4882a593Smuzhiyun 		struct drm_plane *p;
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 		/* Disable mixer only if all overlay planes (GDP and VDP)
267*4882a593Smuzhiyun 		 * are disabled */
268*4882a593Smuzhiyun 		list_for_each_entry(p, &crtc->dev->mode_config.plane_list,
269*4882a593Smuzhiyun 				    head) {
270*4882a593Smuzhiyun 			struct sti_plane *plane = to_sti_plane(p);
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun 			if ((plane->desc & STI_PLANE_TYPE_MASK) <= STI_VDP)
273*4882a593Smuzhiyun 				if (plane->status != STI_PLANE_DISABLED)
274*4882a593Smuzhiyun 					return 0;
275*4882a593Smuzhiyun 		}
276*4882a593Smuzhiyun 		sti_crtc_disable(crtc);
277*4882a593Smuzhiyun 	}
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	return 0;
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun 
sti_crtc_enable_vblank(struct drm_crtc * crtc)282*4882a593Smuzhiyun static int sti_crtc_enable_vblank(struct drm_crtc *crtc)
283*4882a593Smuzhiyun {
284*4882a593Smuzhiyun 	struct drm_device *dev = crtc->dev;
285*4882a593Smuzhiyun 	unsigned int pipe = crtc->index;
286*4882a593Smuzhiyun 	struct sti_private *dev_priv = dev->dev_private;
287*4882a593Smuzhiyun 	struct sti_compositor *compo = dev_priv->compo;
288*4882a593Smuzhiyun 	struct notifier_block *vtg_vblank_nb = &compo->vtg_vblank_nb[pipe];
289*4882a593Smuzhiyun 	struct sti_vtg *vtg = compo->vtg[pipe];
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 	DRM_DEBUG_DRIVER("\n");
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun 	if (sti_vtg_register_client(vtg, vtg_vblank_nb, crtc)) {
294*4882a593Smuzhiyun 		DRM_ERROR("Cannot register VTG notifier\n");
295*4882a593Smuzhiyun 		return -EINVAL;
296*4882a593Smuzhiyun 	}
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun 	return 0;
299*4882a593Smuzhiyun }
300*4882a593Smuzhiyun 
sti_crtc_disable_vblank(struct drm_crtc * crtc)301*4882a593Smuzhiyun static void sti_crtc_disable_vblank(struct drm_crtc *crtc)
302*4882a593Smuzhiyun {
303*4882a593Smuzhiyun 	struct drm_device *drm_dev = crtc->dev;
304*4882a593Smuzhiyun 	unsigned int pipe = crtc->index;
305*4882a593Smuzhiyun 	struct sti_private *priv = drm_dev->dev_private;
306*4882a593Smuzhiyun 	struct sti_compositor *compo = priv->compo;
307*4882a593Smuzhiyun 	struct notifier_block *vtg_vblank_nb = &compo->vtg_vblank_nb[pipe];
308*4882a593Smuzhiyun 	struct sti_vtg *vtg = compo->vtg[pipe];
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun 	DRM_DEBUG_DRIVER("\n");
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 	if (sti_vtg_unregister_client(vtg, vtg_vblank_nb))
313*4882a593Smuzhiyun 		DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n");
314*4882a593Smuzhiyun }
315*4882a593Smuzhiyun 
sti_crtc_late_register(struct drm_crtc * crtc)316*4882a593Smuzhiyun static int sti_crtc_late_register(struct drm_crtc *crtc)
317*4882a593Smuzhiyun {
318*4882a593Smuzhiyun 	struct sti_mixer *mixer = to_sti_mixer(crtc);
319*4882a593Smuzhiyun 	struct sti_compositor *compo = dev_get_drvdata(mixer->dev);
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun 	if (drm_crtc_index(crtc) == 0)
322*4882a593Smuzhiyun 		sti_compositor_debugfs_init(compo, crtc->dev->primary);
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun 	return 0;
325*4882a593Smuzhiyun }
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun static const struct drm_crtc_funcs sti_crtc_funcs = {
328*4882a593Smuzhiyun 	.set_config = drm_atomic_helper_set_config,
329*4882a593Smuzhiyun 	.page_flip = drm_atomic_helper_page_flip,
330*4882a593Smuzhiyun 	.destroy = sti_crtc_destroy,
331*4882a593Smuzhiyun 	.set_property = sti_crtc_set_property,
332*4882a593Smuzhiyun 	.reset = drm_atomic_helper_crtc_reset,
333*4882a593Smuzhiyun 	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
334*4882a593Smuzhiyun 	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
335*4882a593Smuzhiyun 	.late_register = sti_crtc_late_register,
336*4882a593Smuzhiyun 	.enable_vblank = sti_crtc_enable_vblank,
337*4882a593Smuzhiyun 	.disable_vblank = sti_crtc_disable_vblank,
338*4882a593Smuzhiyun };
339*4882a593Smuzhiyun 
sti_crtc_is_main(struct drm_crtc * crtc)340*4882a593Smuzhiyun bool sti_crtc_is_main(struct drm_crtc *crtc)
341*4882a593Smuzhiyun {
342*4882a593Smuzhiyun 	struct sti_mixer *mixer = to_sti_mixer(crtc);
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun 	if (mixer->id == STI_MIXER_MAIN)
345*4882a593Smuzhiyun 		return true;
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun 	return false;
348*4882a593Smuzhiyun }
349*4882a593Smuzhiyun 
sti_crtc_init(struct drm_device * drm_dev,struct sti_mixer * mixer,struct drm_plane * primary,struct drm_plane * cursor)350*4882a593Smuzhiyun int sti_crtc_init(struct drm_device *drm_dev, struct sti_mixer *mixer,
351*4882a593Smuzhiyun 		  struct drm_plane *primary, struct drm_plane *cursor)
352*4882a593Smuzhiyun {
353*4882a593Smuzhiyun 	struct drm_crtc *crtc = &mixer->drm_crtc;
354*4882a593Smuzhiyun 	int res;
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun 	res = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
357*4882a593Smuzhiyun 					&sti_crtc_funcs, NULL);
358*4882a593Smuzhiyun 	if (res) {
359*4882a593Smuzhiyun 		DRM_ERROR("Can't initialize CRTC\n");
360*4882a593Smuzhiyun 		return -EINVAL;
361*4882a593Smuzhiyun 	}
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun 	drm_crtc_helper_add(crtc, &sti_crtc_helper_funcs);
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun 	DRM_DEBUG_DRIVER("drm CRTC:%d mapped to %s\n",
366*4882a593Smuzhiyun 			 crtc->base.id, sti_mixer_to_str(mixer));
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun 	return 0;
369*4882a593Smuzhiyun }
370