1*4882a593Smuzhiyun1. stiH display hardware IP 2*4882a593Smuzhiyun--------------------------- 3*4882a593SmuzhiyunThe STMicroelectronics stiH SoCs use a common chain of HW display IP blocks: 4*4882a593Smuzhiyun- The High Quality Video Display Processor (HQVDP) gets video frames from a 5*4882a593Smuzhiyun video decoder and does high quality video processing, including scaling. 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun- The Compositor is a multiplane, dual-mixer (Main & Aux) digital processor. It 8*4882a593Smuzhiyun has several inputs: 9*4882a593Smuzhiyun - The graphics planes are internally processed by the Generic Display 10*4882a593Smuzhiyun Pipeline (GDP). 11*4882a593Smuzhiyun - The video plug (VID) connects to the HQVDP output. 12*4882a593Smuzhiyun - The cursor handles ... a cursor. 13*4882a593Smuzhiyun- The TV OUT pre-formats (convert, clip, round) the compositor output data 14*4882a593Smuzhiyun- The HDMI / DVO / HD Analog / SD analog IP builds the video signals 15*4882a593Smuzhiyun - DVO (Digital Video Output) handles a 24bits parallel signal 16*4882a593Smuzhiyun - The HD analog signal is typically driven by a YCbCr cable, supporting up to 17*4882a593Smuzhiyun 1080i mode. 18*4882a593Smuzhiyun - The SD analog signal is typically used for legacy TV 19*4882a593Smuzhiyun- The VTG (Video Timing Generators) build Vsync signals used by the other HW IP 20*4882a593SmuzhiyunNote that some stiH drivers support only a subset of thee HW IP. 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun .-------------. .-----------. .-----------. 23*4882a593SmuzhiyunGPU >-------------+GDP Main | | +---+ HDMI +--> HDMI 24*4882a593SmuzhiyunGPU >-------------+GDP mixer+---+ | :===========: 25*4882a593SmuzhiyunGPU >-------------+Cursor | | +---+ DVO +--> 24b// 26*4882a593Smuzhiyun ------- | COMPOSITOR | | TV OUT | :===========: 27*4882a593Smuzhiyun | | | | | +---+ HD analog +--> YCbCr 28*4882a593SmuzhiyunVid >--+ HQVDP +--+VID Aux +---+ | :===========: 29*4882a593Smuzhiyundec | | | mixer| | +---+ SD analog +--> CVBS 30*4882a593Smuzhiyun '-------' '-------------' '-----------' '-----------' 31*4882a593Smuzhiyun .-----------. 32*4882a593Smuzhiyun | main+--> Vsync 33*4882a593Smuzhiyun | VTG | 34*4882a593Smuzhiyun | aux+--> Vsync 35*4882a593Smuzhiyun '-----------' 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun2. DRM / HW mapping 38*4882a593Smuzhiyun------------------- 39*4882a593SmuzhiyunThese IP are mapped to the DRM objects as following: 40*4882a593Smuzhiyun- The CRTCs are mapped to the Compositor Main and Aux Mixers 41*4882a593Smuzhiyun- The Framebuffers and planes are mapped to the Compositor GDP (non video 42*4882a593Smuzhiyun buffers) and to HQVDP+VID (video buffers) 43*4882a593Smuzhiyun- The Cursor is mapped to the Compositor Cursor 44*4882a593Smuzhiyun- The Encoders are mapped to the TVOut 45*4882a593Smuzhiyun- The Bridges/Connectors are mapped to the HDMI / DVO / HD Analog / SD analog 46*4882a593Smuzhiyun 47*4882a593SmuzhiyunFB & planes Cursor CRTC Encoders Bridges/Connectors 48*4882a593Smuzhiyun | | | | | 49*4882a593Smuzhiyun | | | | | 50*4882a593Smuzhiyun | .-------------. | .-----------. .-----------. | 51*4882a593Smuzhiyun +------------> |GDP | Main | | | +-> | | HDMI | <-+ 52*4882a593Smuzhiyun +------------> |GDP v mixer|<+ | | | :===========: | 53*4882a593Smuzhiyun | |Cursor | | | +-> | | DVO | <-+ 54*4882a593Smuzhiyun | ------- | COMPOSITOR | | |TV OUT | | :===========: | 55*4882a593Smuzhiyun | | | | | | | +-> | | HD analog | <-+ 56*4882a593Smuzhiyun +-> | HQVDP | |VID Aux |<+ | | | :===========: | 57*4882a593Smuzhiyun | | | mixer| | +-> | | SD analog | <-+ 58*4882a593Smuzhiyun '-------' '-------------' '-----------' '-----------' 59