1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * Author: Sandy Huang <hjc@rock-chips.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef ROCKCHIP_DRM_LOGO_H 8*4882a593Smuzhiyun #define ROCKCHIP_DRM_LOGO_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include "rockchip_drm_vop.h" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun struct rockchip_drm_mode_set { 13*4882a593Smuzhiyun struct list_head head; 14*4882a593Smuzhiyun struct drm_framebuffer *fb; 15*4882a593Smuzhiyun struct rockchip_drm_sub_dev *sub_dev; 16*4882a593Smuzhiyun struct drm_crtc *crtc; 17*4882a593Smuzhiyun struct drm_display_mode *mode; 18*4882a593Smuzhiyun struct post_csc csc; 19*4882a593Smuzhiyun int clock; 20*4882a593Smuzhiyun int hdisplay; 21*4882a593Smuzhiyun int vdisplay; 22*4882a593Smuzhiyun int vrefresh; 23*4882a593Smuzhiyun int flags; 24*4882a593Smuzhiyun int picture_aspect_ratio; 25*4882a593Smuzhiyun int crtc_hsync_end; 26*4882a593Smuzhiyun int crtc_vsync_end; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun int left_margin; 29*4882a593Smuzhiyun int right_margin; 30*4882a593Smuzhiyun int top_margin; 31*4882a593Smuzhiyun int bottom_margin; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun unsigned int brightness; 34*4882a593Smuzhiyun unsigned int contrast; 35*4882a593Smuzhiyun unsigned int saturation; 36*4882a593Smuzhiyun unsigned int hue; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun bool mode_changed; 39*4882a593Smuzhiyun bool force_output; 40*4882a593Smuzhiyun int ratio; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun void rockchip_drm_show_logo(struct drm_device *drm_dev); 44*4882a593Smuzhiyun void rockchip_free_loader_memory(struct drm_device *drm); 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #endif 47