1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
4 *
5 * Author: Algea Cao <algea.cao@rock-chips.com>
6 */
7
8 #include <linux/clk.h>
9 #include <linux/debugfs.h>
10 #include <linux/delay.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15 #include <linux/reset.h>
16 #include <linux/timer.h>
17 #include <linux/workqueue.h>
18 #include <linux/mfd/rk628.h>
19 #include <linux/phy/phy.h>
20
21 #include <drm/drm_atomic.h>
22 #include <drm/drm_atomic_helper.h>
23 #include <drm/drm_print.h>
24 #include <drm/drm_dp_helper.h>
25 #include <drm/drm_of.h>
26
27 #define REG(x) ((x) + 0x30000)
28 #define HDMI_RX_HDMI_SETUP_CTRL REG(0x0000)
29 #define HOT_PLUG_DETECT_MASK BIT(0)
30 #define HOT_PLUG_DETECT(x) UPDATE(x, 0, 0)
31 #define HDMI_RX_HDMI_OVR_CTRL REG(0x0004)
32 #define HDMI_RX_HDMI_TIMER_CTRL REG(0x0008)
33 #define HDMI_RX_HDMI_RES_OVR REG(0x0010)
34 #define HDMI_RX_HDMI_RES_STS REG(0x0014)
35 #define HDMI_RX_HDMI_PLL_CTRL REG(0x0018)
36 #define HDMI_RX_HDMI_PLL_FRQSET1 REG(0x001c)
37 #define HDMI_RX_HDMI_PLL_FRQSET2 REG(0x0020)
38 #define HDMI_RX_HDMI_PLL_PAR1 REG(0x0024)
39 #define HDMI_RX_HDMI_PLL_PAR2 REG(0x0028)
40 #define HDMI_RX_HDMI_PLL_PAR3 REG(0x002c)
41 #define HDMI_RX_HDMI_PLL_LCK_STS REG(0x0030)
42 #define HDMI_RX_HDMI_CLK_CTRL REG(0x0034)
43 #define HDMI_RX_HDMI_PCB_CTRL REG(0x0038)
44 #define SEL_PIXCLKSRC_MASK GENMASK(19, 18)
45 #define SEL_PIXCLKSRC(x) UPDATE(x, 19, 18)
46 #define HDMI_RX_HDMI_PHS_CTR REG(0x0040)
47 #define HDMI_RX_HDMI_PHS_USED REG(0x0044)
48 #define HDMI_RX_HDMI_MISC_CTRL REG(0x0048)
49 #define HDMI_RX_HDMI_EQOFF_CTRL REG(0x004c)
50 #define HDMI_RX_HDMI_EQGAIN_CTRL REG(0x0050)
51 #define HDMI_RX_HDMI_EQCAL_STS REG(0x0054)
52 #define HDMI_RX_HDMI_EQRESULT REG(0x0058)
53 #define HDMI_RX_HDMI_EQ_MEAS_CTRL REG(0x005c)
54 #define HDMI_RX_HDMI_WR_CFG REG(0x0060)
55 #define HDMI_RX_HDMI_CTRL REG(0x0064)
56 #define HDMI_RX_HDMI_MODE_RECOVER REG(0x0080)
57 #define PREAMBLE_CNT_LIMIT_MASK GENMASK(31, 27)
58 #define PREAMBLE_CNT_LIMIT(x) UPDATE(x, 31, 27)
59 #define OESSCTL3_THR_MASK GENMASK(20, 19)
60 #define OESSCTL3_THR(x) UPDATE(x, 20, 19)
61 #define SPIKE_FILTER_EN_MASK BIT(18)
62 #define SPIKE_FILTER_EN(x) UPDATE(x, 18, 18)
63 #define DVI_MODE_HYST_MASK GENMASK(17, 13)
64 #define DVI_MODE_HYST(x) UPDATE(x, 17, 13)
65 #define HDMI_MODE_HYST_MASK GENMASK(12, 8)
66 #define HDMI_MODE_HYST(x) UPDATE(x, 12, 8)
67 #define HDMI_MODE_MASK GENMASK(7, 6)
68 #define HDMI_MODE(x) UPDATE(x, 7, 6)
69 #define GB_DET_MASK GENMASK(5, 4)
70 #define GB_DET(x) UPDATE(x, 5, 4)
71 #define EESS_OESS_MASK GENMASK(3, 2)
72 #define EESS_OESS(x) UPDATE(x, 3, 2)
73 #define SEL_CTL01_MASK GENMASK(1, 0)
74 #define SEL_CTL01(x) UPDATE(x, 1, 0)
75 #define HDMI_RX_HDMI_ERROR_PROTECT REG(0x0084)
76 #define RG_BLOCK_OFF_MASK BIT(20)
77 #define RG_BLOCK_OFF(x) UPDATE(x, 20, 20)
78 #define BLOCK_OFF_MASK BIT(19)
79 #define BLOCK_OFF(x) UPDATE(x, 19, 19)
80 #define VALID_MODE_MASK GENMASK(18, 16)
81 #define VALID_MODE(x) UPDATE(x, 18, 16)
82 #define CTRL_FILT_SEN_MASK GENMASK(13, 12)
83 #define CTRL_FILT_SEN(x) UPDATE(x, 13, 12)
84 #define VS_FILT_SENS_MASK GENMASK(11, 10)
85 #define VS_FILT_SENS(x) UPDATE(x, 11, 10)
86 #define HS_FILT_SENS_MASK GENMASK(9, 8)
87 #define HS_FILT_SENS(x) UPDATE(x, 9, 8)
88 #define DE_MEASURE_MODE_MASK GENMASK(7, 6)
89 #define DE_MEASURE_MODE(x) UPDATE(x, 7, 6)
90 #define DE_REGEN_MASK BIT(5)
91 #define DE_REGEN(x) UPDATE(x, 5, 5)
92 #define DE_FILTER_SENS_MASK GENMASK(4, 3)
93 #define DE_FILTER_SENS(x) UPDATE(x, 4, 3)
94 #define HDMI_RX_HDMI_ERD_STS REG(0x0088)
95 #define HDMI_RX_HDMI_SYNC_CTRL REG(0x0090)
96 #define VS_POL_ADJ_MODE_MASK GENMASK(4, 3)
97 #define VS_POL_ADJ_MODE(x) UPDATE(x, 4, 3)
98 #define HS_POL_ADJ_MODE_MASK GENMASK(2, 1)
99 #define HS_POL_ADJ_MODE(x) UPDATE(x, 2, 1)
100 #define HDMI_RX_HDMI_CKM_EVLTM REG(0x0094)
101 #define LOCK_HYST_MASK GENMASK(21, 20)
102 #define LOCK_HYST(x) UPDATE(x, 21, 20)
103 #define CLK_HYST_MASK GENMASK(18, 16)
104 #define CLK_HYST(x) UPDATE(x, 18, 16)
105 #define EVAL_TIME_MASK GENMASK(15, 4)
106 #define EVAL_TIME(x) UPDATE(x, 15, 4)
107 #define HDMI_RX_HDMI_CKM_F REG(0x0098)
108 #define HDMIRX_MAXFREQ_MASK GENMASK(31, 16)
109 #define HDMIRX_MAXFREQ(x) UPDATE(x, 31, 16)
110 #define MINFREQ_MASK GENMASK(15, 0)
111 #define MINFREQ(x) UPDATE(x, 15, 0)
112 #define HDMI_RX_HDMI_CKM_RESULT REG(0x009c)
113 #define HDMI_RX_HDMI_PVO_CONFIG REG(0x00a0)
114 #define HDMI_RX_HDMI_RESMPL_CTRL REG(0x00a4)
115 #define MAN_VID_DEREPEAT_MASK GENMASK(4, 1)
116 #define MAN_VID_DEREPEAT(x) UPDATE(x, 4, 1)
117 #define AUTO_DEREPEAT_MASK BIT(0)
118 #define AUTO_DEREPEAT(x) UPDATE(x, 0, 0)
119 #define HDMI_RX_HDMI_DCM_CTRL REG(0x00a8)
120 #define DCM_DEFAULT_PHASE_MASK BIT(18)
121 #define DCM_DEFAULT_PHASE(x) UPDATE(x, 18, 18)
122 #define DCM_COLOUR_DEPTH_SEL_MASK BIT(12)
123 #define DCM_COLOUR_DEPTH_SEL(x) UPDATE(x, 12, 12)
124 #define DCM_COLOUR_DEPTH_MASK GENMASK(11, 8)
125 #define DCM_COLOUR_DEPTH(x) UPDATE(x, 11, 8)
126 #define DCM_GCP_ZERO_FIELDS_MASK GENMASK(5, 2)
127 #define DCM_GCP_ZERO_FIELDS(x) UPDATE(x, 5, 2)
128 #define HDMI_RX_HDMI_VM_CFG_CH_0_1 REG(0x00b0)
129 #define HDMI_RX_HDMI_VM_CFG_CH2 REG(0x00b4)
130 #define HDMI_RX_HDMI_SPARE REG(0x00b8)
131 #define HDMI_RX_HDMI_STS REG(0x00bc)
132 #define HDMI_RX_HDCP_CTRL REG(0x00c0)
133 #define HDCP_ENABLE_MASK BIT(24)
134 #define HDCP_ENABLE(x) UPDATE(x, 24, 24)
135 #define FREEZE_HDCP_FSM_MASK BIT(21)
136 #define FREEZE_HDCP_FSM(x) UPDATE(x, 21, 21)
137 #define FREEZE_HDCP_STATE_MASK GENMASK(20, 15)
138 #define FREEZE_HDCP_STATE(x) UPDATE(x, 20, 15)
139 #define HDCP_CTL_MASK GENMASK(9, 8)
140 #define HDCP_CTL(x) UPDATE(x, 9, 8)
141 #define HDCP_RI_RATE_MASK GENMASK(7, 6)
142 #define HDCP_RI_RATE(x) UPDATE(x, 7, 6)
143 #define KEY_DECRYPT_ENABLE_MASK BIT(1)
144 #define KEY_DECRYPT_ENABLE(x) UPDATE(x, 1, 1)
145 #define HDCP_ENC_EN_MASK BIT(0)
146 #define HDCP_ENC_EN(x) UPDATE(x, 0, 0)
147 #define HDMI_RX_HDCP_SETTINGS REG(0x00c4)
148 #define HDMI_RX_HDCP_SEED REG(0x00c8)
149 #define HDMI_RX_HDCP_BKSV1 REG(0x00cc)
150 #define HDMI_RX_HDCP_BKSV0 REG(0x00d0)
151 #define HDMI_RX_HDCP_KIDX REG(0x00d4)
152 #define HDMI_RX_HDCP_KEY1 REG(0x00d8)
153 #define HDMI_RX_HDCP_KEY0 REG(0x00dc)
154 #define HDMI_RX_HDCP_DBG REG(0x00e0)
155 #define HDMI_RX_HDCP_AKSV1 REG(0x00e4)
156 #define HDMI_RX_HDCP_AKSV0 REG(0x00e8)
157 #define HDMI_RX_HDCP_AN1 REG(0x00ec)
158 #define HDMI_RX_HDCP_AN0 REG(0x00f0)
159 #define HDMI_RX_HDCP_EESS_WOO REG(0x00f4)
160 #define HDMI_RX_HDCP_I2C_TIMEOUT REG(0x00f8)
161 #define HDMI_RX_HDCP_STS REG(0x00fc)
162 #define HDMI_RX_MD_HCTRL1 REG(0x0140)
163 #define HACT_PIX_ITH_MASK GENMASK(10, 8)
164 #define HACT_PIX_ITH(x) UPDATE(x, 10, 8)
165 #define HACT_PIX_SRC_MASK BIT(5)
166 #define HACT_PIX_SRC(x) UPDATE(x, 5, 5)
167 #define HTOT_PIX_SRC_MASK BIT(4)
168 #define HTOT_PIX_SRC(x) UPDATE(x, 4, 4)
169 #define HDMI_RX_MD_HCTRL2 REG(0x0144)
170 #define HS_CLK_ITH_MASK GENMASK(14, 12)
171 #define HS_CLK_ITH(x) UPDATE(x, 14, 12)
172 #define HTOT32_CLK_ITH_MASK GENMASK(9, 8)
173 #define HTOT32_CLK_ITH(x) UPDATE(x, 9, 8)
174 #define VS_ACT_TIME_MASK BIT(5)
175 #define VS_ACT_TIME(x) UPDATE(x, 5, 5)
176 #define HS_ACT_TIME_MASK GENMASK(4, 3)
177 #define HS_ACT_TIME(x) UPDATE(x, 4, 3)
178 #define H_START_POS_MASK GENMASK(1, 0)
179 #define H_START_POS(x) UPDATE(x, 1, 0)
180 #define HDMI_RX_MD_HT0 REG(0x0148)
181 #define HDMI_RX_MD_HT1 REG(0x014c)
182 #define HDMI_RX_MD_HACT_PX REG(0x0150)
183 #define HDMI_RX_MD_HACT_RSV REG(0x0154)
184 #define HDMI_RX_MD_VCTRL REG(0x0158)
185 #define V_OFFS_LIN_MODE_MASK BIT(4)
186 #define V_OFFS_LIN_MODE(x) UPDATE(x, 4, 4)
187 #define V_EDGE_MASK BIT(1)
188 #define V_EDGE(x) UPDATE(x, 1, 1)
189 #define V_MODE_MASK BIT(0)
190 #define V_MODE(x) UPDATE(x, 0, 0)
191 #define HDMI_RX_MD_VSC REG(0x015c)
192 #define HDMI_RX_MD_VTC REG(0x0160)
193 #define HDMI_RX_MD_VOL REG(0x0164)
194 #define HDMI_RX_MD_VAL REG(0x0168)
195 #define HDMI_RX_MD_VTH REG(0x016c)
196 #define VOFS_LIN_ITH_MASK GENMASK(11, 10)
197 #define VOFS_LIN_ITH(x) UPDATE(x, 11, 10)
198 #define VACT_LIN_ITH_MASK GENMASK(9, 8)
199 #define VACT_LIN_ITH(x) UPDATE(x, 9, 8)
200 #define VTOT_LIN_ITH_MASK GENMASK(7, 6)
201 #define VTOT_LIN_ITH(x) UPDATE(x, 7, 6)
202 #define VS_CLK_ITH_MASK GENMASK(5, 3)
203 #define VS_CLK_ITH(x) UPDATE(x, 5, 3)
204 #define VTOT_CLK_ITH_MASK GENMASK(2, 0)
205 #define VTOT_CLK_ITH(x) UPDATE(x, 2, 0)
206 #define HDMI_RX_MD_VTL REG(0x0170)
207 #define HDMI_RX_MD_IL_CTRL REG(0x0174)
208 #define HDMI_RX_MD_IL_SKEW REG(0x0178)
209 #define HDMI_RX_MD_IL_POL REG(0x017c)
210 #define FAFIELDDET_EN_MASK BIT(2)
211 #define FAFIELDDET_EN(x) UPDATE(x, 2, 2)
212 #define FIELD_POL_MODE_MASK GENMASK(1, 0)
213 #define FIELD_POL_MODE(x) UPDATE(x, 1, 0)
214 #define HDMI_RX_MD_STS REG(0x0180)
215 #define HDMI_RX_AUD_CTRL REG(0x0200)
216 #define HDMI_RX_AUD_PLL_CTRL REG(0x0208)
217 #define PLL_LOCK_TOGGLE_DIV_MASK GENMASK(27, 24)
218 #define PLL_LOCK_TOGGLE_DIV(x) UPDATE(x, 27, 24)
219 #define HDMI_RX_AUD_CLK_CTRL REG(0x0214)
220 #define CTS_N_REF_MASK BIT(4)
221 #define CTS_N_REF(x) UPDATE(x, 4, 4)
222 #define HDMI_RX_AUD_CLK_STS REG(0x023c)
223 #define HDMI_RX_AUD_FIFO_CTRL REG(0x0240)
224 #define AFIF_SUBPACKET_DESEL_MASK GENMASK(27, 24)
225 #define AFIF_SUBPACKET_DESEL(x) UPDATE(x, 27, 24)
226 #define AFIF_SUBPACKETS_MASK BIT(16)
227 #define AFIF_SUBPACKETS(x) UPDATE(x, 16, 16)
228 #define MSA_CHANNEL_DESELECT BIT(24)
229 #define HDMI_RX_AUD_FIFO_TH REG(0x0244)
230 #define AFIF_TH_START_MASK GENMASK(26, 18)
231 #define AFIF_TH_START(x) UPDATE(x, 26, 18)
232 #define AFIF_TH_MAX_MASK GENMASK(17, 9)
233 #define AFIF_TH_MAX(x) UPDATE(x, 17, 9)
234 #define AFIF_TH_MIN_MASK GENMASK(8, 0)
235 #define AFIF_TH_MIN(x) UPDATE(x, 8, 0)
236 #define HDMI_RX_AUD_FIFO_FILL_S REG(0x0248)
237 #define HDMI_RX_AUD_FIFO_CLR_MM REG(0x024c)
238 #define HDMI_RX_AUD_FIFO_FILLSTS REG(0x0250)
239 #define HDMI_RX_AUD_CHEXTR_CTRL REG(0x0254)
240 #define AUD_LAYOUT_CTRL(x) UPDATE(x, 1, 0)
241 #define HDMI_RX_AUD_MUTE_CTRL REG(0x0258)
242 #define APPLY_INT_MUTE_MASK BIT(31)
243 #define APPLY_INT_MUTE(x) UPDATE(x, 31, 31)
244 #define APORT_SHDW_CTRL_MASK GENMASK(22, 21)
245 #define APORT_SHDW_CTRL(x) UPDATE(x, 22, 21)
246 #define AUTO_ACLK_MUTE_MASK GENMASK(20, 19)
247 #define AUTO_ACLK_MUTE(x) UPDATE(x, 20, 19)
248 #define AUD_MUTE_SPEED_MASK GENMASK(16, 10)
249 #define AUD_MUTE_SPEED(x) UPDATE(x, 16, 10)
250 #define AUD_AVMUTE_EN_MASK BIT(7)
251 #define AUD_AVMUTE_EN(x) UPDATE(x, 7, 7)
252 #define AUD_MUTE_SEL_MASK GENMASK(6, 5)
253 #define AUD_MUTE_SEL(x) UPDATE(x, 6, 5)
254 #define AUD_MUTE_MODE_MASK GENMASK(4, 3)
255 #define AUD_MUTE_MODE(x) UPDATE(x, 4, 3)
256 #define HDMI_RX_AUD_FIFO_FILLSTS1 REG(0x025c)
257 #define HDMI_RX_AUD_SAO_CTRL REG(0x0260)
258 #define I2S_LPCM_BPCUV_MASK BIT(11)
259 #define I2S_LPCM_BPCUV(x) UPDATE(x, 11, 11)
260 #define I2S_32_16_MASK BIT(0)
261 #define I2S_32_16(x) UPDATE(x, 0, 0)
262 #define HDMI_RX_AUD_PAO_CTRL REG(0x0264)
263 #define PAO_RATE_MASK GENMASK(17, 16)
264 #define PAO_RATE(x) UPDATE(x, 17, 16)
265 #define HDMI_RX_AUD_SPARE REG(0x0268)
266 #define HDMI_RX_AUD_FIFO_STS REG(0x027c)
267 #define HDMI_RX_AUDPLL_GEN_CTS REG(0x0280)
268 #define AUDPLL_CTS_MANUAL(x) UPDATE(x, 19, 0)
269 #define HDMI_RX_AUDPLL_GEN_N REG(0x0284)
270 #define AUDPLL_N_MANUAL(x) UPDATE(x, 19, 0)
271 #define HDMI_RX_AUDPLL_GEN_CTRL_RW1 REG(0x0288)
272 #define HDMI_RX_AUDPLL_GEN_CTRL_RW2 REG(0x028c)
273 #define HDMI_RX_AUDPLL_GEN_CTRL_W1 REG(0x0298)
274 #define HDMI_RX_AUDPLL_GEN_STS_RO1 REG(0x02a0)
275 #define HDMI_RX_AUDPLL_GEN_STS_RO2 REG(0x02a4)
276 #define HDMI_RX_AUDPLL_SC_NDIVCTSTH REG(0x02a8)
277 #define HDMI_RX_AUDPLL_SC_CTS REG(0x02ac)
278 #define HDMI_RX_AUDPLL_SC_N REG(0x02b0)
279 #define HDMI_RX_AUDPLL_SC_CTRL REG(0x02b4)
280 #define HDMI_RX_AUDPLL_SC_STS1 REG(0x02b8)
281 #define HDMI_RX_AUDPLL_SC_STS2 REG(0x02bc)
282 #define HDMI_RX_SNPS_PHYG3_CTRL REG(0x02c0)
283 #define PORTSELECT_MASK GENMASK(3, 2)
284 #define PORTSELECT(x) UPDATE(x, 3, 2)
285 #define HDMI_RX_I2CM_PHYG3_SLAVE REG(0x02c4)
286 #define HDMI_RX_I2CM_PHYG3_ADDRESS REG(0x02c8)
287 #define HDMI_RX_I2CM_PHYG3_DATAO REG(0x02cc)
288 #define HDMI_RX_I2CM_PHYG3_DATAI REG(0x02d0)
289 #define HDMI_RX_I2CM_PHYG3_OPERATION REG(0x02d4)
290 #define HDMI_RX_I2CM_PHYG3_MODE REG(0x02d8)
291 #define HDMI_RX_I2CM_PHYG3_SOFTRST REG(0x02dc)
292 #define HDMI_RX_I2CM_PHYG3_SS_CNTS REG(0x02e0)
293 #define HDMI_RX_I2CM_PHYG3_FS_HCNT REG(0x02e4)
294 #define HDMI_RX_JTAG_CONF REG(0x02ec)
295 #define HDMI_RX_JTAG_TAP_TCLK REG(0x02f0)
296 #define HDMI_RX_JTAG_TAP_IN REG(0x02f4)
297 #define HDMI_RX_JTAG_TAP_OUT REG(0x02f8)
298 #define HDMI_RX_JTAG_ADDR REG(0x02fc)
299 #define HDMI_RX_PDEC_CTRL REG(0x0300)
300 #define PFIFO_SCORE_FILTER_EN BIT(31)
301 #define PFIFO_SCORE_HDP_IF BIT(29)
302 #define PFIFO_SCORE_AMP_IF BIT(28)
303 #define PFIFO_SCORE_NTSCVBI_IF BIT(27)
304 #define PFIFO_SCORE_MPEGS_IF BIT(26)
305 #define PFIFO_SCORE_AUD_IF BIT(25)
306 #define PFIFO_SCORE_SPD_IF BIT(24)
307 #define PFIFO_SCORE_AVI_IF BIT(23)
308 #define PFIFO_SCORE_VS_IF BIT(22)
309 #define PFIFO_SCORE_GMTP BIT(21)
310 #define PFIFO_SCORE_ISRC2 BIT(20)
311 #define PFIFO_SCORE_ISRC1 BIT(19)
312 #define PFIFO_SCORE_ACP BIT(18)
313 #define PFIFO_SCORE_GCP BIT(17)
314 #define PFIFO_SCORE_ACR BIT(16)
315 #define GCP_GLOBAVMUTE BIT(15)
316 #define PD_FIFO_WE BIT(4)
317 #define PDEC_BCH_EN BIT(0)
318 #define HDMI_RX_PDEC_FIFO_CFG REG(0x0304)
319 #define PD_FIFO_TH_START_MASK GENMASK(29, 20)
320 #define PD_FIFO_TH_START(x) UPDATE(x, 29, 20)
321 #define PD_FIFO_TH_MAX_MASK GENMASK(19, 10)
322 #define PD_FIFO_TH_MAX(x) UPDATE(x, 19, 10)
323 #define PD_FIFO_TH_MIN_MASK GENMASK(9, 0)
324 #define PD_FIFO_TH_MIN(x) UPDATE(x, 9, 0)
325 #define HDMI_RX_PDEC_FIFO_STS REG(0x0308)
326 #define HDMI_RX_PDEC_FIFO_DATA REG(0x030c)
327 #define HDMI_RX_PDEC_AUDIODET_CTRL REG(0x0310)
328 #define AUDIODET_THRESHOLD_MASK GENMASK(13, 9)
329 #define AUDIODET_THRESHOLD(x) UPDATE(x, 13, 9)
330 #define HDMI_RX_PDEC_DBG_ACP REG(0x031c)
331 #define HDMI_RX_PDEC_DBG_ERR_CORR REG(0x0320)
332 #define HDMI_RX_PDEC_FIFO_STS1 REG(0x0324)
333 #define HDMI_RX_PDEC_ACRM_CTRL REG(0x0330)
334 #define DELTACTS_IRQTRIG_MASK GENMASK(4, 2)
335 #define DELTACTS_IRQTRIG(x) UPDATE(x, 4, 2)
336 #define HDMI_RX_PDEC_ACRM_MAX REG(0x0334)
337 #define HDMI_RX_PDEC_ACRM_MIN REG(0x0338)
338 #define HDMI_RX_PDEC_ERR_FILTER REG(0x033c)
339 #define HDMI_RX_PDEC_ASP_CTRL REG(0x0340)
340 #define HDMI_RX_PDEC_ASP_ERR REG(0x0344)
341 #define HDMI_RX_PDEC_STS REG(0x0360)
342 #define HDMI_RX_PDEC_AUD_STS REG(0x0364)
343 #define HDMI_RX_PDEC_VSI_PAYLOAD0 REG(0x0368)
344 #define HDMI_RX_PDEC_VSI_PAYLOAD1 REG(0x036c)
345 #define HDMI_RX_PDEC_VSI_PAYLOAD2 REG(0x0370)
346 #define HDMI_RX_PDEC_VSI_PAYLOAD3 REG(0x0374)
347 #define HDMI_RX_PDEC_VSI_PAYLOAD4 REG(0x0378)
348 #define HDMI_RX_PDEC_VSI_PAYLOAD5 REG(0x037c)
349 #define HDMI_RX_PDEC_GCP_AVMUTE REG(0x0380)
350 #define PKTDEC_GCP_CD_MASK GENMASK(7, 4)
351 #define HDMI_RX_PDEC_ACR_CTS REG(0x0390)
352 #define HDMI_RX_PDEC_ACR_N REG(0x0394)
353 #define HDMI_RX_PDEC_AVI_HB REG(0x03a0)
354 #define HDMI_RX_PDEC_AVI_PB REG(0x03a4)
355 #define VID_IDENT_CODE_VIC7 BIT(31)
356 #define VID_IDENT_CODE GENMASK(30, 24)
357 #define VIDEO_FORMAT GENMASK(6, 5)
358 #define HDMI_RX_PDEC_AVI_TBB REG(0x03a8)
359 #define HDMI_RX_PDEC_AVI_LRB REG(0x03ac)
360 #define HDMI_RX_PDEC_AIF_CTRL REG(0x03c0)
361 #define FC_LFE_EXCHG BIT(18)
362 #define HDMI_RX_PDEC_AIF_HB REG(0x03c4)
363 #define HDMI_RX_PDEC_AIF_PB0 REG(0x03c8)
364 #define HDMI_RX_PDEC_AIF_PB1 REG(0x03cc)
365 #define HDMI_RX_PDEC_GMD_HB REG(0x03d0)
366 #define HDMI_RX_PDEC_GMD_PB REG(0x03d4)
367 #define HDMI_RX_PDEC_VSI_ST0 REG(0x03e0)
368 #define HDMI_RX_PDEC_VSI_ST1 REG(0x03e4)
369 #define HDMI_RX_PDEC_VSI_PB0 REG(0x03e8)
370 #define HDMI_RX_PDEC_VSI_PB1 REG(0x03ec)
371 #define HDMI_RX_PDEC_VSI_PB2 REG(0x03f0)
372 #define HDMI_RX_PDEC_VSI_PB3 REG(0x03f4)
373 #define HDMI_RX_PDEC_VSI_PB4 REG(0x03f8)
374 #define HDMI_RX_PDEC_VSI_PB5 REG(0x03fc)
375 #define HDMI_RX_CEAVID_CONFIG REG(0x0400)
376 #define HDMI_RX_CEAVID_3DCONFIG REG(0x0404)
377 #define HDMI_RX_CEAVID_HCONFIG_LO REG(0x0408)
378 #define HDMI_RX_CEAVID_HCONFIG_HI REG(0x040c)
379 #define HDMI_RX_CEAVID_VCONFIG_LO REG(0x0410)
380 #define HDMI_RX_CEAVID_VCONFIG_HI REG(0x0414)
381 #define HDMI_RX_CEAVID_STATUS REG(0x0418)
382 #define HDMI_RX_PDEC_AMP_HB REG(0x0480)
383 #define HDMI_RX_PDEC_AMP_PAYLOAD0 REG(0x0484)
384 #define HDMI_RX_PDEC_AMP_PAYLOAD1 REG(0x0488)
385 #define HDMI_RX_PDEC_AMP_PAYLOAD2 REG(0x048c)
386 #define HDMI_RX_PDEC_AMP_PAYLOAD3 REG(0x0490)
387 #define HDMI_RX_PDEC_AMP_PAYLOAD4 REG(0x0494)
388 #define HDMI_RX_PDEC_AMP_PAYLOAD5 REG(0x0498)
389 #define HDMI_RX_PDEC_AMP_PAYLOAD6 REG(0x049c)
390 #define HDMI_RX_PDEC_NTSCVBI_HB REG(0x04a0)
391 #define HDMI_RX_PDEC_NTSCVBI_PAYLOAD0 REG(0x04a4)
392 #define HDMI_RX_PDEC_NTSCVBI_PAYLOAD1 REG(0x04a8)
393 #define HDMI_RX_PDEC_NTSCVBI_PAYLOAD2 REG(0x04ac)
394 #define HDMI_RX_PDEC_NTSCVBI_PAYLOAD3 REG(0x04b0)
395 #define HDMI_RX_PDEC_NTSCVBI_PAYLOAD4 REG(0x04b4)
396 #define HDMI_RX_PDEC_NTSCVBI_PAYLOAD5 REG(0x04b8)
397 #define HDMI_RX_PDEC_NTSCVBI_PAYLOAD6 REG(0x04bc)
398 #define HDMI_RX_PDEC_DRM_HB REG(0x04c0)
399 #define HDMI_RX_PDEC_DRM_PAYLOAD0 REG(0x04c4)
400 #define HDMI_RX_PDEC_DRM_PAYLOAD1 REG(0x04c8)
401 #define HDMI_RX_PDEC_DRM_PAYLOAD2 REG(0x04cc)
402 #define HDMI_RX_PDEC_DRM_PAYLOAD3 REG(0x04d0)
403 #define HDMI_RX_PDEC_DRM_PAYLOAD4 REG(0x04d4)
404 #define HDMI_RX_PDEC_DRM_PAYLOAD5 REG(0x04d8)
405 #define HDMI_RX_PDEC_DRM_PAYLOAD6 REG(0x04dc)
406 #define HDMI_RX_MHLMODE_CTRL REG(0x0500)
407 #define HDMI_RX_CDSENSE_STATUS REG(0x0504)
408 #define HDMI_RX_DESERFIFO_CTRL REG(0x0508)
409 #define HDMI_RX_DESER_INTTRSHCTRL REG(0x050c)
410 #define HDMI_RX_DESER_INTCNTCTRL REG(0x0510)
411 #define HDMI_RX_DESER_INTCNT REG(0x0514)
412 #define HDMI_RX_HDCP_RPT_CTRL REG(0x0600)
413 #define HDMI_RX_HDCP_RPT_BSTATUS REG(0x0604)
414 #define HDMI_RX_HDCP_RPT_KSVFIFO_CTRL REG(0x0608)
415 #define HDMI_RX_HDCP_RPT_KSVFIFO1 REG(0x060c)
416 #define HDMI_RX_HDCP_RPT_KSVFIFO0 REG(0x0610)
417 #define HDMI_RX_HDMI20_CONTROL REG(0x0800)
418 #define HDMI_RX_SCDC_I2CCONFIG REG(0x0804)
419 #define I2CSPIKESUPPR_MASK GENMASK(25, 24)
420 #define I2CSPIKESUPPR(x) UPDATE(x, 25, 24)
421 #define HDMI_RX_SCDC_CONFIG REG(0x0808)
422 #define HDMI_RX_CHLOCK_CONFIG REG(0x080c)
423 #define CHLOCKMAXER_MASK GENMASK(29, 20)
424 #define CHLOCKMAXER(x) UPDATE(x, 29, 20)
425 #define MILISECTIMERLIMIT_MASK GENMASK(15, 0)
426 #define MILISECTIMERLIMIT(x) UPDATE(x, 15, 0)
427 #define HDMI_RX_HDCP22_CONTROL REG(0x081c)
428 #define HDMI_RX_SCDC_REGS0 REG(0x0820)
429 #define HDMI_RX_SCDC_REGS1 REG(0x0824)
430 #define HDMI_RX_SCDC_REGS2 REG(0x0828)
431 #define HDMI_RX_SCDC_REGS3 REG(0x082c)
432 #define HDMI_RX_SCDC_MANSPEC0 REG(0x0840)
433 #define HDMI_RX_SCDC_MANSPEC1 REG(0x0844)
434 #define HDMI_RX_SCDC_MANSPEC2 REG(0x0848)
435 #define HDMI_RX_SCDC_MANSPEC3 REG(0x084c)
436 #define HDMI_RX_SCDC_MANSPEC4 REG(0x0850)
437 #define HDMI_RX_SCDC_WRDATA0 REG(0x0860)
438 #define MANUFACTUREROUI_MASK GENMASK(31, 8)
439 #define MANUFACTUREROUI(x) UPDATE(x, 31, 8)
440 #define SINKVERSION_MASK GENMASK(7, 0)
441 #define SINKVERSION(x) UPDATE(x, 7, 0)
442 #define HDMI_RX_SCDC_WRDATA1 REG(0x0864)
443 #define HDMI_RX_SCDC_WRDATA2 REG(0x0868)
444 #define HDMI_RX_SCDC_WRDATA3 REG(0x086c)
445 #define HDMI_RX_SCDC_WRDATA4 REG(0x0870)
446 #define HDMI_RX_SCDC_WRDATA5 REG(0x0874)
447 #define HDMI_RX_SCDC_WRDATA6 REG(0x0878)
448 #define HDMI_RX_SCDC_WRDATA7 REG(0x087c)
449 #define HDMI_RX_HDMI20_STATUS REG(0x08e0)
450 #define HDMI_RX_HDCP2_ESM_GLOBAL_GPIO_IN REG(0x08e8)
451 #define HDMI_RX_HDCP2_ESM_GLOBAL_GPIO_OUT REG(0x08ec)
452 #define HDMI_RX_HDCP2_ESM_P0_GPIO_IN REG(0x08f0)
453 #define HDMI_RX_HDCP2_ESM_P0_GPIO_OUT REG(0x08f4)
454 #define HDMI_RX_HDCP22_STATUS REG(0x08fc)
455 #define HDMI_RX_HDMI2_IEN_CLR REG(0x0f60)
456 #define HDMI_RX_HDMI2_IEN_SET REG(0x0f64)
457 #define HDMI_RX_HDMI2_ISTS REG(0x0f68)
458 #define HDMI_RX_HDMI2_IEN REG(0x0f6c)
459 #define HDMI_RX_HDMI2_ICLR REG(0x0f70)
460 #define HDMI_RX_HDMI2_ISET REG(0x0f74)
461 #define HDMI_RX_PDEC_IEN_CLR REG(0x0f78)
462 #define HDMI_RX_PDEC_IEN_SET REG(0x0f7c)
463 #define HDMI_RX_PDEC_ISTS REG(0x0f80)
464 #define HDMI_RX_PDEC_IEN REG(0x0f84)
465 #define HDMI_RX_PDEC_ICLR REG(0x0f88)
466 #define HDMI_RX_PDEC_ISET REG(0x0f8c)
467 #define HDMI_RX_AUD_CEC_IEN_CLR REG(0x0f90)
468 #define HDMI_RX_AUD_CEC_IEN_SET REG(0x0f94)
469 #define HDMI_RX_AUD_CEC_ISTS REG(0x0f98)
470 #define HDMI_RX_AUD_CEC_IEN REG(0x0f9c)
471 #define HDMI_RX_AUD_CEC_ICLR REG(0x0fa0)
472 #define HDMI_RX_AUD_CEC_ISET REG(0x0fa4)
473 #define HDMI_RX_AUD_FIFO_IEN_CLR REG(0x0fa8)
474 #define HDMI_RX_AUD_FIFO_IEN_SET REG(0x0fac)
475 #define HDMI_RX_AUD_FIFO_ISTS REG(0x0fb0)
476 #define HDMI_RX_AUD_FIFO_IEN REG(0x0fb4)
477 #define HDMI_RX_AUD_FIFO_ICLR REG(0x0fb8)
478 #define HDMI_RX_AUD_FIFO_ISET REG(0x0fbc)
479 #define HDMI_RX_MD_IEN_CLR REG(0x0fc0)
480 #define HDMI_RX_MD_IEN_SET REG(0x0fc4)
481 #define HDMI_RX_MD_ISTS REG(0x0fc8)
482 #define HDMI_RX_MD_IEN REG(0x0fcc)
483 #define HDMI_RX_MD_ICLR REG(0x0fd0)
484 #define HDMI_RX_MD_ISET REG(0x0fd4)
485 #define HDMI_RX_HDMI_IEN_CLR REG(0x0fd8)
486 #define HDMI_RX_HDMI_IEN_SET REG(0x0fdc)
487 #define HDCP_DKSET_DONE_ENCLR_MASK BIT(31)
488 #define HDCP_DKSET_DONE_ENCLR(x) UPDATE(x, 31, 31)
489 #define HDMI_RX_HDMI_ISTS REG(0x0fe0)
490 #define HDMI_RX_HDMI_IEN REG(0x0fe4)
491 #define HDMI_RX_HDMI_ICLR REG(0x0fe8)
492 #define HDMI_RX_HDMI_ISET REG(0x0fec)
493 #define HDMI_RX_DMI_SW_RST REG(0x0ff0)
494 #define HDMI_RX_DMI_DISABLE_IF REG(0x0ff4)
495 #define MAIN_ENABLE BIT(0)
496 #define MODET_ENABLE BIT(1)
497 #define HDMI_ENABLE BIT(2)
498 #define BUS_ENABLE BIT(3)
499 #define AUD_ENABLE BIT(4)
500 #define CEC_ENABLE BIT(5)
501 #define PIXEL_ENABLE BIT(6)
502 #define VID_ENABLE BIT(7)
503 #define TMDS_ENABLE_MASK BIT(16)
504 #define TMDS_ENABLE(x) UPDATE(x, 16, 16)
505 #define HDMI_RX_DMI_MODULE_ID_EXT REG(0x0ff8)
506 #define HDMI_RX_DMI_MODULE_ID REG(0x0ffc)
507 #define HDMI_RX_CEC_CTRL REG(0x1f00)
508 #define HDMI_RX_CEC_MASK REG(0x1f08)
509 #define HDMI_RX_CEC_ADDR_L REG(0x1f14)
510 #define HDMI_RX_CEC_ADDR_H REG(0x1f18)
511 #define HDMI_RX_CEC_TX_CNT REG(0x1f1c)
512 #define HDMI_RX_CEC_RX_CNT REG(0x1f20)
513 #define HDMI_RX_CEC_TX_DATA_0 REG(0x1f40)
514 #define HDMI_RX_CEC_TX_DATA_1 REG(0x1f44)
515 #define HDMI_RX_CEC_TX_DATA_2 REG(0x1f48)
516 #define HDMI_RX_CEC_TX_DATA_3 REG(0x1f4c)
517 #define HDMI_RX_CEC_TX_DATA_4 REG(0x1f50)
518 #define HDMI_RX_CEC_TX_DATA_5 REG(0x1f54)
519 #define HDMI_RX_CEC_TX_DATA_6 REG(0x1f58)
520 #define HDMI_RX_CEC_TX_DATA_7 REG(0x1f5c)
521 #define HDMI_RX_CEC_TX_DATA_8 REG(0x1f60)
522 #define HDMI_RX_CEC_TX_DATA_9 REG(0x1f64)
523 #define HDMI_RX_CEC_TX_DATA_10 REG(0x1f68)
524 #define HDMI_RX_CEC_TX_DATA_11 REG(0x1f6c)
525 #define HDMI_RX_CEC_TX_DATA_12 REG(0x1f70)
526 #define HDMI_RX_CEC_TX_DATA_13 REG(0x1f74)
527 #define HDMI_RX_CEC_TX_DATA_14 REG(0x1f78)
528 #define HDMI_RX_CEC_TX_DATA_15 REG(0x1f7c)
529 #define HDMI_RX_CEC_RX_DATA_0 REG(0x1f80)
530 #define HDMI_RX_CEC_RX_DATA_1 REG(0x1f84)
531 #define HDMI_RX_CEC_RX_DATA_2 REG(0x1f88)
532 #define HDMI_RX_CEC_RX_DATA_3 REG(0x1f8c)
533 #define HDMI_RX_CEC_RX_DATA_4 REG(0x1f90)
534 #define HDMI_RX_CEC_RX_DATA_5 REG(0x1f94)
535 #define HDMI_RX_CEC_RX_DATA_6 REG(0x1f98)
536 #define HDMI_RX_CEC_RX_DATA_7 REG(0x1f9c)
537 #define HDMI_RX_CEC_RX_DATA_8 REG(0x1fa0)
538 #define HDMI_RX_CEC_RX_DATA_9 REG(0x1fa4)
539 #define HDMI_RX_CEC_RX_DATA_10 REG(0x1fa8)
540 #define HDMI_RX_CEC_RX_DATA_11 REG(0x1fac)
541 #define HDMI_RX_CEC_RX_DATA_12 REG(0x1fb0)
542 #define HDMI_RX_CEC_RX_DATA_13 REG(0x1fb4)
543 #define HDMI_RX_CEC_RX_DATA_14 REG(0x1fb8)
544 #define HDMI_RX_CEC_RX_DATA_15 REG(0x1fbc)
545 #define HDMI_RX_CEC_LOCK REG(0x1fc0)
546 #define HDMI_RX_CEC_WAKEUPCTRL REG(0x1fc4)
547 #define HDMI_RX_CBUSSWRESETREQ REG(0x3000)
548 #define HDMI_RX_CBUSENABLEIF REG(0x3004)
549 #define HDMI_RX_CB_LOCKONCLOCK_STS REG(0x3010)
550 #define HDMI_RX_CB_LOCKONCLOCKCLR REG(0x3014)
551 #define HDMI_RX_CBUSIOCTRL REG(0x3020)
552 #define HDMI_RX_DD_CTRL REG(0x3040)
553 #define HDMI_RX_DD_OP_CTRL REG(0x3044)
554 #define HDMI_RX_DD_STS REG(0x3048)
555 #define HDMI_RX_DD_BYPASS_EN REG(0x304c)
556 #define HDMI_RX_DD_BYPASS_CTRL REG(0x3050)
557 #define HDMI_RX_DD_BYPASS_CBUS REG(0x3054)
558 #define HDMI_RX_LL_TXPCKFIFO REG(0x3080)
559 #define HDMI_RX_LL_RXPCKFIFO_RD_CLR REG(0x3084)
560 #define HDMI_RX_LL_RXPCKFIFO_A REG(0x3088)
561 #define HDMI_RX_LL_RXPCKFIFO_B REG(0x308c)
562 #define HDMI_RX_LL_TXPCKCTRL_0 REG(0x3090)
563 #define HDMI_RX_LL_TXPCKCTRL_1 REG(0x3094)
564 #define HDMI_RX_LL_PCKFIFO_STS REG(0x309c)
565 #define HDMI_RX_LL_RXPCKCTRL_0 REG(0x30a0)
566 #define HDMI_RX_LL_RXPCKCTRL_1 REG(0x30a4)
567 #define HDMI_RX_LL_INTTRSHLDCTRL REG(0x30b0)
568 #define HDMI_RX_LL_INTCNTCTRL REG(0x30b4)
569 #define HDMI_RX_LL_INTCNT_0 REG(0x30b8)
570 #define HDMI_RX_LL_INTCNT_1 REG(0x30bc)
571 #define HDMI_RX_CBHDCP_OPCTRL REG(0x3100)
572 #define HDMI_RX_CBHDCP_WDATA_0 REG(0x3104)
573 #define HDMI_RX_CBHDCP_WDATA_1 REG(0x3108)
574 #define HDMI_RX_CBHDCP_RDATA_0 REG(0x310c)
575 #define HDMI_RX_CBHDCP_RDATA_1 REG(0x3110)
576 #define HDMI_RX_CBHDCP_STATUS REG(0x3114)
577 #define HDMI_RX_CBHDCP_DDC_REPORT REG(0x3118)
578 #define HDMI_RX_ISTAT_CB_DD REG(0x3200)
579 #define HDMI_RX_IMASK_CB_DD REG(0x3204)
580 #define HDMI_RX_IFORCE_CB_DD REG(0x3208)
581 #define HDMI_RX_ICLEAR_CB_DD REG(0x320c)
582 #define HDMI_RX_IMUTE_CB_DD REG(0x3210)
583 #define HDMI_RX_ISTAT_CB_LL REG(0x3220)
584 #define HDMI_RX_IMASK_CB_LL REG(0x3224)
585 #define HDMI_RX_IFORCE_CB_LL REG(0x3228)
586 #define HDMI_RX_ICLEAR_CB_LL REG(0x322c)
587 #define HDMI_RX_IMUTE_CB_LL REG(0x3230)
588 #define HDMI_RX_ISTAT_CB_HDCP REG(0x3240)
589 #define HDMI_RX_IMASK_CB_HDCP REG(0x3244)
590 #define HDMI_RX_IFORCE_CB_HDCP REG(0x3248)
591 #define HDMI_RX_ICLEAR_CB_HDCP REG(0x324c)
592 #define HDMI_RX_IMUTE_CB_HDCP REG(0x3250)
593 #define HDMI_RX_ISTAT_CB_MCTRL REG(0x3260)
594 #define HDMI_RX_IMASK_CB_MCTRL REG(0x3264)
595 #define HDMI_RX_IFORCE_CB_MCTRL REG(0x3268)
596 #define HDMI_RX_ICLEAR_CB_MCTRL REG(0x326c)
597 #define HDMI_RX_IMUTE_CB_MCTRL REG(0x3270)
598 #define HDMI_RX_IMASTER_MUTE_CB REG(0x32e0)
599 #define HDMI_RX_IVECTOR_INDEX_CB REG(0x32e4)
600 #define HDMI_RX_MAX_REGISTER HDMI_RX_IVECTOR_INDEX_CB
601
602 struct rk628_hdmirx {
603 struct drm_bridge base;
604 struct drm_bridge *bridge;
605 struct device *dev;
606 struct regmap *regmap;
607 struct regmap *grf;
608 struct phy *phy;
609 struct clk *pclk;
610 struct clk *cec_clk;
611 struct clk *aud_clk;
612 struct clk *imodet_clk;
613 struct reset_control *hdmirx;
614 struct reset_control *hdmirx_pon;
615 struct rk628 *parent;
616 struct drm_display_mode mode;
617 };
618
619 static const struct regmap_range rk628_hdmirx_readable_ranges[] = {
620 regmap_reg_range(HDMI_RX_HDMI_SETUP_CTRL, HDMI_RX_HDMI_TIMER_CTRL),
621 regmap_reg_range(HDMI_RX_HDMI_MODE_RECOVER, HDMI_RX_HDMI_ERD_STS),
622 regmap_reg_range(HDMI_RX_MD_HCTRL1, HDMI_RX_MD_STS),
623 regmap_reg_range(HDMI_RX_PDEC_ACRM_CTRL, HDMI_RX_PDEC_ASP_ERR),
624 regmap_reg_range(HDMI_RX_PDEC_AVI_HB, HDMI_RX_PDEC_AVI_LRB),
625 regmap_reg_range(HDMI_RX_PDEC_AIF_CTRL, HDMI_RX_PDEC_GMD_PB),
626 regmap_reg_range(HDMI_RX_HDMI20_CONTROL, HDMI_RX_CHLOCK_CONFIG),
627 regmap_reg_range(HDMI_RX_SCDC_REGS1, HDMI_RX_SCDC_REGS3),
628 regmap_reg_range(HDMI_RX_SCDC_WRDATA0, HDMI_RX_SCDC_WRDATA7),
629 regmap_reg_range(HDMI_RX_DMI_DISABLE_IF, HDMI_RX_DMI_DISABLE_IF),
630 };
631
632 static const struct regmap_access_table rk628_hdmirx_readable_table = {
633 .yes_ranges = rk628_hdmirx_readable_ranges,
634 .n_yes_ranges = ARRAY_SIZE(rk628_hdmirx_readable_ranges),
635 };
636
637 static const struct regmap_config rk628_hdmirx_regmap_config = {
638 .name = "hdmirx",
639 .reg_bits = 32,
640 .val_bits = 32,
641 .reg_stride = 4,
642 .max_register = HDMI_RX_MAX_REGISTER,
643 .reg_format_endian = REGMAP_ENDIAN_LITTLE,
644 .val_format_endian = REGMAP_ENDIAN_LITTLE,
645 .rd_table = &rk628_hdmirx_readable_table,
646 };
647
bridge_to_hdmirx(struct drm_bridge * bridge)648 static inline struct rk628_hdmirx *bridge_to_hdmirx(struct drm_bridge *bridge)
649 {
650 return container_of(bridge, struct rk628_hdmirx, base);
651 }
652
rk628_hdmirx_ctrl_enable(struct rk628_hdmirx * hdmirx)653 static void rk628_hdmirx_ctrl_enable(struct rk628_hdmirx *hdmirx)
654 {
655 clk_prepare_enable(hdmirx->pclk);
656 clk_prepare_enable(hdmirx->aud_clk);
657 clk_prepare_enable(hdmirx->imodet_clk);
658
659 reset_control_deassert(hdmirx->hdmirx);
660 reset_control_deassert(hdmirx->hdmirx_pon);
661
662 regmap_update_bits(hdmirx->grf, GRF_SYSTEM_CON0,
663 SW_INPUT_MODE_MASK,
664 SW_INPUT_MODE(INPUT_MODE_HDMI));
665
666 regmap_write(hdmirx->regmap, HDMI_RX_DMI_SW_RST, 0x000101ff);
667
668 regmap_write(hdmirx->regmap, HDMI_RX_DMI_DISABLE_IF, 0x00000000);
669 regmap_write(hdmirx->regmap, HDMI_RX_DMI_DISABLE_IF, 0x0000017f);
670 regmap_write(hdmirx->regmap, HDMI_RX_DMI_DISABLE_IF, 0x0001017f);
671
672 regmap_write(hdmirx->regmap, HDMI_RX_HDMI20_CONTROL, 0x10001f10);
673
674 regmap_update_bits(hdmirx->regmap, HDMI_RX_CHLOCK_CONFIG,
675 CHLOCKMAXER_MASK | MILISECTIMERLIMIT_MASK,
676 CHLOCKMAXER(0x1) | MILISECTIMERLIMIT(49500));
677
678 regmap_write(hdmirx->regmap, HDMI_RX_SCDC_CONFIG, 0x00000001);
679 regmap_write(hdmirx->regmap, HDMI_RX_DMI_SW_RST, 0x000001fe);
680 regmap_write(hdmirx->regmap, HDMI_RX_HDMI_CKM_EVLTM, 0x0016fff0);
681 regmap_write(hdmirx->regmap, HDMI_RX_HDMI_CKM_F, 0xf98a0190);
682
683 regmap_update_bits(hdmirx->regmap, HDMI_RX_HDMI_MODE_RECOVER,
684 SPIKE_FILTER_EN_MASK | DVI_MODE_HYST_MASK |
685 HDMI_MODE_HYST_MASK | HDMI_MODE_MASK |
686 GB_DET_MASK | EESS_OESS_MASK | SEL_CTL01_MASK,
687 SPIKE_FILTER_EN(0) |
688 DVI_MODE_HYST(0) |
689 HDMI_MODE_HYST(0) |
690 HDMI_MODE(3) |
691 GB_DET(2) |
692 EESS_OESS(0) |
693 SEL_CTL01(1));
694
695 regmap_write(hdmirx->regmap, HDMI_RX_PDEC_CTRL, 0xbfff8011);
696 regmap_write(hdmirx->regmap, HDMI_RX_PDEC_ASP_CTRL, 0x00000040);
697
698 regmap_update_bits(hdmirx->regmap, HDMI_RX_HDMI_RESMPL_CTRL,
699 MAN_VID_DEREPEAT_MASK, MAN_VID_DEREPEAT(1));
700
701 regmap_update_bits(hdmirx->regmap, HDMI_RX_HDMI_SYNC_CTRL,
702 VS_POL_ADJ_MODE_MASK | HS_POL_ADJ_MODE_MASK,
703 VS_POL_ADJ_MODE(2) | HS_POL_ADJ_MODE(2));
704
705 regmap_write(hdmirx->regmap, HDMI_RX_PDEC_ERR_FILTER, 0x00000008);
706
707 regmap_update_bits(hdmirx->regmap, HDMI_RX_SCDC_I2CCONFIG,
708 I2CSPIKESUPPR_MASK, I2CSPIKESUPPR(1));
709
710 regmap_write(hdmirx->regmap, HDMI_RX_SCDC_CONFIG, 0x00000001);
711 regmap_write(hdmirx->regmap, HDMI_RX_SCDC_WRDATA0, 0xabcdef01);
712
713 regmap_update_bits(hdmirx->regmap, HDMI_RX_CHLOCK_CONFIG,
714 CHLOCKMAXER_MASK | MILISECTIMERLIMIT_MASK,
715 CHLOCKMAXER(0x1) | MILISECTIMERLIMIT(49500));
716
717 regmap_write(hdmirx->regmap, HDMI_RX_HDMI_ERROR_PROTECT, 0x000d0c98);
718 regmap_write(hdmirx->regmap, HDMI_RX_MD_HCTRL1, 0x00000010);
719 regmap_write(hdmirx->regmap, HDMI_RX_MD_HCTRL2, 0x00001738);
720 regmap_write(hdmirx->regmap, HDMI_RX_MD_VCTRL, 0x00000012);
721 regmap_write(hdmirx->regmap, HDMI_RX_MD_VTH, 0x0000073a);
722 regmap_write(hdmirx->regmap, HDMI_RX_MD_IL_POL, 0x00000004);
723 regmap_write(hdmirx->regmap, HDMI_RX_PDEC_ACRM_CTRL, 0x00000000);
724 regmap_write(hdmirx->regmap, HDMI_RX_HDMI_DCM_CTRL, 0x00040414);
725 regmap_write(hdmirx->regmap, HDMI_RX_HDMI_PCB_CTRL, 0x00100000);
726 regmap_write(hdmirx->regmap, HDMI_RX_HDMI_SETUP_CTRL, 0x0f000fff);
727 regmap_write(hdmirx->regmap, HDMI_RX_HDMI_CKM_EVLTM, 0x00104260);
728 regmap_write(hdmirx->regmap, HDMI_RX_HDMI_CKM_F, 0x0f2d0eed);
729 regmap_write(hdmirx->regmap, HDMI_RX_DMI_DISABLE_IF, 0x00000001);
730 udelay(400);
731 regmap_write(hdmirx->regmap, HDMI_RX_DMI_DISABLE_IF, 0x0001017f);
732 regmap_update_bits(hdmirx->regmap, HDMI_RX_HDMI_RESMPL_CTRL,
733 MAN_VID_DEREPEAT_MASK, MAN_VID_DEREPEAT(1));
734 regmap_write(hdmirx->regmap, HDMI_RX_DMI_SW_RST, 0x000001fe);
735 }
736
rk628_hdmirx_ctrl_disable(struct rk628_hdmirx * hdmirx)737 static void rk628_hdmirx_ctrl_disable(struct rk628_hdmirx *hdmirx)
738 {
739 reset_control_assert(hdmirx->hdmirx);
740 reset_control_assert(hdmirx->hdmirx_pon);
741 clk_disable_unprepare(hdmirx->pclk);
742 clk_disable_unprepare(hdmirx->aud_clk);
743 clk_disable_unprepare(hdmirx->imodet_clk);
744 }
745
rk628_hdmirx_bridge_enable(struct drm_bridge * bridge)746 static void rk628_hdmirx_bridge_enable(struct drm_bridge *bridge)
747 {
748 bool locked;
749 u32 value, i, hact, vact, bus_width, hdisplay, vdisplay;
750 struct rk628_hdmirx *hdmirx = bridge_to_hdmirx(bridge);
751
752 /* force 594m mode to yuv420 format */
753 if (hdmirx->mode.clock == 594000) {
754 /*
755 * bit30 is used to indicate whether it is
756 * yuv420 format
757 */
758 bus_width = hdmirx->mode.clock | BIT(30);
759 hdisplay = hdmirx->mode.hdisplay / 2;
760 } else {
761 bus_width = hdmirx->mode.clock;
762 hdisplay = hdmirx->mode.hdisplay;
763 }
764
765 vdisplay = hdmirx->mode.vdisplay;
766
767 phy_set_bus_width(hdmirx->phy, bus_width);
768 phy_power_on(hdmirx->phy);
769 usleep_range(10*1000, 11*1000);
770 rk628_hdmirx_ctrl_enable(hdmirx);
771
772 /* if hdmirx ctrl unlock or get incorrect timing, reset ctrl and phy */
773 for (i = 0; i < 5; i++) {
774 usleep_range(100*1000, 110*1000);
775 regmap_read(hdmirx->regmap, HDMI_RX_SCDC_REGS1, &value);
776 dev_dbg(hdmirx->dev, "HDMI_RX_SCDC_REGS1:0x%x\n", value);
777 value = (value >> 8) & 0xf;
778
779 regmap_read(hdmirx->regmap, HDMI_RX_MD_HACT_PX, &hact);
780 regmap_read(hdmirx->regmap, HDMI_RX_MD_VAL, &vact);
781
782 hact = hact & 0xffff;
783 vact = vact & 0xffff;
784 dev_dbg(hdmirx->dev, "hact:%d,vact:%d\n", hact, vact);
785
786 if (value == 0xf && hact == hdisplay && vact == vdisplay)
787 locked = true;
788 else
789 locked = false;
790
791 if (!locked) {
792 rk628_hdmirx_ctrl_disable(hdmirx);
793 usleep_range(10*1000, 11*1000);
794 phy_power_off(hdmirx->phy);
795 usleep_range(10*1000, 11*1000);
796 phy_power_on(hdmirx->phy);
797 usleep_range(10*1000, 11*1000);
798 rk628_hdmirx_ctrl_enable(hdmirx);
799 } else {
800 /* hdmirx ctrl get correct timing, enable output */
801 regmap_write(hdmirx->regmap, HDMI_RX_DMI_DISABLE_IF,
802 0x000001ff);
803 return;
804 }
805 }
806
807 dev_err(hdmirx->dev, "hdmirx channel can't lock!\n");
808
809 }
810
rk628_hdmirx_bridge_disable(struct drm_bridge * bridge)811 static void rk628_hdmirx_bridge_disable(struct drm_bridge *bridge)
812 {
813 struct rk628_hdmirx *hdmirx = bridge_to_hdmirx(bridge);
814
815 rk628_hdmirx_ctrl_disable(hdmirx);
816 phy_power_off(hdmirx->phy);
817 }
818
rk628_hdmirx_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)819 static int rk628_hdmirx_bridge_attach(struct drm_bridge *bridge,
820 enum drm_bridge_attach_flags flags)
821 {
822 struct rk628_hdmirx *hdmirx = bridge_to_hdmirx(bridge);
823 struct device *dev = hdmirx->dev;
824 int ret;
825
826 ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1,
827 NULL, &hdmirx->bridge);
828 if (ret) {
829 dev_err(dev, "failed to find next bridge\n");
830 return ret;
831 }
832
833 ret = drm_bridge_attach(bridge->encoder, hdmirx->bridge, bridge, flags);
834 if (ret) {
835 dev_err(dev, "failed to attach bridge\n");
836 return ret;
837 }
838
839 return 0;
840 }
841
rk628_hdmirx_bridge_mode_set(struct drm_bridge * bridge,const struct drm_display_mode * mode,const struct drm_display_mode * adj)842 static void rk628_hdmirx_bridge_mode_set(struct drm_bridge *bridge,
843 const struct drm_display_mode *mode,
844 const struct drm_display_mode *adj)
845 {
846 struct rk628_hdmirx *hdmirx = bridge_to_hdmirx(bridge);
847
848 memcpy(&hdmirx->mode, adj, sizeof(hdmirx->mode));
849 }
850
851 static const struct drm_bridge_funcs rk628_hdmirx_bridge_funcs = {
852 .attach = rk628_hdmirx_bridge_attach,
853 .enable = rk628_hdmirx_bridge_enable,
854 .disable = rk628_hdmirx_bridge_disable,
855 .mode_set = rk628_hdmirx_bridge_mode_set,
856 };
857
rk628_hdmirx_probe(struct platform_device * pdev)858 static int rk628_hdmirx_probe(struct platform_device *pdev)
859 {
860 struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
861 struct device *dev = &pdev->dev;
862 struct platform_device_info pdevinfo;
863 struct rk628_hdmirx *hdmirx;
864 int ret, irq;
865
866 if (!of_device_is_available(dev->of_node))
867 return -ENODEV;
868
869 hdmirx = devm_kzalloc(dev, sizeof(*hdmirx), GFP_KERNEL);
870 if (!hdmirx)
871 return -ENOMEM;
872
873 hdmirx->dev = dev;
874 hdmirx->parent = rk628;
875 platform_set_drvdata(pdev, hdmirx);
876
877 irq = platform_get_irq(pdev, 0);
878 if (irq < 0)
879 return irq;
880
881 hdmirx->grf = rk628->grf;
882 if (!hdmirx->grf)
883 return -ENODEV;
884
885 hdmirx->pclk = devm_clk_get(dev, "pclk");
886 if (IS_ERR(hdmirx->pclk)) {
887 ret = PTR_ERR(hdmirx->pclk);
888 dev_err(dev, "failed to get pclk: %d\n", ret);
889 return ret;
890 }
891
892 hdmirx->cec_clk = devm_clk_get(dev, "cec");
893 if (IS_ERR(hdmirx->cec_clk)) {
894 ret = PTR_ERR(hdmirx->cec_clk);
895 dev_err(dev, "failed to get cec clk: %d\n", ret);
896 return ret;
897 }
898
899 hdmirx->aud_clk = devm_clk_get(dev, "audio");
900 if (IS_ERR(hdmirx->aud_clk)) {
901 ret = PTR_ERR(hdmirx->aud_clk);
902 dev_err(dev, "failed to get audio clk: %d\n", ret);
903 return ret;
904 }
905
906 hdmirx->imodet_clk = devm_clk_get(dev, "imodet");
907 if (IS_ERR(hdmirx->imodet_clk)) {
908 ret = PTR_ERR(hdmirx->imodet_clk);
909 dev_err(dev, "failed to get imodet clk: %d\n", ret);
910 return ret;
911 }
912
913 hdmirx->hdmirx = of_reset_control_get(dev->of_node, "hdmirx");
914 if (IS_ERR(hdmirx->hdmirx)) {
915 ret = PTR_ERR(hdmirx->hdmirx);
916 DRM_DEV_ERROR(dev, "failed to get hdmirx control: %d\n", ret);
917 return ret;
918 }
919
920 hdmirx->hdmirx_pon = of_reset_control_get(dev->of_node, "hdmirx_pon");
921 if (IS_ERR(hdmirx->hdmirx_pon)) {
922 ret = PTR_ERR(hdmirx->hdmirx_pon);
923 DRM_DEV_ERROR(dev, "failed to get hdmirx_pon control: %d\n", ret);
924 return ret;
925 }
926
927 hdmirx->phy = devm_of_phy_get(dev, dev->of_node, NULL);
928 if (IS_ERR(hdmirx->phy)) {
929 ret = PTR_ERR(hdmirx->phy);
930 dev_err(dev, "failed to get phy: %d\n", ret);
931 return ret;
932 }
933
934 hdmirx->regmap = devm_regmap_init_i2c(rk628->client,
935 &rk628_hdmirx_regmap_config);
936 if (IS_ERR(hdmirx->regmap)) {
937 ret = PTR_ERR(hdmirx->regmap);
938 dev_err(dev, "failed to allocate register map: %d\n", ret);
939 return ret;
940 }
941
942 hdmirx->base.funcs = &rk628_hdmirx_bridge_funcs;
943 hdmirx->base.of_node = dev->of_node;
944 drm_bridge_add(&hdmirx->base);
945
946 memset(&pdevinfo, 0, sizeof(pdevinfo));
947 pdevinfo.parent = dev;
948 pdevinfo.id = PLATFORM_DEVID_AUTO;
949
950 return 0;
951 }
952
rk628_hdmirx_remove(struct platform_device * pdev)953 static int rk628_hdmirx_remove(struct platform_device *pdev)
954 {
955 struct rk628_hdmirx *hdmirx = platform_get_drvdata(pdev);
956
957 drm_bridge_remove(&hdmirx->base);
958
959 return 0;
960 }
961
962 static const struct of_device_id rk628_hdmirx_of_match[] = {
963 { .compatible = "rockchip,rk628-hdmirx", },
964 {},
965 };
966 MODULE_DEVICE_TABLE(of, rk628_hdmirx_of_match);
967
968 static struct platform_driver rk628_hdmirx_driver = {
969 .driver = {
970 .name = "rk628-hdmirx",
971 .of_match_table = of_match_ptr(rk628_hdmirx_of_match),
972 },
973 .probe = rk628_hdmirx_probe,
974 .remove = rk628_hdmirx_remove,
975 };
976 module_platform_driver(rk628_hdmirx_driver);
977
978 MODULE_AUTHOR("Algea Cao <algea.cao@rock-chips.com>");
979 MODULE_DESCRIPTION("Rockchip RK628 HDMI RX driver");
980 MODULE_LICENSE("GPL v2");
981