1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
4 *
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
6 */
7
8 #include <linux/clk.h>
9 #include <linux/platform_device.h>
10 #include <linux/of.h>
11 #include <linux/regmap.h>
12 #include <linux/mfd/rk618.h>
13
14 #include <drm/drm_drv.h>
15 #include <drm/drm_of.h>
16 #include <drm/drm_atomic.h>
17 #include <drm/drm_crtc_helper.h>
18 #include <drm/drm_atomic_helper.h>
19 #include <drm/drm_mipi_dsi.h>
20 #include <drm/drm_panel.h>
21 #include <drm/drm_probe_helper.h>
22
23 #include <video/of_display_timing.h>
24 #include <video/mipi_display.h>
25 #include <video/videomode.h>
26 #include <asm/unaligned.h>
27
28 #include "../rockchip_drm_drv.h"
29
30 #define HOSTREG(x) ((x) + 0x1000)
31 #define DSI_VERSION HOSTREG(0x0000)
32 #define DSI_PWR_UP HOSTREG(0x0004)
33 #define SHUTDOWNZ BIT(0)
34 #define POWER_UP BIT(0)
35 #define RESET 0
36 #define DSI_CLKMGR_CFG HOSTREG(0x0008)
37 #define TO_CLK_DIVIDSION(x) UPDATE(x, 15, 8)
38 #define TX_ESC_CLK_DIVIDSION(x) UPDATE(x, 7, 0)
39 #define DSI_DPI_CFG HOSTREG(0x000c)
40 #define EN18_LOOSELY BIT(10)
41 #define COLORM_ACTIVE_LOW BIT(9)
42 #define SHUTD_ACTIVE_LOW BIT(8)
43 #define HSYNC_ACTIVE_LOW BIT(7)
44 #define VSYNC_ACTIVE_LOW BIT(6)
45 #define DATAEN_ACTIVE_LOW BIT(5)
46 #define DPI_COLOR_CODING(x) UPDATE(x, 4, 2)
47 #define DPI_VID(x) UPDATE(x, 1, 0)
48 #define DSI_PCKHDL_CFG HOSTREG(0x0018)
49 #define GEN_VID_RX(x) UPDATE(x, 6, 5)
50 #define EN_CRC_RX BIT(4)
51 #define EN_ECC_RX BIT(3)
52 #define EN_BTA BIT(2)
53 #define EN_EOTP_RX BIT(1)
54 #define EN_EOTP_TX BIT(0)
55 #define DSI_VID_MODE_CFG HOSTREG(0x001c)
56 #define LPCMDEN BIT(12)
57 #define FRAME_BTA_ACK BIT(11)
58 #define EN_NULL_PKT BIT(10)
59 #define EN_MULTI_PKT BIT(9)
60 #define EN_LP_HFP BIT(8)
61 #define EN_LP_HBP BIT(7)
62 #define EN_LP_VACT BIT(6)
63 #define EN_LP_VFP BIT(5)
64 #define EN_LP_VBP BIT(4)
65 #define EN_LP_VSA BIT(3)
66 #define VID_MODE_TYPE(x) UPDATE(x, 2, 1)
67 #define EN_VIDEO_MODE BIT(0)
68 #define DSI_VID_PKT_CFG HOSTREG(0x0020)
69 #define NULL_PKT_SIZE(x) UPDATE(x, 30, 21)
70 #define NUM_CHUNKS(x) UPDATE(x, 20, 11)
71 #define VID_PKT_SIZE(x) UPDATE(x, 10, 0)
72 #define DSI_CMD_MODE_CFG HOSTREG(0x0024)
73 #define TEAR_FX_EN BIT(14)
74 #define ACK_RQST_EN BIT(13)
75 #define DCS_LW_TX BIT(12)
76 #define GEN_LW_TX BIT(11)
77 #define MAX_RD_PKT_SIZE BIT(10)
78 #define DCS_SR_0P_TX BIT(9)
79 #define DCS_SW_1P_TX BIT(8)
80 #define DCS_SW_0P_TX BIT(7)
81 #define GEN_SR_2P_TX BIT(6)
82 #define GEN_SR_1P_TX BIT(5)
83 #define GEN_SR_0P_TX BIT(4)
84 #define GEN_SW_2P_TX BIT(3)
85 #define GEN_SW_1P_TX BIT(2)
86 #define GEN_SW_0P_TX BIT(1)
87 #define EN_CMD_MODE BIT(0)
88 #define DSI_TMR_LINE_CFG HOSTREG(0x0028)
89 #define HLINE_TIME(x) UPDATE(x, 31, 18)
90 #define HBP_TIME(x) UPDATE(x, 17, 9)
91 #define HSA_TIME(x) UPDATE(x, 8, 0)
92 #define DSI_VTIMING_CFG HOSTREG(0x002c)
93 #define V_ACTIVE_LINES(x) UPDATE(x, 26, 16)
94 #define VFP_LINES(x) UPDATE(x, 15, 10)
95 #define VBP_LINES(x) UPDATE(x, 9, 4)
96 #define VSA_LINES(x) UPDATE(x, 3, 0)
97 #define DSI_PHY_TMR_CFG HOSTREG(0x0030)
98 #define PHY_HS2LP_TIME(x) UPDATE(x, 31, 24)
99 #define PHY_LP2HS_TIME(x) UPDATE(x, 23, 16)
100 #define MAX_RD_TIME(x) UPDATE(x, 14, 0)
101 #define DSI_GEN_HDR HOSTREG(0x0034)
102 #define DSI_GEN_PLD_DATA HOSTREG(0x0038)
103 #define DSI_GEN_PKT_STATUS HOSTREG(0x003c)
104 #define GEN_RD_CMD_BUSY BIT(6)
105 #define GEN_PLD_R_FULL BIT(5)
106 #define GEN_PLD_R_EMPTY BIT(4)
107 #define GEN_PLD_W_FULL BIT(3)
108 #define GEN_PLD_W_EMPTY BIT(2)
109 #define GEN_CMD_FULL BIT(1)
110 #define GEN_CMD_EMPTY BIT(0)
111 #define DSI_TO_CNT_CFG HOSTREG(0x0040)
112 #define LPRX_TO_CNT(x) UPDATE(x, 31, 16)
113 #define HSTX_TO_CNT(x) UPDATE(x, 15, 0)
114 #define DSI_INT_ST0 HOSTREG(0x0044)
115 #define DSI_INT_ST1 HOSTREG(0x0048)
116 #define DSI_INT_MSK0 HOSTREG(0x004c)
117 #define DSI_INT_MSK1 HOSTREG(0x0050)
118 #define DSI_PHY_RSTZ HOSTREG(0x0054)
119 #define PHY_ENABLECLK BIT(2)
120 #define DSI_PHY_IF_CFG HOSTREG(0x0058)
121 #define PHY_STOP_WAIT_TIME(x) UPDATE(x, 9, 2)
122 #define N_LANES(x) UPDATE(x, 1, 0)
123 #define DSI_PHY_IF_CTRL HOSTREG(0x005c)
124 #define PHY_TX_TRIGGERS(x) UPDATE(x, 8, 5)
125 #define PHY_TXEXITULPSLAN BIT(4)
126 #define PHY_TXREQULPSLAN BIT(3)
127 #define PHY_TXEXITULPSCLK BIT(2)
128 #define PHY_RXREQULPSCLK BIT(1)
129 #define PHY_TXREQUESCLKHS BIT(0)
130 #define DSI_PHY_STATUS HOSTREG(0x0060)
131 #define ULPSACTIVENOT3LANE BIT(12)
132 #define PHYSTOPSTATE3LANE BIT(11)
133 #define ULPSACTIVENOT2LANE BIT(10)
134 #define PHYSTOPSTATE2LANE BIT(9)
135 #define ULPSACTIVENOT1LANE BIT(8)
136 #define PHYSTOPSTATE1LANE BIT(7)
137 #define RXULPSESC0LANE BIT(6)
138 #define ULPSACTIVENOT0LANE BIT(5)
139 #define PHYSTOPSTATE0LANE BIT(4)
140 #define PHYULPSACTIVENOTCLK BIT(3)
141 #define PHYSTOPSTATECLKLANE BIT(2)
142 #define PHYSTOPSTATELANE (PHYSTOPSTATE0LANE | PHYSTOPSTATECLKLANE)
143 #define PHYDIRECTION BIT(1)
144 #define PHYLOCK BIT(0)
145 #define DSI_LP_CMD_TIM HOSTREG(0x0070)
146 #define OUTVACT_LPCMD_TIME(x) UPDATE(x, 15, 8)
147 #define INVACT_LPCMD_TIME(x) UPDATE(x, 7, 0)
148 #define DSI_MAX_REGISTER DSI_LP_CMD_TIM
149
150 #define PHYREG(x) ((x) + 0x0c00)
151 #define MIPI_PHY_REG0 PHYREG(0x0000)
152 #define LANE_EN_MASK GENMASK(6, 2)
153 #define LANE_EN_CK BIT(6)
154 #define MIPI_PHY_REG1 PHYREG(0x0004)
155 #define REG_DA_PPFC BIT(4)
156 #define REG_DA_SYNCRST BIT(2)
157 #define REG_DA_LDOPD BIT(1)
158 #define REG_DA_PLLPD BIT(0)
159 #define MIPI_PHY_REG3 PHYREG(0x000c)
160 #define REG_FBDIV_HI_MASK GENMASK(5, 5)
161 #define REG_FBDIV_HI(x) UPDATE(x, 5, 5)
162 #define REG_PREDIV_MASK GENMASK(4, 0)
163 #define REG_PREDIV(x) UPDATE(x, 4, 0)
164 #define MIPI_PHY_REG4 PHYREG(0x0010)
165 #define REG_FBDIV_LO_MASK GENMASK(7, 0)
166 #define REG_FBDIV_LO(x) UPDATE(x, 7, 0)
167 #define MIPI_PHY_REG5 PHYREG(0x0014)
168 #define MIPI_PHY_REG6 PHYREG(0x0018)
169 #define MIPI_PHY_REG7 PHYREG(0x001c)
170 #define MIPI_PHY_REG9 PHYREG(0x0024)
171 #define MIPI_PHY_REG20 PHYREG(0x0080)
172 #define REG_DIG_RSTN BIT(0)
173 #define MIPI_PHY_MAX_REGISTER PHYREG(0x0348)
174
175 #define THS_SETTLE_OFFSET 0x00
176 #define THS_SETTLE_MASK GENMASK(3, 0)
177 #define THS_SETTLE(x) UPDATE(x, 3, 0)
178 #define TLPX_OFFSET 0x14
179 #define TLPX_MASK GENMASK(5, 0)
180 #define TLPX(x) UPDATE(x, 5, 0)
181 #define THS_PREPARE_OFFSET 0x18
182 #define THS_PREPARE_MASK GENMASK(6, 0)
183 #define THS_PREPARE(x) UPDATE(x, 6, 0)
184 #define THS_ZERO_OFFSET 0x1c
185 #define THS_ZERO_MASK GENMASK(5, 0)
186 #define THS_ZERO(x) UPDATE(x, 5, 0)
187 #define THS_TRAIL_OFFSET 0x20
188 #define THS_TRAIL_MASK GENMASK(6, 0)
189 #define THS_TRAIL(x) UPDATE(x, 6, 0)
190 #define THS_EXIT_OFFSET 0x24
191 #define THS_EXIT_MASK GENMASK(4, 0)
192 #define THS_EXIT(x) UPDATE(x, 4, 0)
193 #define TCLK_POST_OFFSET 0x28
194 #define TCLK_POST_MASK GENMASK(3, 0)
195 #define TCLK_POST(x) UPDATE(x, 3, 0)
196 #define TWAKUP_HI_OFFSET 0x30
197 #define TWAKUP_HI_MASK GENMASK(1, 0)
198 #define TWAKUP_HI(x) UPDATE(x, 1, 0)
199 #define TWAKUP_LO_OFFSET 0x34
200 #define TWAKUP_LO_MASK GENMASK(7, 0)
201 #define TWAKUP_LO(x) UPDATE(x, 7, 0)
202 #define TCLK_PRE_OFFSET 0x38
203 #define TCLK_PRE_MASK GENMASK(3, 0)
204 #define TCLK_PRE(x) UPDATE(x, 3, 0)
205 #define TTA_GO_OFFSET 0x40
206 #define TTA_GO_MASK GENMASK(5, 0)
207 #define TTA_GO(x) UPDATE(x, 5, 0)
208 #define TTA_SURE_OFFSET 0x44
209 #define TTA_SURE_MASK GENMASK(5, 0)
210 #define TTA_SURE(x) UPDATE(x, 5, 0)
211 #define TTA_WAIT_OFFSET 0x48
212 #define TTA_WAIT_MASK GENMASK(5, 0)
213 #define TTA_WAIT(x) UPDATE(x, 5, 0)
214
215 #define PSEC_PER_NSEC 1000L
216 #define PSEC_PER_SEC 1000000000000LL
217
218 struct mipi_dphy {
219 struct regmap *regmap;
220 u8 prediv;
221 u16 fbdiv;
222 unsigned int rate;
223 };
224
225 struct rk618_dsi {
226 struct drm_bridge base;
227 struct drm_connector connector;
228 struct drm_display_mode mode;
229 struct drm_panel *panel;
230 struct mipi_dsi_host host;
231 struct mipi_dphy phy;
232 unsigned int channel;
233 unsigned int lanes;
234 enum mipi_dsi_pixel_format format;
235 unsigned long mode_flags;
236
237 struct device *dev;
238 struct rk618 *parent;
239 struct regmap *regmap;
240 struct clk *clock;
241 struct rockchip_drm_sub_dev sub_dev;
242 };
243
244 enum {
245 NON_BURST_MODE_SYNC_PULSE,
246 NON_BURST_MODE_SYNC_EVENT,
247 BURST_MODE,
248 };
249
250 enum {
251 PIXEL_COLOR_CODING_16BIT_1,
252 PIXEL_COLOR_CODING_16BIT_2,
253 PIXEL_COLOR_CODING_16BIT_3,
254 PIXEL_COLOR_CODING_18BIT_1,
255 PIXEL_COLOR_CODING_18BIT_2,
256 PIXEL_COLOR_CODING_24BIT,
257 };
258
bridge_to_dsi(struct drm_bridge * b)259 static inline struct rk618_dsi *bridge_to_dsi(struct drm_bridge *b)
260 {
261 return container_of(b, struct rk618_dsi, base);
262 }
263
connector_to_dsi(struct drm_connector * c)264 static inline struct rk618_dsi *connector_to_dsi(struct drm_connector *c)
265 {
266 return container_of(c, struct rk618_dsi, connector);
267 }
268
host_to_dsi(struct mipi_dsi_host * h)269 static inline struct rk618_dsi *host_to_dsi(struct mipi_dsi_host *h)
270 {
271 return container_of(h, struct rk618_dsi, host);
272 }
273
is_clk_lane(u32 offset)274 static inline bool is_clk_lane(u32 offset)
275 {
276 if (offset == 0x100)
277 return true;
278
279 return false;
280 }
281
rk618_dsi_set_hs_clk(struct rk618_dsi * dsi)282 static void rk618_dsi_set_hs_clk(struct rk618_dsi *dsi)
283 {
284 const struct drm_display_mode *mode = &dsi->mode;
285 struct mipi_dphy *phy = &dsi->phy;
286 struct device *dev = dsi->dev;
287 u32 fout, fref, prediv, fbdiv;
288 u32 min_delta = UINT_MAX;
289 unsigned int value;
290
291 if (!of_property_read_u32(dev->of_node, "rockchip,lane-rate", &value)) {
292 fout = value * USEC_PER_SEC;
293 } else {
294 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
295 unsigned int lanes = dsi->lanes;
296 u64 bandwidth;
297
298 bandwidth = (u64)mode->clock * 1000 * bpp;
299 do_div(bandwidth, lanes);
300 bandwidth = div_u64(bandwidth * 10, 9);
301 bandwidth = div_u64(bandwidth, USEC_PER_SEC);
302 bandwidth = bandwidth * USEC_PER_SEC;
303 fout = bandwidth;
304 }
305
306 if (fout > 1000000000UL)
307 fout = 1000000000UL;
308
309 fref = clk_get_rate(dsi->parent->clkin);
310
311 for (prediv = 1; prediv <= 12; prediv++) {
312 u64 tmp;
313 u32 delta;
314
315 if (fref % prediv)
316 continue;
317
318 tmp = (u64)fout * prediv;
319 do_div(tmp, fref);
320 fbdiv = tmp;
321
322 if (fbdiv < 12 || fbdiv > 511)
323 continue;
324
325 if (fbdiv == 15)
326 continue;
327
328 tmp = (u64)fbdiv * fref;
329 do_div(tmp, prediv);
330
331 delta = abs(fout - tmp);
332 if (!delta) {
333 phy->rate = tmp;
334 phy->prediv = prediv;
335 phy->fbdiv = fbdiv;
336 break;
337 } else if (delta < min_delta) {
338 phy->rate = tmp;
339 phy->prediv = prediv;
340 phy->fbdiv = fbdiv;
341 min_delta = delta;
342 }
343 }
344 }
345
rk618_dsi_phy_power_off(struct rk618_dsi * dsi)346 static void rk618_dsi_phy_power_off(struct rk618_dsi *dsi)
347 {
348 struct mipi_dphy *phy = &dsi->phy;
349
350 regmap_update_bits(phy->regmap, MIPI_PHY_REG0, LANE_EN_MASK, 0);
351 regmap_update_bits(phy->regmap, MIPI_PHY_REG1,
352 REG_DA_LDOPD | REG_DA_PLLPD,
353 REG_DA_LDOPD | REG_DA_PLLPD);
354 }
355
rk618_dsi_phy_power_on(struct rk618_dsi * dsi,u32 txclkesc)356 static void rk618_dsi_phy_power_on(struct rk618_dsi *dsi, u32 txclkesc)
357 {
358 struct mipi_dphy *phy = &dsi->phy;
359 u32 offset, value, index;
360 const struct {
361 unsigned int rate;
362 u8 ths_settle;
363 u8 ths_zero;
364 u8 ths_trail;
365 } timing_table[] = {
366 { 110000000, 0x00, 0x03, 0x0c},
367 { 150000000, 0x01, 0x04, 0x0d},
368 { 200000000, 0x02, 0x04, 0x11},
369 { 250000000, 0x03, 0x05, 0x14},
370 { 300000000, 0x04, 0x06, 0x18},
371 { 400000000, 0x05, 0x07, 0x1d},
372 { 500000000, 0x06, 0x08, 0x23},
373 { 600000000, 0x07, 0x0a, 0x29},
374 { 700000000, 0x08, 0x0b, 0x31},
375 { 800000000, 0x09, 0x0c, 0x34},
376 {1000000000, 0x0a, 0x0f, 0x40},
377 };
378 u32 Ttxbyteclkhs, UI, Ttxddrclkhs, Ttxclkesc;
379 u32 Tlpx, Ths_exit, Tclk_post, Tclk_pre, Ths_prepare;
380 u32 Tta_go, Tta_sure, Tta_wait;
381
382 Ttxbyteclkhs = div_u64(PSEC_PER_SEC, phy->rate / 8);
383 UI = Ttxddrclkhs = div_u64(PSEC_PER_SEC, phy->rate);
384 Ttxclkesc = div_u64(PSEC_PER_SEC, txclkesc);
385
386 regmap_update_bits(phy->regmap, MIPI_PHY_REG3, REG_FBDIV_HI_MASK |
387 REG_PREDIV_MASK, REG_FBDIV_HI(phy->fbdiv >> 8) |
388 REG_PREDIV(phy->prediv));
389 regmap_update_bits(phy->regmap, MIPI_PHY_REG4,
390 REG_FBDIV_LO_MASK, REG_FBDIV_LO(phy->fbdiv));
391 regmap_update_bits(phy->regmap, MIPI_PHY_REG1,
392 REG_DA_LDOPD | REG_DA_PLLPD, 0);
393
394 regmap_update_bits(phy->regmap, MIPI_PHY_REG0, LANE_EN_MASK,
395 LANE_EN_CK | GENMASK(dsi->lanes - 1 + 2, 2));
396
397 regmap_update_bits(phy->regmap, MIPI_PHY_REG1,
398 REG_DA_SYNCRST, REG_DA_SYNCRST);
399 udelay(1);
400 regmap_update_bits(phy->regmap, MIPI_PHY_REG1, REG_DA_SYNCRST, 0);
401
402 regmap_update_bits(phy->regmap, MIPI_PHY_REG20, REG_DIG_RSTN, 0);
403 udelay(1);
404 regmap_update_bits(phy->regmap, MIPI_PHY_REG20,
405 REG_DIG_RSTN, REG_DIG_RSTN);
406
407 /* XXX */
408 regmap_write(phy->regmap, MIPI_PHY_REG6, 0x11);
409 regmap_write(phy->regmap, MIPI_PHY_REG7, 0x11);
410 regmap_write(phy->regmap, MIPI_PHY_REG9, 0xcc);
411
412 if (phy->rate < 800000000)
413 regmap_update_bits(phy->regmap, MIPI_PHY_REG1,
414 REG_DA_PPFC, REG_DA_PPFC);
415 else
416 regmap_write(phy->regmap, MIPI_PHY_REG5, 0x30);
417
418 for (index = 0; index < ARRAY_SIZE(timing_table); index++)
419 if (phy->rate <= timing_table[index].rate)
420 break;
421
422 if (index == ARRAY_SIZE(timing_table))
423 --index;
424
425 for (offset = 0x100; offset <= 0x300; offset += 0x80) {
426 regmap_update_bits(phy->regmap,
427 PHYREG(offset + THS_SETTLE_OFFSET),
428 THS_SETTLE_MASK,
429 THS_SETTLE(timing_table[index].ths_settle));
430
431 /*
432 * The value of counter for HS Tlpx Time
433 * Tlpx = Tpin_txbyteclkhs * value
434 */
435 Tlpx = 60 * PSEC_PER_NSEC;
436 value = DIV_ROUND_UP(Tlpx, Ttxbyteclkhs);
437 Tlpx = Ttxbyteclkhs * value;
438 regmap_update_bits(phy->regmap,
439 PHYREG(offset + TLPX_OFFSET),
440 TLPX_MASK, TLPX(value));
441
442 /*
443 * The value of counter for HS Ths-prepare
444 * For clock lane, Ths-prepare(38ns~95ns)
445 * For data lane, Ths-prepare(40ns+4UI~85ns+6UI)
446 * Ths-prepare = Ttxddrclkhs * value
447 */
448 if (is_clk_lane(offset))
449 Ths_prepare = 65 * PSEC_PER_NSEC;
450 else
451 Ths_prepare = 65 * PSEC_PER_NSEC + 4 * UI;
452
453 value = DIV_ROUND_UP(Ths_prepare, Ttxddrclkhs);
454 regmap_update_bits(phy->regmap,
455 PHYREG(offset + THS_PREPARE_OFFSET),
456 THS_PREPARE_MASK, THS_PREPARE(value));
457
458 regmap_update_bits(phy->regmap,
459 PHYREG(offset + THS_ZERO_OFFSET),
460 THS_ZERO_MASK,
461 THS_ZERO(timing_table[index].ths_zero));
462
463 regmap_update_bits(phy->regmap,
464 PHYREG(offset + THS_TRAIL_OFFSET),
465 THS_TRAIL_MASK,
466 THS_TRAIL(timing_table[index].ths_trail));
467
468 /*
469 * The value of counter for HS Ths-exit
470 * Ths-exit = Tpin_txbyteclkhs * value
471 */
472 Ths_exit = 120 * PSEC_PER_NSEC;
473 value = DIV_ROUND_UP(Ths_exit, Ttxbyteclkhs);
474 regmap_update_bits(phy->regmap,
475 PHYREG(offset + THS_EXIT_OFFSET),
476 THS_EXIT_MASK, THS_EXIT(value));
477
478 /*
479 * The value of counter for HS Tclk-post
480 * Tclk-post = Ttxbyteclkhs * value
481 */
482 Tclk_post = 70 * PSEC_PER_NSEC + 52 * UI;
483 value = DIV_ROUND_UP(Tclk_post, Ttxbyteclkhs);
484 regmap_update_bits(phy->regmap,
485 PHYREG(offset + TCLK_POST_OFFSET),
486 TCLK_POST_MASK, TCLK_POST(value));
487
488 /*
489 * The value of counter for HS Twakup
490 * Twakup for ulpm,
491 * Twakup = Tpin_sys_clk * value
492 */
493 regmap_update_bits(phy->regmap,
494 PHYREG(offset + TWAKUP_HI_OFFSET),
495 TWAKUP_HI_MASK, TWAKUP_HI(0x3));
496 regmap_update_bits(phy->regmap,
497 PHYREG(offset + TWAKUP_LO_OFFSET),
498 TWAKUP_LO_MASK, TWAKUP_LO(0xff));
499
500 /*
501 * The value of counter for HS Tclk-pre
502 * Tclk-pre for clock lane
503 * Tclk-pre = Tpin_txbyteclkhs * value
504 */
505 Tclk_pre = 8 * UI;
506 value = DIV_ROUND_UP(Tclk_pre, Ttxbyteclkhs);
507 regmap_update_bits(phy->regmap,
508 PHYREG(offset + TCLK_PRE_OFFSET),
509 TCLK_PRE_MASK, TCLK_PRE(value));
510
511 /*
512 * The value of counter for HS Tta-go
513 * Tta-go for turnaround
514 * Tta-go = Ttxclkesc * value
515 */
516 Tta_go = 4 * Tlpx;
517 value = DIV_ROUND_UP(Tta_go, Ttxclkesc);
518 regmap_update_bits(phy->regmap,
519 PHYREG(offset + TTA_GO_OFFSET),
520 TTA_GO_MASK, TTA_GO(value));
521
522 /*
523 * The value of counter for HS Tta-sure
524 * Tta-sure for turnaround
525 * Tta-sure = Ttxclkesc * value
526 */
527 Tta_sure = 2 * Tlpx;
528 value = DIV_ROUND_UP(Tta_sure, Ttxclkesc);
529 regmap_update_bits(phy->regmap,
530 PHYREG(offset + TTA_SURE_OFFSET),
531 TTA_SURE_MASK, TTA_SURE(value));
532
533 /*
534 * The value of counter for HS Tta-wait
535 * Tta-wait for turnaround
536 * Interval from receiving ppi turnaround request to
537 * sending esc request.
538 * Tta-wait = Ttxclkesc * value
539 */
540 Tta_wait = 5 * Tlpx;
541 value = DIV_ROUND_UP(Tta_wait, Ttxclkesc);
542 regmap_update_bits(phy->regmap,
543 PHYREG(offset + TTA_WAIT_OFFSET),
544 TTA_WAIT_MASK, TTA_WAIT(value));
545 }
546 }
547
rk618_dsi_pre_enable(struct rk618_dsi * dsi)548 static int rk618_dsi_pre_enable(struct rk618_dsi *dsi)
549 {
550 struct drm_display_mode *mode = &dsi->mode;
551 u32 esc_clk_div, txclkesc;
552 u32 lanebyteclk, dpipclk;
553 u32 hsw, hbp, vsw, vfp, vbp;
554 u32 hsa_time, hbp_time, hline_time;
555 u32 value;
556 int ret;
557
558 rk618_dsi_set_hs_clk(dsi);
559
560 regmap_update_bits(dsi->regmap, DSI_PWR_UP, SHUTDOWNZ, RESET);
561
562 /* Configuration of the internal clock dividers */
563 esc_clk_div = DIV_ROUND_UP(dsi->phy.rate >> 3, 20000000);
564 txclkesc = dsi->phy.rate >> 3 / esc_clk_div;
565 value = TO_CLK_DIVIDSION(10) | TX_ESC_CLK_DIVIDSION(esc_clk_div);
566 regmap_write(dsi->regmap, DSI_CLKMGR_CFG, value);
567
568 /* The DPI interface configuration */
569 value = DPI_VID(dsi->channel);
570
571 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
572 value |= VSYNC_ACTIVE_LOW;
573 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
574 value |= HSYNC_ACTIVE_LOW;
575
576 switch (dsi->format) {
577 case MIPI_DSI_FMT_RGB666:
578 value |= DPI_COLOR_CODING(PIXEL_COLOR_CODING_18BIT_2);
579 break;
580 case MIPI_DSI_FMT_RGB666_PACKED:
581 value |= DPI_COLOR_CODING(PIXEL_COLOR_CODING_18BIT_1);
582 value |= EN18_LOOSELY;
583 break;
584 case MIPI_DSI_FMT_RGB565:
585 value |= DPI_COLOR_CODING(PIXEL_COLOR_CODING_16BIT_1);
586 break;
587 case MIPI_DSI_FMT_RGB888:
588 default:
589 value |= DPI_COLOR_CODING(PIXEL_COLOR_CODING_24BIT);
590 break;
591 }
592
593 regmap_write(dsi->regmap, DSI_DPI_CFG, value);
594
595 /* Packet handler configuration */
596 value = GEN_VID_RX(dsi->channel) | EN_CRC_RX | EN_ECC_RX | EN_BTA;
597
598 if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
599 value |= EN_EOTP_TX;
600
601 regmap_write(dsi->regmap, DSI_PCKHDL_CFG, value);
602
603 /* Video mode configuration */
604 value = EN_LP_VACT | EN_LP_VBP | EN_LP_VFP | EN_LP_VSA;
605
606 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP))
607 value |= EN_LP_HFP;
608
609 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP))
610 value |= EN_LP_HBP;
611
612 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
613 value |= VID_MODE_TYPE(BURST_MODE);
614 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
615 value |= VID_MODE_TYPE(NON_BURST_MODE_SYNC_PULSE);
616 else
617 value |= VID_MODE_TYPE(NON_BURST_MODE_SYNC_EVENT);
618
619 regmap_write(dsi->regmap, DSI_VID_MODE_CFG, value);
620
621 /* Video packet configuration */
622 regmap_write(dsi->regmap, DSI_VID_PKT_CFG,
623 VID_PKT_SIZE(mode->hdisplay));
624
625 /* Timeout timers configuration */
626 regmap_write(dsi->regmap, DSI_TO_CNT_CFG,
627 LPRX_TO_CNT(1000) | HSTX_TO_CNT(1000));
628
629 hsw = mode->hsync_end - mode->hsync_start;
630 hbp = mode->htotal - mode->hsync_end;
631 vsw = mode->vsync_end - mode->vsync_start;
632 vfp = mode->vsync_start - mode->vdisplay;
633 vbp = mode->vtotal - mode->vsync_end;
634
635 /* Line timing configuration */
636 lanebyteclk = (dsi->phy.rate >> 3) / USEC_PER_SEC;
637 dpipclk = mode->clock / USEC_PER_MSEC;
638 hline_time = DIV_ROUND_UP(mode->htotal * lanebyteclk, dpipclk);
639 hbp_time = DIV_ROUND_UP(hbp * lanebyteclk, dpipclk);
640 hsa_time = DIV_ROUND_UP(hsw * lanebyteclk, dpipclk);
641 regmap_write(dsi->regmap, DSI_TMR_LINE_CFG, HLINE_TIME(hline_time) |
642 HBP_TIME(hbp_time) | HSA_TIME(hsa_time));
643
644 /* Vertical timing configuration */
645 regmap_write(dsi->regmap, DSI_VTIMING_CFG,
646 V_ACTIVE_LINES(mode->vdisplay) | VFP_LINES(vfp) |
647 VBP_LINES(vbp) | VSA_LINES(vsw));
648
649 /* D-PHY interface configuration */
650 value = N_LANES(dsi->lanes - 1) | PHY_STOP_WAIT_TIME(0x20);
651 regmap_write(dsi->regmap, DSI_PHY_IF_CFG, value);
652
653 /* D-PHY timing configuration */
654 value = PHY_HS2LP_TIME(20) | PHY_LP2HS_TIME(16) | MAX_RD_TIME(10000);
655 regmap_write(dsi->regmap, DSI_PHY_TMR_CFG, value);
656
657 /* enables the D-PHY Clock Lane Module */
658 regmap_update_bits(dsi->regmap, DSI_PHY_RSTZ,
659 PHY_ENABLECLK, PHY_ENABLECLK);
660
661 regmap_write(dsi->regmap, DSI_INT_MSK0, 0);
662 regmap_write(dsi->regmap, DSI_INT_MSK1, 0);
663
664 regmap_update_bits(dsi->regmap, DSI_VID_MODE_CFG, EN_VIDEO_MODE, 0);
665 regmap_update_bits(dsi->regmap, DSI_CMD_MODE_CFG,
666 EN_CMD_MODE, EN_CMD_MODE);
667
668 rk618_dsi_phy_power_on(dsi, txclkesc);
669
670 /* wait for the PHY to acquire lock */
671 ret = regmap_read_poll_timeout(dsi->regmap, DSI_PHY_STATUS,
672 value, value & PHYLOCK, 50, 1000);
673 if (ret) {
674 dev_err(dsi->dev, "PHY is not locked\n");
675 return ret;
676 }
677
678 /* wait for the lane go to the stop state */
679 ret = regmap_read_poll_timeout(dsi->regmap, DSI_PHY_STATUS,
680 value, value & PHYSTOPSTATELANE,
681 50, 1000);
682 if (ret) {
683 dev_err(dsi->dev, "lane module is not in stop state\n");
684 return ret;
685 }
686
687 regmap_update_bits(dsi->regmap, DSI_PWR_UP, SHUTDOWNZ, POWER_UP);
688
689 return 0;
690 }
691
rk618_dsi_enable(struct rk618_dsi * dsi)692 static void rk618_dsi_enable(struct rk618_dsi *dsi)
693 {
694 /* controls the D-PHY PPI txrequestclkhs signal */
695 regmap_update_bits(dsi->regmap, DSI_PHY_IF_CTRL,
696 PHY_TXREQUESCLKHS, PHY_TXREQUESCLKHS);
697
698 /* enables the DPI Video mode transmission */
699 regmap_update_bits(dsi->regmap, DSI_PWR_UP, SHUTDOWNZ, RESET);
700 regmap_update_bits(dsi->regmap, DSI_CMD_MODE_CFG, EN_CMD_MODE, 0);
701 regmap_update_bits(dsi->regmap, DSI_VID_MODE_CFG,
702 EN_VIDEO_MODE, EN_VIDEO_MODE);
703 regmap_update_bits(dsi->regmap, DSI_PWR_UP, SHUTDOWNZ, POWER_UP);
704
705 dev_info(dsi->dev, "final DSI-Link bandwidth: %lu x %d Mbps\n",
706 dsi->phy.rate / USEC_PER_SEC, dsi->lanes);
707 }
708
rk618_dsi_disable(struct rk618_dsi * dsi)709 static void rk618_dsi_disable(struct rk618_dsi *dsi)
710 {
711 /* enables the Command mode protocol for transmissions */
712 regmap_update_bits(dsi->regmap, DSI_PWR_UP, SHUTDOWNZ, RESET);
713 regmap_update_bits(dsi->regmap, DSI_PHY_IF_CTRL, PHY_TXREQUESCLKHS, 0);
714 regmap_update_bits(dsi->regmap, DSI_VID_MODE_CFG, EN_VIDEO_MODE, 0);
715 regmap_update_bits(dsi->regmap, DSI_CMD_MODE_CFG,
716 EN_CMD_MODE, EN_CMD_MODE);
717 regmap_update_bits(dsi->regmap, DSI_PWR_UP, SHUTDOWNZ, POWER_UP);
718 }
719
rk618_dsi_post_disable(struct rk618_dsi * dsi)720 static void rk618_dsi_post_disable(struct rk618_dsi *dsi)
721 {
722 regmap_update_bits(dsi->regmap, DSI_PWR_UP, SHUTDOWNZ, RESET);
723 regmap_update_bits(dsi->regmap, DSI_PHY_RSTZ, PHY_ENABLECLK, 0);
724
725 rk618_dsi_phy_power_off(dsi);
726 }
727
728 static struct drm_encoder *
rk618_dsi_connector_best_encoder(struct drm_connector * connector)729 rk618_dsi_connector_best_encoder(struct drm_connector *connector)
730 {
731 struct rk618_dsi *dsi = connector_to_dsi(connector);
732
733 return dsi->base.encoder;
734 }
735
rk618_dsi_connector_get_modes(struct drm_connector * connector)736 static int rk618_dsi_connector_get_modes(struct drm_connector *connector)
737 {
738 struct rk618_dsi *dsi = connector_to_dsi(connector);
739
740 return drm_panel_get_modes(dsi->panel, connector);
741 }
742
743 static const struct drm_connector_helper_funcs
744 rk618_dsi_connector_helper_funcs = {
745 .get_modes = rk618_dsi_connector_get_modes,
746 .best_encoder = rk618_dsi_connector_best_encoder,
747 };
748
749 static enum drm_connector_status
rk618_dsi_connector_detect(struct drm_connector * connector,bool force)750 rk618_dsi_connector_detect(struct drm_connector *connector, bool force)
751 {
752 return connector_status_connected;
753 }
754
rk618_dsi_connector_destroy(struct drm_connector * connector)755 static void rk618_dsi_connector_destroy(struct drm_connector *connector)
756 {
757 drm_connector_cleanup(connector);
758 }
759
760 static const struct drm_connector_funcs rk618_dsi_connector_funcs = {
761 .detect = rk618_dsi_connector_detect,
762 .fill_modes = drm_helper_probe_single_connector_modes,
763 .destroy = rk618_dsi_connector_destroy,
764 .reset = drm_atomic_helper_connector_reset,
765 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
766 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
767 };
768
rk618_dsi_bridge_enable(struct drm_bridge * bridge)769 static void rk618_dsi_bridge_enable(struct drm_bridge *bridge)
770 {
771 struct rk618_dsi *dsi = bridge_to_dsi(bridge);
772
773 clk_prepare_enable(dsi->clock);
774
775 rk618_dsi_pre_enable(dsi);
776 drm_panel_prepare(dsi->panel);
777 rk618_dsi_enable(dsi);
778 drm_panel_enable(dsi->panel);
779 }
780
rk618_dsi_bridge_disable(struct drm_bridge * bridge)781 static void rk618_dsi_bridge_disable(struct drm_bridge *bridge)
782 {
783 struct rk618_dsi *dsi = bridge_to_dsi(bridge);
784
785 drm_panel_disable(dsi->panel);
786 rk618_dsi_disable(dsi);
787 drm_panel_unprepare(dsi->panel);
788 rk618_dsi_post_disable(dsi);
789
790 clk_disable_unprepare(dsi->clock);
791 }
792
rk618_dsi_bridge_mode_set(struct drm_bridge * bridge,const struct drm_display_mode * mode,const struct drm_display_mode * adj)793 static void rk618_dsi_bridge_mode_set(struct drm_bridge *bridge,
794 const struct drm_display_mode *mode,
795 const struct drm_display_mode *adj)
796 {
797 struct rk618_dsi *dsi = bridge_to_dsi(bridge);
798
799 if (bridge->driver_private)
800 drm_mode_copy(&dsi->mode, bridge->driver_private);
801 else
802 drm_mode_copy(&dsi->mode, adj);
803 }
804
rk618_dsi_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)805 static int rk618_dsi_bridge_attach(struct drm_bridge *bridge,
806 enum drm_bridge_attach_flags flags)
807 {
808 struct rk618_dsi *dsi = bridge_to_dsi(bridge);
809 struct drm_connector *connector = &dsi->connector;
810 struct drm_device *drm = bridge->dev;
811 int ret;
812
813 ret = drm_connector_init(drm, connector, &rk618_dsi_connector_funcs,
814 DRM_MODE_CONNECTOR_DSI);
815 if (ret) {
816 dev_err(dsi->dev, "Failed to initialize connector with drm\n");
817 return ret;
818 }
819
820 drm_connector_helper_add(connector, &rk618_dsi_connector_helper_funcs);
821 drm_connector_attach_encoder(connector, bridge->encoder);
822
823 dsi->sub_dev.connector = &dsi->connector;
824 dsi->sub_dev.of_node = dsi->dev->of_node;
825 rockchip_drm_register_sub_dev(&dsi->sub_dev);
826
827 return 0;
828 }
829
rk618_dsi_bridge_detach(struct drm_bridge * bridge)830 static void rk618_dsi_bridge_detach(struct drm_bridge *bridge)
831 {
832 struct rk618_dsi *dsi = bridge_to_dsi(bridge);
833
834 rockchip_drm_unregister_sub_dev(&dsi->sub_dev);
835 }
836
837 static const struct drm_bridge_funcs rk618_dsi_bridge_funcs = {
838 .attach = rk618_dsi_bridge_attach,
839 .detach = rk618_dsi_bridge_detach,
840 .mode_set = rk618_dsi_bridge_mode_set,
841 .enable = rk618_dsi_bridge_enable,
842 .disable = rk618_dsi_bridge_disable,
843 };
844
rk618_dsi_host_transfer(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)845 static ssize_t rk618_dsi_host_transfer(struct mipi_dsi_host *host,
846 const struct mipi_dsi_msg *msg)
847 {
848 struct rk618_dsi *dsi = host_to_dsi(host);
849 struct mipi_dsi_packet packet;
850 u32 value, mask;
851 int ret;
852
853 if (msg->flags & MIPI_DSI_MSG_USE_LPM)
854 regmap_update_bits(dsi->regmap, DSI_PHY_IF_CTRL,
855 PHY_TXREQUESCLKHS, 0);
856 else
857 regmap_update_bits(dsi->regmap, DSI_PHY_IF_CTRL,
858 PHY_TXREQUESCLKHS, PHY_TXREQUESCLKHS);
859
860 switch (msg->type) {
861 case MIPI_DSI_DCS_SHORT_WRITE:
862 regmap_update_bits(dsi->regmap, DSI_CMD_MODE_CFG, DCS_SW_0P_TX,
863 msg->flags & MIPI_DSI_MSG_USE_LPM ?
864 DCS_SW_0P_TX : 0);
865 break;
866 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
867 regmap_update_bits(dsi->regmap, DSI_CMD_MODE_CFG, DCS_SW_1P_TX,
868 msg->flags & MIPI_DSI_MSG_USE_LPM ?
869 DCS_SW_1P_TX : 0);
870 break;
871 case MIPI_DSI_DCS_LONG_WRITE:
872 regmap_update_bits(dsi->regmap, DSI_CMD_MODE_CFG, DCS_LW_TX,
873 msg->flags & MIPI_DSI_MSG_USE_LPM ?
874 DCS_LW_TX : 0);
875 break;
876 case MIPI_DSI_DCS_READ:
877 regmap_update_bits(dsi->regmap, DSI_CMD_MODE_CFG, DCS_SR_0P_TX,
878 msg->flags & MIPI_DSI_MSG_USE_LPM ?
879 DCS_SR_0P_TX : 0);
880 break;
881 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
882 regmap_update_bits(dsi->regmap, DSI_CMD_MODE_CFG,
883 MAX_RD_PKT_SIZE,
884 msg->flags & MIPI_DSI_MSG_USE_LPM ?
885 MAX_RD_PKT_SIZE : 0);
886 break;
887 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
888 regmap_update_bits(dsi->regmap, DSI_CMD_MODE_CFG, GEN_SW_0P_TX,
889 msg->flags & MIPI_DSI_MSG_USE_LPM ?
890 GEN_SW_0P_TX : 0);
891 break;
892 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
893 regmap_update_bits(dsi->regmap, DSI_CMD_MODE_CFG, GEN_SW_1P_TX,
894 msg->flags & MIPI_DSI_MSG_USE_LPM ?
895 GEN_SW_1P_TX : 0);
896 break;
897 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
898 regmap_update_bits(dsi->regmap, DSI_CMD_MODE_CFG, GEN_SW_2P_TX,
899 msg->flags & MIPI_DSI_MSG_USE_LPM ?
900 GEN_SW_2P_TX : 0);
901 break;
902 case MIPI_DSI_GENERIC_LONG_WRITE:
903 regmap_update_bits(dsi->regmap, DSI_CMD_MODE_CFG, GEN_LW_TX,
904 msg->flags & MIPI_DSI_MSG_USE_LPM ?
905 GEN_LW_TX : 0);
906 break;
907 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
908 regmap_update_bits(dsi->regmap, DSI_CMD_MODE_CFG, GEN_SR_0P_TX,
909 msg->flags & MIPI_DSI_MSG_USE_LPM ?
910 GEN_SR_0P_TX : 0);
911 break;
912 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
913 regmap_update_bits(dsi->regmap, DSI_CMD_MODE_CFG, GEN_SR_1P_TX,
914 msg->flags & MIPI_DSI_MSG_USE_LPM ?
915 GEN_SR_1P_TX : 0);
916 break;
917 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
918 regmap_update_bits(dsi->regmap, DSI_CMD_MODE_CFG, GEN_SR_2P_TX,
919 msg->flags & MIPI_DSI_MSG_USE_LPM ?
920 GEN_SR_2P_TX : 0);
921 break;
922 default:
923 return -EINVAL;
924 }
925
926 /* create a packet to the DSI protocol */
927 ret = mipi_dsi_create_packet(&packet, msg);
928 if (ret) {
929 dev_err(dsi->dev, "failed to create packet: %d\n", ret);
930 return ret;
931 }
932
933 /* Send payload */
934 while (packet.payload_length >= 4) {
935 mask = GEN_PLD_W_FULL;
936 ret = regmap_read_poll_timeout(dsi->regmap, DSI_GEN_PKT_STATUS,
937 value, !(value & mask),
938 50, 1000);
939 if (ret) {
940 dev_err(dsi->dev, "Write payload FIFO is full\n");
941 return ret;
942 }
943
944 value = get_unaligned_le32(packet.payload);
945 regmap_write(dsi->regmap, DSI_GEN_PLD_DATA, value);
946 packet.payload += 4;
947 packet.payload_length -= 4;
948 }
949
950 value = 0;
951 switch (packet.payload_length) {
952 case 3:
953 value |= packet.payload[2] << 16;
954 /* Fall through */
955 case 2:
956 value |= packet.payload[1] << 8;
957 /* Fall through */
958 case 1:
959 value |= packet.payload[0];
960 regmap_write(dsi->regmap, DSI_GEN_PLD_DATA, value);
961 break;
962 }
963
964 mask = GEN_CMD_FULL;
965 ret = regmap_read_poll_timeout(dsi->regmap, DSI_GEN_PKT_STATUS,
966 value, !(value & mask), 50, 1000);
967 if (ret) {
968 dev_err(dsi->dev, "Command FIFO is full\n");
969 return ret;
970 }
971
972 /* Send packet header */
973 value = get_unaligned_le32(packet.header);
974 regmap_write(dsi->regmap, DSI_GEN_HDR, value);
975
976 mask = GEN_PLD_W_EMPTY | GEN_CMD_EMPTY;
977 ret = regmap_read_poll_timeout(dsi->regmap, DSI_GEN_PKT_STATUS,
978 value, (value & mask) == mask, 50, 1000);
979 if (ret) {
980 dev_err(dsi->dev, "Write payload FIFO is not empty\n");
981 return ret;
982 }
983
984 if (msg->rx_len) {
985 u8 *payload = msg->rx_buf;
986 u16 length;
987
988 mask = GEN_RD_CMD_BUSY;
989 ret = regmap_read_poll_timeout(dsi->regmap, DSI_GEN_PKT_STATUS,
990 value, !(value & mask),
991 50, 1000);
992 if (ret) {
993 dev_err(dsi->dev,
994 "entire response is not stored in the FIFO\n");
995 return ret;
996 }
997
998 /* Receive payload */
999 for (length = msg->rx_len; length; length -= 4) {
1000 mask = GEN_PLD_R_EMPTY;
1001 ret = regmap_read_poll_timeout(dsi->regmap,
1002 DSI_GEN_PKT_STATUS,
1003 value, !(value & mask),
1004 50, 1000);
1005 if (ret) {
1006 dev_err(dsi->dev,
1007 "Read payload FIFO is empty\n");
1008 return ret;
1009 }
1010
1011 regmap_read(dsi->regmap, DSI_GEN_PLD_DATA, &value);
1012
1013 switch (length) {
1014 case 3:
1015 payload[2] = (value >> 16) & 0xff;
1016 /* Fall through */
1017 case 2:
1018 payload[1] = (value >> 8) & 0xff;
1019 /* Fall through */
1020 case 1:
1021 payload[0] = value & 0xff;
1022 return length;
1023 }
1024
1025 payload[0] = (value >> 0) & 0xff;
1026 payload[1] = (value >> 8) & 0xff;
1027 payload[2] = (value >> 16) & 0xff;
1028 payload[3] = (value >> 24) & 0xff;
1029 payload += 4;
1030 }
1031 }
1032
1033 return packet.payload_length;
1034 }
1035
rk618_dsi_host_attach(struct mipi_dsi_host * host,struct mipi_dsi_device * device)1036 static int rk618_dsi_host_attach(struct mipi_dsi_host *host,
1037 struct mipi_dsi_device *device)
1038 {
1039 struct rk618_dsi *dsi = host_to_dsi(host);
1040
1041 if (device->lanes < 1 || device->lanes > 4)
1042 return -EINVAL;
1043
1044 dsi->lanes = device->lanes;
1045 dsi->channel = device->channel;
1046 dsi->format = device->format;
1047 dsi->mode_flags = device->mode_flags;
1048
1049 dsi->panel = of_drm_find_panel(device->dev.of_node);
1050 if (!dsi->panel)
1051 return -EPROBE_DEFER;
1052
1053 return 0;
1054 }
1055
rk618_dsi_host_detach(struct mipi_dsi_host * host,struct mipi_dsi_device * device)1056 static int rk618_dsi_host_detach(struct mipi_dsi_host *host,
1057 struct mipi_dsi_device *device)
1058 {
1059 return 0;
1060 }
1061
1062 static const struct mipi_dsi_host_ops rk618_dsi_host_ops = {
1063 .attach = rk618_dsi_host_attach,
1064 .detach = rk618_dsi_host_detach,
1065 .transfer = rk618_dsi_host_transfer,
1066 };
1067
rk618_dsi_readable_reg(struct device * dev,unsigned int reg)1068 static bool rk618_dsi_readable_reg(struct device *dev, unsigned int reg)
1069 {
1070 switch (reg) {
1071 case DSI_VERSION ... DSI_MAX_REGISTER:
1072 return true;
1073 default:
1074 return false;
1075 }
1076 }
1077
1078 static const struct regmap_config rk618_dsi_host_regmap_config = {
1079 .name = "dsi",
1080 .reg_bits = 16,
1081 .val_bits = 32,
1082 .reg_stride = 4,
1083 .max_register = DSI_MAX_REGISTER,
1084 .reg_format_endian = REGMAP_ENDIAN_NATIVE,
1085 .val_format_endian = REGMAP_ENDIAN_NATIVE,
1086 .readable_reg = rk618_dsi_readable_reg,
1087 };
1088
rk618_dsi_phy_readable_reg(struct device * dev,unsigned int reg)1089 static bool rk618_dsi_phy_readable_reg(struct device *dev, unsigned int reg)
1090 {
1091 switch (reg) {
1092 case MIPI_PHY_REG0 ... MIPI_PHY_MAX_REGISTER:
1093 return true;
1094 default:
1095 return false;
1096 }
1097 }
1098
1099 static const struct regmap_config rk618_dsi_phy_regmap_config = {
1100 .name = "dphy",
1101 .reg_bits = 16,
1102 .val_bits = 32,
1103 .reg_stride = 4,
1104 .max_register = MIPI_PHY_MAX_REGISTER,
1105 .reg_format_endian = REGMAP_ENDIAN_NATIVE,
1106 .val_format_endian = REGMAP_ENDIAN_NATIVE,
1107 .readable_reg = rk618_dsi_phy_readable_reg,
1108 };
1109
rk618_dsi_probe(struct platform_device * pdev)1110 static int rk618_dsi_probe(struct platform_device *pdev)
1111 {
1112 struct rk618 *rk618 = dev_get_drvdata(pdev->dev.parent);
1113 struct device *dev = &pdev->dev;
1114 struct rk618_dsi *dsi;
1115 int ret;
1116
1117 if (!of_device_is_available(dev->of_node))
1118 return -ENODEV;
1119
1120 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1121 if (!dsi)
1122 return -ENOMEM;
1123
1124 dsi->dev = dev;
1125 dsi->parent = rk618;
1126 platform_set_drvdata(pdev, dsi);
1127
1128 dsi->clock = devm_clk_get(dev, "dsi");
1129 if (IS_ERR(dsi->clock)) {
1130 ret = PTR_ERR(dsi->clock);
1131 dev_err(dev, "failed to get dsi clock: %d\n", ret);
1132 return ret;
1133 }
1134
1135 dsi->regmap = devm_regmap_init_i2c(rk618->client,
1136 &rk618_dsi_host_regmap_config);
1137 if (IS_ERR(dsi->regmap)) {
1138 ret = PTR_ERR(dsi->regmap);
1139 dev_err(dev, "failed to allocate host register map: %d\n", ret);
1140 return ret;
1141 }
1142
1143 dsi->phy.regmap = devm_regmap_init_i2c(rk618->client,
1144 &rk618_dsi_phy_regmap_config);
1145 if (IS_ERR(dsi->phy.regmap)) {
1146 ret = PTR_ERR(dsi->phy.regmap);
1147 dev_err(dev, "failed to allocate phy register map: %d\n", ret);
1148 return ret;
1149 }
1150
1151 dsi->base.funcs = &rk618_dsi_bridge_funcs;
1152 dsi->base.of_node = dev->of_node;
1153 drm_bridge_add(&dsi->base);
1154
1155 dsi->host.dev = dev;
1156 dsi->host.ops = &rk618_dsi_host_ops;
1157 ret = mipi_dsi_host_register(&dsi->host);
1158 if (ret) {
1159 drm_bridge_remove(&dsi->base);
1160 dev_err(dev, "failed to register host: %d\n", ret);
1161 return ret;
1162 }
1163
1164 return 0;
1165 }
1166
rk618_dsi_remove(struct platform_device * pdev)1167 static int rk618_dsi_remove(struct platform_device *pdev)
1168 {
1169 struct rk618_dsi *dsi = platform_get_drvdata(pdev);
1170
1171 mipi_dsi_host_unregister(&dsi->host);
1172 drm_bridge_remove(&dsi->base);
1173
1174 return 0;
1175 }
1176
1177 static const struct of_device_id rk618_dsi_of_match[] = {
1178 { .compatible = "rockchip,rk618-dsi", },
1179 {},
1180 };
1181 MODULE_DEVICE_TABLE(of, rk618_dsi_of_match);
1182
1183 static struct platform_driver rk618_dsi_driver = {
1184 .driver = {
1185 .name = "rk618-dsi",
1186 .of_match_table = of_match_ptr(rk618_dsi_of_match),
1187 },
1188 .probe = rk618_dsi_probe,
1189 .remove = rk618_dsi_remove,
1190 };
1191 module_platform_driver(rk618_dsi_driver);
1192
1193 MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
1194 MODULE_DESCRIPTION("Rockchip RK618 MIPI-DSI driver");
1195 MODULE_LICENSE("GPL v2");
1196