1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) Rockchip Electronics Co.Ltd
4 * Author:
5 * Guochun Huang <hero.huang@rock-chips.com>
6 */
7
8 #include <linux/clk.h>
9 #include <linux/component.h>
10 #include <linux/gpio.h>
11 #include <linux/iopoll.h>
12 #include <linux/math64.h>
13 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/of_gpio.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 #include <linux/reset.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/phy/phy.h>
21
22 #include <drm/drm_atomic_helper.h>
23 #include <drm/drm_crtc.h>
24 #include <drm/drm_crtc_helper.h>
25 #include <drm/drm_dsc.h>
26 #include <drm/drm_mipi_dsi.h>
27 #include <drm/drm_of.h>
28 #include <drm/drm_panel.h>
29 #include <video/mipi_display.h>
30 #include <video/videomode.h>
31 #include <asm/unaligned.h>
32 #include <uapi/linux/videodev2.h>
33 #include <drm/drm_panel.h>
34 #include <drm/drm_connector.h>
35 #include <drm/drm_probe_helper.h>
36 #include <drm/drm_simple_kms_helper.h>
37
38 #include "rockchip_drm_drv.h"
39 #include "rockchip_drm_vop.h"
40
41 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l)))
42
43 #define DSI2_PWR_UP 0x000c
44 #define RESET 0
45 #define POWER_UP BIT(0)
46 #define CMD_TX_MODE(x) UPDATE(x, 24, 24)
47 #define DSI2_SOFT_RESET 0x0010
48 #define SYS_RSTN BIT(2)
49 #define PHY_RSTN BIT(1)
50 #define IPI_RSTN BIT(0)
51 #define INT_ST_MAIN 0x0014
52 #define DSI2_MODE_CTRL 0x0018
53 #define DSI2_MODE_STATUS 0x001c
54 #define DSI2_CORE_STATUS 0x0020
55 #define PRI_RD_DATA_AVAIL BIT(26)
56 #define PRI_FIFOS_NOT_EMPTY BIT(25)
57 #define PRI_BUSY BIT(24)
58 #define CRI_RD_DATA_AVAIL BIT(18)
59 #define CRT_FIFOS_NOT_EMPTY BIT(17)
60 #define CRI_BUSY BIT(16)
61 #define IPI_FIFOS_NOT_EMPTY BIT(9)
62 #define IPI_BUSY BIT(8)
63 #define CORE_FIFOS_NOT_EMPTY BIT(1)
64 #define CORE_BUSY BIT(0)
65 #define MANUAL_MODE_CFG 0x0024
66 #define MANUAL_MODE_EN BIT(0)
67 #define DSI2_TIMEOUT_HSTX_CFG 0x0048
68 #define TO_HSTX(x) UPDATE(x, 15, 0)
69 #define DSI2_TIMEOUT_HSTXRDY_CFG 0x004c
70 #define TO_HSTXRDY(x) UPDATE(x, 15, 0)
71 #define DSI2_TIMEOUT_LPRX_CFG 0x0050
72 #define TO_LPRXRDY(x) UPDATE(x, 15, 0)
73 #define DSI2_TIMEOUT_LPTXRDY_CFG 0x0054
74 #define TO_LPTXRDY(x) UPDATE(x, 15, 0)
75 #define DSI2_TIMEOUT_LPTXTRIG_CFG 0x0058
76 #define TO_LPTXTRIG(x) UPDATE(x, 15, 0)
77 #define DSI2_TIMEOUT_LPTXULPS_CFG 0x005c
78 #define TO_LPTXULPS(x) UPDATE(x, 15, 0)
79 #define DSI2_TIMEOUT_BTA_CFG 0x60
80 #define TO_BTA(x) UPDATE(x, 15, 0)
81
82 #define DSI2_PHY_MODE_CFG 0x0100
83 #define PPI_WIDTH(x) UPDATE(x, 9, 8)
84 #define PHY_LANES(x) UPDATE(x - 1, 5, 4)
85 #define PHY_TYPE(x) UPDATE(x, 0, 0)
86 #define DSI2_PHY_CLK_CFG 0X0104
87 #define PHY_LPTX_CLK_DIV(x) UPDATE(x, 12, 8)
88 #define CLK_TYPE_MASK BIT(0)
89 #define NON_CONTINUOUS_CLK BIT(0)
90 #define CONTIUOUS_CLK 0
91 #define DSI2_PHY_LP2HS_MAN_CFG 0x010c
92 #define PHY_LP2HS_TIME(x) UPDATE(x, 28, 0)
93 #define DSI2_PHY_HS2LP_MAN_CFG 0x0114
94 #define PHY_HS2LP_TIME(x) UPDATE(x, 28, 0)
95 #define DSI2_PHY_MAX_RD_T_MAN_CFG 0x011c
96 #define PHY_MAX_RD_TIME(x) UPDATE(x, 26, 0)
97 #define DSI2_PHY_ESC_CMD_T_MAN_CFG 0x0124
98 #define PHY_ESC_CMD_TIME(x) UPDATE(x, 28, 0)
99 #define DSI2_PHY_ESC_BYTE_T_MAN_CFG 0x012c
100 #define PHY_ESC_BYTE_TIME(x) UPDATE(x, 28, 0)
101
102 #define DSI2_PHY_IPI_RATIO_MAN_CFG 0x0134
103 #define PHY_IPI_RATIO(x) UPDATE(x, 21, 0)
104 #define DSI2_PHY_SYS_RATIO_MAN_CFG 0x013C
105 #define PHY_SYS_RATIO(x) UPDATE(x, 16, 0)
106
107 #define DSI2_DSI_GENERAL_CFG 0x0200
108 #define BTA_EN BIT(1)
109 #define EOTP_TX_EN BIT(0)
110 #define DSI2_DSI_VCID_CFG 0x0204
111 #define TX_VCID(x) UPDATE(x, 1, 0)
112 #define DSI2_DSI_SCRAMBLING_CFG 0x0208
113 #define SCRAMBLING_SEED(x) UPDATE(x, 31, 16)
114 #define SCRAMBLING_EN BIT(0)
115 #define DSI2_DSI_VID_TX_CFG 0x020c
116 #define LPDT_DISPLAY_CMD_EN BIT(20)
117 #define BLK_VFP_HS_EN BIT(14)
118 #define BLK_VBP_HS_EN BIT(13)
119 #define BLK_VSA_HS_EN BIT(12)
120 #define BLK_HFP_HS_EN BIT(6)
121 #define BLK_HBP_HS_EN BIT(5)
122 #define BLK_HSA_HS_EN BIT(4)
123 #define VID_MODE_TYPE(x) UPDATE(x, 1, 0)
124 #define DSI2_CRI_TX_HDR 0x02c0
125 #define CMD_TX_MODE(x) UPDATE(x, 24, 24)
126 #define DSI2_CRI_TX_PLD 0x02c4
127 #define DSI2_CRI_RX_HDR 0x02c8
128 #define DSI2_CRI_RX_PLD 0x02cc
129
130 #define DSI2_IPI_COLOR_MAN_CFG 0x0300
131 #define IPI_DEPTH(x) UPDATE(x, 7, 4)
132 #define IPI_DEPTH_5_6_5_BITS 0x02
133 #define IPI_DEPTH_6_BITS 0x03
134 #define IPI_DEPTH_8_BITS 0x05
135 #define IPI_DEPTH_10_BITS 0x06
136 #define IPI_FORMAT(x) UPDATE(x, 3, 0)
137 #define IPI_FORMAT_RGB 0x0
138 #define IPI_FORMAT_DSC 0x0b
139 #define DSI2_IPI_VID_HSA_MAN_CFG 0x0304
140 #define VID_HSA_TIME(x) UPDATE(x, 29, 0)
141 #define DSI2_IPI_VID_HBP_MAN_CFG 0x030c
142 #define VID_HBP_TIME(x) UPDATE(x, 29, 0)
143 #define DSI2_IPI_VID_HACT_MAN_CFG 0x0314
144 #define VID_HACT_TIME(x) UPDATE(x, 29, 0)
145 #define DSI2_IPI_VID_HLINE_MAN_CFG 0x031c
146 #define VID_HLINE_TIME(x) UPDATE(x, 29, 0)
147 #define DSI2_IPI_VID_VSA_MAN_CFG 0x0324
148 #define VID_VSA_LINES(x) UPDATE(x, 9, 0)
149 #define DSI2_IPI_VID_VBP_MAN_CFG 0X032C
150 #define VID_VBP_LINES(x) UPDATE(x, 9, 0)
151 #define DSI2_IPI_VID_VACT_MAN_CFG 0X0334
152 #define VID_VACT_LINES(x) UPDATE(x, 13, 0)
153 #define DSI2_IPI_VID_VFP_MAN_CFG 0X033C
154 #define VID_VFP_LINES(x) UPDATE(x, 9, 0)
155 #define DSI2_IPI_PIX_PKT_CFG 0x0344
156 #define MAX_PIX_PKT(x) UPDATE(x, 15, 0)
157
158 #define DSI2_INT_ST_PHY 0x0400
159 #define DSI2_INT_MASK_PHY 0x0404
160 #define DSI2_INT_ST_TO 0x0410
161 #define DSI2_INT_MASK_TO 0x0414
162 #define DSI2_INT_ST_ACK 0x0420
163 #define DSI2_INT_MASK_ACK 0x0424
164 #define DSI2_INT_ST_IPI 0x0430
165 #define DSI2_INT_MASK_IPI 0x0434
166 #define DSI2_INT_ST_FIFO 0x0440
167 #define DSI2_INT_MASK_FIFO 0x0444
168 #define DSI2_INT_ST_PRI 0x0450
169 #define DSI2_INT_MASK_PRI 0x0454
170 #define DSI2_INT_ST_CRI 0x0460
171 #define DSI2_INT_MASK_CRI 0x0464
172 #define DSI2_INT_FORCE_CRI 0x0468
173 #define DSI2_MAX_REGISGER DSI2_INT_FORCE_CRI
174
175 #define MODE_STATUS_TIMEOUT_US 10000
176 #define CMD_PKT_STATUS_TIMEOUT_US 20000
177 #define PSEC_PER_SEC 1000000000000LL
178
179 #define GRF_REG_FIELD(reg, lsb, msb) (((reg) << 16) | ((lsb) << 8) | (msb))
180
181 enum vid_mode_type {
182 VID_MODE_TYPE_NON_BURST_SYNC_PULSES,
183 VID_MODE_TYPE_NON_BURST_SYNC_EVENTS,
184 VID_MODE_TYPE_BURST,
185 };
186
187 enum mode_ctrl {
188 IDLE_MODE,
189 AUTOCALC_MODE,
190 COMMAND_MODE,
191 VIDEO_MODE,
192 DATA_STREAM_MODE,
193 VIDE_TEST_MODE,
194 DATA_STREAM_TEST_MODE,
195 };
196
197 enum grf_reg_fields {
198 TXREQCLKHS_EN,
199 GATING_EN,
200 IPI_SHUTDN,
201 IPI_COLORM,
202 IPI_COLOR_DEPTH,
203 IPI_FORMAT,
204 MAX_FIELDS,
205 };
206
207 enum phy_type {
208 DPHY,
209 CPHY,
210 };
211
212 enum ppi_width {
213 PPI_WIDTH_8_BITS,
214 PPI_WIDTH_16_BITS,
215 PPI_WIDTH_32_BITS,
216 };
217
218 struct cmd_header {
219 u8 cmd_type;
220 u8 delay;
221 u8 payload_length;
222 };
223
224 struct dw_mipi_dsi2_plat_data {
225 const u32 *dsi0_grf_reg_fields;
226 const u32 *dsi1_grf_reg_fields;
227 unsigned long long dphy_max_bit_rate_per_lane;
228 unsigned long long cphy_max_symbol_rate_per_lane;
229
230 };
231
232 struct dw_mipi_dsi2 {
233 struct drm_device *drm_dev;
234 struct drm_encoder encoder;
235 struct drm_connector connector;
236 struct drm_bridge *bridge;
237 struct mipi_dsi_host host;
238 struct drm_panel *panel;
239 struct drm_display_mode mode;
240 struct device *dev;
241 struct device_node *client;
242 struct regmap *grf;
243 struct clk *pclk;
244 struct clk *sys_clk;
245 bool phy_enabled;
246 struct phy *dcphy;
247 union phy_configure_opts phy_opts;
248
249 bool c_option;
250 bool scrambling_en;
251 unsigned int slice_width;
252 unsigned int slice_height;
253 bool dsc_enable;
254 u8 version_major;
255 u8 version_minor;
256
257 struct drm_dsc_picture_parameter_set *pps;
258 struct regmap *regmap;
259 struct reset_control *apb_rst;
260 int irq;
261 int id;
262
263 /* dual-channel */
264 struct dw_mipi_dsi2 *master;
265 struct dw_mipi_dsi2 *slave;
266 bool data_swap;
267
268 unsigned int lane_hs_rate; /* Mbps or Msps per lane */
269 u32 channel;
270 u32 lanes;
271 u32 format;
272 unsigned long mode_flags;
273
274 const struct dw_mipi_dsi2_plat_data *pdata;
275 struct rockchip_drm_sub_dev sub_dev;
276
277 struct gpio_desc *te_gpio;
278
279 /* split with other display interface */
280 bool dual_connector_split;
281 bool left_display;
282 u32 split_area;
283 };
284
host_to_dsi2(struct mipi_dsi_host * host)285 static inline struct dw_mipi_dsi2 *host_to_dsi2(struct mipi_dsi_host *host)
286 {
287 return container_of(host, struct dw_mipi_dsi2, host);
288 }
289
con_to_dsi2(struct drm_connector * con)290 static inline struct dw_mipi_dsi2 *con_to_dsi2(struct drm_connector *con)
291 {
292 return container_of(con, struct dw_mipi_dsi2, connector);
293 }
294
encoder_to_dsi2(struct drm_encoder * encoder)295 static inline struct dw_mipi_dsi2 *encoder_to_dsi2(struct drm_encoder *encoder)
296 {
297 return container_of(encoder, struct dw_mipi_dsi2, encoder);
298 }
299
grf_field_write(struct dw_mipi_dsi2 * dsi2,enum grf_reg_fields index,unsigned int val)300 static void grf_field_write(struct dw_mipi_dsi2 *dsi2, enum grf_reg_fields index,
301 unsigned int val)
302 {
303 const u32 field = dsi2->id ?
304 dsi2->pdata->dsi1_grf_reg_fields[index] :
305 dsi2->pdata->dsi0_grf_reg_fields[index];
306 u16 reg;
307 u8 msb, lsb;
308
309 if (!field)
310 return;
311
312 reg = (field >> 16) & 0xffff;
313 lsb = (field >> 8) & 0xff;
314 msb = (field >> 0) & 0xff;
315
316 regmap_write(dsi2->grf, reg, (val << lsb) | (GENMASK(msb, lsb) << 16));
317 }
318
cri_fifos_wait_avail(struct dw_mipi_dsi2 * dsi2)319 static int cri_fifos_wait_avail(struct dw_mipi_dsi2 *dsi2)
320 {
321 u32 sts, mask;
322 int ret;
323
324 mask = CRI_BUSY | CRT_FIFOS_NOT_EMPTY;
325 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_CORE_STATUS, sts,
326 !(sts & mask), 0,
327 CMD_PKT_STATUS_TIMEOUT_US);
328 if (ret < 0) {
329 DRM_DEV_ERROR(dsi2->dev, "command interface is busy\n");
330 return ret;
331 }
332
333 return 0;
334 }
335
dw_mipi_dsi2_irq_enable(struct dw_mipi_dsi2 * dsi2,bool enable)336 static void dw_mipi_dsi2_irq_enable(struct dw_mipi_dsi2 *dsi2, bool enable)
337 {
338 if (enable) {
339 regmap_write(dsi2->regmap, DSI2_INT_MASK_PHY, 0x1);
340 regmap_write(dsi2->regmap, DSI2_INT_MASK_TO, 0xf);
341 regmap_write(dsi2->regmap, DSI2_INT_MASK_ACK, 0x1);
342 regmap_write(dsi2->regmap, DSI2_INT_MASK_IPI, 0x1);
343 regmap_write(dsi2->regmap, DSI2_INT_MASK_FIFO, 0x1);
344 regmap_write(dsi2->regmap, DSI2_INT_MASK_PRI, 0x1);
345 regmap_write(dsi2->regmap, DSI2_INT_MASK_CRI, 0x1);
346 } else {
347 regmap_write(dsi2->regmap, DSI2_INT_MASK_PHY, 0x0);
348 regmap_write(dsi2->regmap, DSI2_INT_MASK_TO, 0x0);
349 regmap_write(dsi2->regmap, DSI2_INT_MASK_ACK, 0x0);
350 regmap_write(dsi2->regmap, DSI2_INT_MASK_IPI, 0x0);
351 regmap_write(dsi2->regmap, DSI2_INT_MASK_FIFO, 0x0);
352 regmap_write(dsi2->regmap, DSI2_INT_MASK_PRI, 0x0);
353 regmap_write(dsi2->regmap, DSI2_INT_MASK_CRI, 0x0);
354 };
355 }
356
mipi_dcphy_power_on(struct dw_mipi_dsi2 * dsi2)357 static void mipi_dcphy_power_on(struct dw_mipi_dsi2 *dsi2)
358 {
359 if (dsi2->phy_enabled)
360 return;
361
362 if (dsi2->dcphy)
363 phy_power_on(dsi2->dcphy);
364
365 dsi2->phy_enabled = true;
366 }
367
mipi_dcphy_power_off(struct dw_mipi_dsi2 * dsi2)368 static void mipi_dcphy_power_off(struct dw_mipi_dsi2 *dsi2)
369 {
370 if (!dsi2->phy_enabled)
371 return;
372
373 if (dsi2->dcphy)
374 phy_power_off(dsi2->dcphy);
375
376 dsi2->phy_enabled = false;
377 }
378
dw_mipi_dsi2_set_vid_mode(struct dw_mipi_dsi2 * dsi2)379 static void dw_mipi_dsi2_set_vid_mode(struct dw_mipi_dsi2 *dsi2)
380 {
381 u32 val = 0, mode;
382 int ret;
383
384 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HFP)
385 val |= BLK_HFP_HS_EN;
386
387 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HBP)
388 val |= BLK_HBP_HS_EN;
389
390 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HSA)
391 val |= BLK_HSA_HS_EN;
392
393 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
394 val |= VID_MODE_TYPE_BURST;
395 else if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
396 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
397 else
398 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
399
400 regmap_write(dsi2->regmap, DSI2_DSI_VID_TX_CFG, val);
401
402 regmap_write(dsi2->regmap, DSI2_MODE_CTRL, VIDEO_MODE);
403 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_MODE_STATUS,
404 mode, mode & VIDEO_MODE,
405 1000, MODE_STATUS_TIMEOUT_US);
406 if (ret < 0)
407 dev_err(dsi2->dev, "failed to enter video mode\n");
408 }
409
dw_mipi_dsi2_set_data_stream_mode(struct dw_mipi_dsi2 * dsi2)410 static void dw_mipi_dsi2_set_data_stream_mode(struct dw_mipi_dsi2 *dsi2)
411 {
412 u32 mode;
413 int ret;
414
415 regmap_write(dsi2->regmap, DSI2_MODE_CTRL, DATA_STREAM_MODE);
416 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_MODE_STATUS,
417 mode, mode & DATA_STREAM_MODE,
418 1000, MODE_STATUS_TIMEOUT_US);
419 if (ret < 0)
420 dev_err(dsi2->dev, "failed to enter data stream mode\n");
421 }
422
dw_mipi_dsi2_set_cmd_mode(struct dw_mipi_dsi2 * dsi2)423 static void dw_mipi_dsi2_set_cmd_mode(struct dw_mipi_dsi2 *dsi2)
424 {
425 u32 mode;
426 int ret;
427
428 regmap_write(dsi2->regmap, DSI2_MODE_CTRL, COMMAND_MODE);
429 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_MODE_STATUS,
430 mode, mode & COMMAND_MODE,
431 1000, MODE_STATUS_TIMEOUT_US);
432 if (ret < 0)
433 dev_err(dsi2->dev, "failed to enter data stream mode\n");
434 }
435
dw_mipi_dsi2_disable(struct dw_mipi_dsi2 * dsi2)436 static void dw_mipi_dsi2_disable(struct dw_mipi_dsi2 *dsi2)
437 {
438 regmap_write(dsi2->regmap, DSI2_IPI_PIX_PKT_CFG, 0);
439 dw_mipi_dsi2_set_cmd_mode(dsi2);
440
441 if (dsi2->slave)
442 dw_mipi_dsi2_disable(dsi2->slave);
443 }
444
dw_mipi_dsi2_post_disable(struct dw_mipi_dsi2 * dsi2)445 static void dw_mipi_dsi2_post_disable(struct dw_mipi_dsi2 *dsi2)
446 {
447 dw_mipi_dsi2_irq_enable(dsi2, 0);
448 regmap_write(dsi2->regmap, DSI2_PWR_UP, RESET);
449 mipi_dcphy_power_off(dsi2);
450 pm_runtime_put(dsi2->dev);
451
452 if (dsi2->slave)
453 dw_mipi_dsi2_post_disable(dsi2->slave);
454 }
455
dw_mipi_dsi2_encoder_atomic_disable(struct drm_encoder * encoder,struct drm_atomic_state * state)456 static void dw_mipi_dsi2_encoder_atomic_disable(struct drm_encoder *encoder,
457 struct drm_atomic_state *state)
458 {
459 struct dw_mipi_dsi2 *dsi2 = encoder_to_dsi2(encoder);
460 struct drm_crtc *crtc = encoder->crtc;
461 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
462
463 if (dsi2->panel)
464 drm_panel_disable(dsi2->panel);
465
466 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO))
467 rockchip_drm_crtc_standby(encoder->crtc, 1);
468
469 dw_mipi_dsi2_disable(dsi2);
470
471 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO))
472 rockchip_drm_crtc_standby(encoder->crtc, 0);
473
474 if (dsi2->panel)
475 drm_panel_unprepare(dsi2->panel);
476
477 dw_mipi_dsi2_post_disable(dsi2);
478
479 if (!crtc->state->active_changed)
480 return;
481
482 if (dsi2->slave)
483 s->output_if &= ~(VOP_OUTPUT_IF_MIPI1 | VOP_OUTPUT_IF_MIPI0);
484 else
485 s->output_if &= ~(dsi2->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0);
486 }
487
dw_mipi_dsi2_get_lane_rate(struct dw_mipi_dsi2 * dsi2)488 static void dw_mipi_dsi2_get_lane_rate(struct dw_mipi_dsi2 *dsi2)
489 {
490 struct device *dev = dsi2->dev;
491 const struct drm_display_mode *mode = &dsi2->mode;
492 u64 max_lane_rate;
493 u64 lane_rate, target_pclk;
494 u32 value;
495 int bpp, lanes;
496 u64 tmp;
497
498 max_lane_rate = (dsi2->c_option) ?
499 dsi2->pdata->cphy_max_symbol_rate_per_lane :
500 dsi2->pdata->dphy_max_bit_rate_per_lane;
501
502 lanes = (dsi2->slave || dsi2->master) ? dsi2->lanes * 2 : dsi2->lanes;
503 bpp = mipi_dsi_pixel_format_to_bpp(dsi2->format);
504 if (bpp < 0)
505 bpp = 24;
506
507 /*
508 * optional override of the desired bandwidth
509 * High-Speed mode: Differential and terminated: 80Mbps ~ 4500 Mbps.
510 */
511 if (!of_property_read_u32(dev->of_node, "rockchip,lane-rate", &value)) {
512 if (value >= 80000 && value <= 4500000)
513 lane_rate = value * MSEC_PER_SEC;
514 else if (value >= 80 && value <= 4500)
515 lane_rate = value * USEC_PER_SEC;
516 else
517 lane_rate = 80 * USEC_PER_SEC;
518 } else {
519 tmp = (u64)mode->crtc_clock * 1000 * bpp;
520 do_div(tmp, lanes);
521
522 /*
523 * Multiple bits are encoded into each symbol epoch,
524 * the data rate is ~2.28x the symbol rate.
525 */
526 if (dsi2->c_option)
527 tmp = DIV_ROUND_CLOSEST_ULL(tmp * 100, 228);
528
529 /* set BW a little larger only in video burst mode in
530 * consideration of the protocol overhead and HS mode
531 * switching to BLLP mode, take 1 / 0.9, since Mbps must
532 * big than bandwidth of RGB
533 */
534 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
535 tmp *= 10;
536 do_div(tmp, 9);
537 }
538
539 if (tmp > max_lane_rate)
540 lane_rate = max_lane_rate;
541 else
542 lane_rate = tmp;
543 }
544
545 target_pclk = DIV_ROUND_CLOSEST_ULL(lane_rate * lanes, bpp);
546 phy_mipi_dphy_get_default_config(target_pclk, bpp, lanes,
547 &dsi2->phy_opts.mipi_dphy);
548 if (dsi2->slave)
549 phy_mipi_dphy_get_default_config(target_pclk, bpp, lanes,
550 &dsi2->slave->phy_opts.mipi_dphy);
551 }
552
dw_mipi_dsi2_set_lane_rate(struct dw_mipi_dsi2 * dsi2)553 static void dw_mipi_dsi2_set_lane_rate(struct dw_mipi_dsi2 *dsi2)
554 {
555 unsigned long hs_clk_rate;
556
557 if (dsi2->dcphy)
558 if (!dsi2->c_option)
559 phy_set_mode(dsi2->dcphy, PHY_MODE_MIPI_DPHY);
560
561 phy_configure(dsi2->dcphy, &dsi2->phy_opts);
562 hs_clk_rate = dsi2->phy_opts.mipi_dphy.hs_clk_rate;
563 dsi2->lane_hs_rate = DIV_ROUND_UP(hs_clk_rate, MSEC_PER_SEC);
564 }
565
dw_mipi_dsi2_host_softrst(struct dw_mipi_dsi2 * dsi2)566 static void dw_mipi_dsi2_host_softrst(struct dw_mipi_dsi2 *dsi2)
567 {
568 if (dsi2->apb_rst) {
569 reset_control_assert(dsi2->apb_rst);
570 usleep_range(10, 20);
571 reset_control_deassert(dsi2->apb_rst);
572 }
573
574 regmap_write(dsi2->regmap, DSI2_SOFT_RESET, 0x0);
575 udelay(100);
576 regmap_write(dsi2->regmap, DSI2_SOFT_RESET,
577 SYS_RSTN | PHY_RSTN | IPI_RSTN);
578
579 }
580
dw_mipi_dsi2_phy_mode_cfg(struct dw_mipi_dsi2 * dsi2)581 static void dw_mipi_dsi2_phy_mode_cfg(struct dw_mipi_dsi2 *dsi2)
582 {
583 u32 val = 0;
584
585 /* PPI width is fixed to 16 bits in DCPHY */
586 val |= PPI_WIDTH(PPI_WIDTH_16_BITS) | PHY_LANES(dsi2->lanes);
587 val |= PHY_TYPE(dsi2->c_option ? CPHY : DPHY);
588 regmap_write(dsi2->regmap, DSI2_PHY_MODE_CFG, val);
589 }
590
dw_mipi_dsi2_phy_clk_mode_cfg(struct dw_mipi_dsi2 * dsi2)591 static void dw_mipi_dsi2_phy_clk_mode_cfg(struct dw_mipi_dsi2 *dsi2)
592 {
593 u32 sys_clk, esc_clk_div;
594 u32 val = 0;
595
596 /*
597 * clk_type should be NON_CONTINUOUS_CLK before
598 * initial deskew calibration be sent.
599 */
600 val |= NON_CONTINUOUS_CLK;
601
602 /* The maximum value of the escape clock frequency is 20MHz */
603 sys_clk = clk_get_rate(dsi2->sys_clk) / USEC_PER_SEC;
604 esc_clk_div = DIV_ROUND_UP(sys_clk, 20 * 2);
605 val |= PHY_LPTX_CLK_DIV(esc_clk_div);
606
607 regmap_write(dsi2->regmap, DSI2_PHY_CLK_CFG, val);
608 }
609
dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 * dsi2)610 static void dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 *dsi2)
611 {
612 struct drm_display_mode *mode = &dsi2->mode;
613 u64 sys_clk = clk_get_rate(dsi2->sys_clk);
614 u64 pixel_clk, ipi_clk, phy_hsclk;
615 u64 tmp;
616
617 /*
618 * in DPHY mode, the phy_hstx_clk is exactly 1/16 the Lane high-speed
619 * data rate; In CPHY mode, the phy_hstx_clk is exactly 1/7 the trio
620 * high speed symbol rate.
621 */
622 if (dsi2->c_option)
623 phy_hsclk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_hs_rate * MSEC_PER_SEC, 7);
624 else
625 phy_hsclk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_hs_rate * MSEC_PER_SEC, 16);
626
627 /* IPI_RATIO_MAN_CFG = PHY_HSTX_CLK / IPI_CLK */
628 pixel_clk = mode->crtc_clock * MSEC_PER_SEC;
629 ipi_clk = pixel_clk / 4;
630
631 tmp = DIV_ROUND_CLOSEST_ULL(phy_hsclk << 16, ipi_clk);
632 regmap_write(dsi2->regmap, DSI2_PHY_IPI_RATIO_MAN_CFG,
633 PHY_IPI_RATIO(tmp));
634
635 /*
636 * SYS_RATIO_MAN_CFG = MIPI_DCPHY_HSCLK_Freq / MIPI_DCPHY_HSCLK_Freq
637 */
638 tmp = DIV_ROUND_CLOSEST_ULL(phy_hsclk << 16, sys_clk);
639 regmap_write(dsi2->regmap, DSI2_PHY_SYS_RATIO_MAN_CFG,
640 PHY_SYS_RATIO(tmp));
641 }
642
dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(struct dw_mipi_dsi2 * dsi2)643 static void dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(struct dw_mipi_dsi2 *dsi2)
644 {
645 struct phy_configure_opts_mipi_dphy *cfg = &dsi2->phy_opts.mipi_dphy;
646 unsigned long long tmp, ui;
647 unsigned long long hstx_clk;
648
649 hstx_clk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_hs_rate * MSEC_PER_SEC, 16);
650
651 ui = ALIGN(PSEC_PER_SEC, hstx_clk);
652 do_div(ui, hstx_clk);
653
654 /* PHY_LP2HS_TIME = (TLPX + THS-PREPARE + THS-ZERO) / Tphy_hstx_clk */
655 tmp = cfg->lpx + cfg->hs_prepare + cfg->hs_zero;
656 tmp = DIV_ROUND_CLOSEST_ULL(tmp << 16, ui);
657 regmap_write(dsi2->regmap, DSI2_PHY_LP2HS_MAN_CFG, PHY_LP2HS_TIME(tmp));
658
659 /* PHY_HS2LP_TIME = (THS-TRAIL + THS-EXIT) / Tphy_hstx_clk */
660 tmp = cfg->hs_trail + cfg->hs_exit;
661 tmp = DIV_ROUND_CLOSEST_ULL(tmp << 16, ui);
662 regmap_write(dsi2->regmap, DSI2_PHY_HS2LP_MAN_CFG, PHY_HS2LP_TIME(tmp));
663 }
664
dw_mipi_dsi2_phy_init(struct dw_mipi_dsi2 * dsi2)665 static void dw_mipi_dsi2_phy_init(struct dw_mipi_dsi2 *dsi2)
666 {
667 dw_mipi_dsi2_phy_mode_cfg(dsi2);
668 dw_mipi_dsi2_phy_clk_mode_cfg(dsi2);
669 dw_mipi_dsi2_phy_ratio_cfg(dsi2);
670 dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(dsi2);
671
672 /* phy configuration 8 - 10 */
673 }
674
dw_mipi_dsi2_tx_option_set(struct dw_mipi_dsi2 * dsi2)675 static void dw_mipi_dsi2_tx_option_set(struct dw_mipi_dsi2 *dsi2)
676 {
677 u32 val;
678
679 val = BTA_EN | EOTP_TX_EN;
680
681 if (dsi2->mode_flags & MIPI_DSI_MODE_EOT_PACKET)
682 val &= ~EOTP_TX_EN;
683
684 regmap_write(dsi2->regmap, DSI2_DSI_GENERAL_CFG, val);
685 regmap_write(dsi2->regmap, DSI2_DSI_VCID_CFG, TX_VCID(dsi2->channel));
686
687 if (dsi2->scrambling_en)
688 regmap_write(dsi2->regmap, DSI2_DSI_SCRAMBLING_CFG,
689 SCRAMBLING_EN);
690 }
691
dw_mipi_dsi2_ipi_color_coding_cfg(struct dw_mipi_dsi2 * dsi2)692 static void dw_mipi_dsi2_ipi_color_coding_cfg(struct dw_mipi_dsi2 *dsi2)
693 {
694 u32 val, color_depth;
695
696 switch (dsi2->format) {
697 case MIPI_DSI_FMT_RGB666:
698 case MIPI_DSI_FMT_RGB666_PACKED:
699 color_depth = IPI_DEPTH_6_BITS;
700 break;
701 case MIPI_DSI_FMT_RGB565:
702 color_depth = IPI_DEPTH_5_6_5_BITS;
703 break;
704 case MIPI_DSI_FMT_RGB888:
705 default:
706 color_depth = IPI_DEPTH_8_BITS;
707 break;
708 }
709
710 val = IPI_DEPTH(color_depth) |
711 IPI_FORMAT(dsi2->dsc_enable ? IPI_FORMAT_DSC : IPI_FORMAT_RGB);
712 regmap_write(dsi2->regmap, DSI2_IPI_COLOR_MAN_CFG, val);
713 grf_field_write(dsi2, IPI_COLOR_DEPTH, color_depth);
714
715 if (dsi2->dsc_enable)
716 grf_field_write(dsi2, IPI_FORMAT, IPI_FORMAT_DSC);
717 }
718
dw_mipi_dsi2_ipi_set(struct dw_mipi_dsi2 * dsi2)719 static void dw_mipi_dsi2_ipi_set(struct dw_mipi_dsi2 *dsi2)
720 {
721 struct drm_display_mode *mode = &dsi2->mode;
722 u32 hline, hsa, hbp, hact;
723 u64 hline_time, hsa_time, hbp_time, hact_time, tmp;
724 u64 pixel_clk, phy_hs_clk;
725 u32 vact, vsa, vfp, vbp;
726 u16 val;
727
728 if (dsi2->slave || dsi2->master)
729 val = mode->hdisplay / 2;
730 else
731 val = mode->hdisplay;
732
733 regmap_write(dsi2->regmap, DSI2_IPI_PIX_PKT_CFG, MAX_PIX_PKT(val));
734
735 dw_mipi_dsi2_ipi_color_coding_cfg(dsi2);
736
737 /*
738 * if the controller is intended to operate in data stream mode,
739 * no more steps are required.
740 */
741 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO))
742 return;
743
744 vact = mode->vdisplay;
745 vsa = mode->vsync_end - mode->vsync_start;
746 vfp = mode->vsync_start - mode->vdisplay;
747 vbp = mode->vtotal - mode->vsync_end;
748 hact = mode->hdisplay;
749 hsa = mode->hsync_end - mode->hsync_start;
750 hbp = mode->htotal - mode->hsync_end;
751 hline = mode->htotal;
752
753 pixel_clk = mode->crtc_clock * MSEC_PER_SEC;
754
755 if (dsi2->c_option)
756 phy_hs_clk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_hs_rate * MSEC_PER_SEC, 7);
757 else
758 phy_hs_clk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_hs_rate * MSEC_PER_SEC, 16);
759
760 tmp = hsa * phy_hs_clk;
761 hsa_time = DIV_ROUND_CLOSEST_ULL(tmp << 16, pixel_clk);
762 regmap_write(dsi2->regmap, DSI2_IPI_VID_HSA_MAN_CFG,
763 VID_HSA_TIME(hsa_time));
764
765 tmp = hbp * phy_hs_clk;
766 hbp_time = DIV_ROUND_CLOSEST_ULL(tmp << 16, pixel_clk);
767 regmap_write(dsi2->regmap, DSI2_IPI_VID_HBP_MAN_CFG,
768 VID_HBP_TIME(hbp_time));
769
770 tmp = hact * phy_hs_clk;
771 hact_time = DIV_ROUND_CLOSEST_ULL(tmp << 16, pixel_clk);
772 regmap_write(dsi2->regmap, DSI2_IPI_VID_HACT_MAN_CFG,
773 VID_HACT_TIME(hact_time));
774
775 tmp = hline * phy_hs_clk;
776 hline_time = DIV_ROUND_CLOSEST_ULL(tmp << 16, pixel_clk);
777 regmap_write(dsi2->regmap, DSI2_IPI_VID_HLINE_MAN_CFG,
778 VID_HLINE_TIME(hline_time));
779
780 regmap_write(dsi2->regmap, DSI2_IPI_VID_VSA_MAN_CFG,
781 VID_VSA_LINES(vsa));
782 regmap_write(dsi2->regmap, DSI2_IPI_VID_VBP_MAN_CFG,
783 VID_VBP_LINES(vbp));
784 regmap_write(dsi2->regmap, DSI2_IPI_VID_VACT_MAN_CFG,
785 VID_VACT_LINES(vact));
786 regmap_write(dsi2->regmap, DSI2_IPI_VID_VFP_MAN_CFG,
787 VID_VFP_LINES(vfp));
788 }
789
790 static void
dw_mipi_dsi2_work_mode(struct dw_mipi_dsi2 * dsi2,u32 mode)791 dw_mipi_dsi2_work_mode(struct dw_mipi_dsi2 *dsi2, u32 mode)
792 {
793 /*
794 * select controller work in Manual mode
795 * Manual: MANUAL_MODE_EN
796 * Automatic: 0
797 */
798 regmap_write(dsi2->regmap, MANUAL_MODE_CFG, mode);
799 }
800
dw_mipi_dsi2_pre_enable(struct dw_mipi_dsi2 * dsi2)801 static void dw_mipi_dsi2_pre_enable(struct dw_mipi_dsi2 *dsi2)
802 {
803 pm_runtime_get_sync(dsi2->dev);
804
805 dw_mipi_dsi2_host_softrst(dsi2);
806 regmap_write(dsi2->regmap, DSI2_PWR_UP, RESET);
807
808 /* there may be some timeout registers may be configured if desired */
809
810 dw_mipi_dsi2_work_mode(dsi2, MANUAL_MODE_EN);
811 dw_mipi_dsi2_phy_init(dsi2);
812 dw_mipi_dsi2_tx_option_set(dsi2);
813 dw_mipi_dsi2_irq_enable(dsi2, 1);
814 mipi_dcphy_power_on(dsi2);
815
816 /*
817 * initial deskew calibration is send after phy_power_on,
818 * then we can configure clk_type.
819 */
820 if (!(dsi2->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
821 regmap_update_bits(dsi2->regmap, DSI2_PHY_CLK_CFG,
822 CLK_TYPE_MASK, CONTIUOUS_CLK);
823
824 regmap_write(dsi2->regmap, DSI2_PWR_UP, POWER_UP);
825 dw_mipi_dsi2_set_cmd_mode(dsi2);
826
827 if (dsi2->slave)
828 dw_mipi_dsi2_pre_enable(dsi2->slave);
829 }
830
dw_mipi_dsi2_enable(struct dw_mipi_dsi2 * dsi2)831 static void dw_mipi_dsi2_enable(struct dw_mipi_dsi2 *dsi2)
832 {
833 dw_mipi_dsi2_ipi_set(dsi2);
834
835 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)
836 dw_mipi_dsi2_set_vid_mode(dsi2);
837 else
838 dw_mipi_dsi2_set_data_stream_mode(dsi2);
839
840 if (dsi2->slave)
841 dw_mipi_dsi2_enable(dsi2->slave);
842 }
843
dw_mipi_dsi2_encoder_mode_set(struct dw_mipi_dsi2 * dsi2,struct drm_atomic_state * state)844 static int dw_mipi_dsi2_encoder_mode_set(struct dw_mipi_dsi2 *dsi2,
845 struct drm_atomic_state *state)
846 {
847 struct drm_encoder *encoder = &dsi2->encoder;
848 struct drm_connector *connector;
849 struct drm_connector_state *conn_state;
850 struct drm_crtc_state *crtc_state;
851 const struct drm_display_mode *adjusted_mode;
852 struct drm_display_mode *mode = &dsi2->mode;
853
854 connector = drm_atomic_get_new_connector_for_encoder(state, encoder);
855 if (!connector)
856 return -ENODEV;
857
858 conn_state = drm_atomic_get_new_connector_state(state, connector);
859 if (!conn_state)
860 return -ENODEV;
861
862 crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
863 if (!crtc_state) {
864 dev_err(dsi2->dev, "failed to get crtc state\n");
865 return -ENODEV;
866 }
867
868 adjusted_mode = &crtc_state->adjusted_mode;
869 drm_mode_copy(mode, adjusted_mode);
870
871 if (dsi2->dual_connector_split)
872 drm_mode_convert_to_origin_mode(mode);
873
874 if (dsi2->slave)
875 drm_mode_copy(&dsi2->slave->mode, mode);
876
877 return 0;
878 }
879
dw_mipi_dsi2_encoder_atomic_enable(struct drm_encoder * encoder,struct drm_atomic_state * state)880 static void dw_mipi_dsi2_encoder_atomic_enable(struct drm_encoder *encoder,
881 struct drm_atomic_state *state)
882 {
883 struct dw_mipi_dsi2 *dsi2 = encoder_to_dsi2(encoder);
884 int ret;
885
886 ret = dw_mipi_dsi2_encoder_mode_set(dsi2, state);
887 if (ret) {
888 dev_err(dsi2->dev, "failed to set dsi2 mode\n");
889 return;
890 }
891
892 dw_mipi_dsi2_get_lane_rate(dsi2);
893
894 if (dsi2->dcphy)
895 dw_mipi_dsi2_set_lane_rate(dsi2);
896
897 if (dsi2->slave && dsi2->slave->dcphy)
898 dw_mipi_dsi2_set_lane_rate(dsi2->slave);
899
900 dw_mipi_dsi2_pre_enable(dsi2);
901
902 if (dsi2->panel)
903 drm_panel_prepare(dsi2->panel);
904
905 dw_mipi_dsi2_enable(dsi2);
906
907 if (dsi2->panel)
908 drm_panel_enable(dsi2->panel);
909
910 DRM_DEV_INFO(dsi2->dev, "final DSI-Link bandwidth: %u x %d %s\n",
911 dsi2->lane_hs_rate,
912 dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes,
913 dsi2->c_option ? "Ksps" : "Kbps");
914 }
915
916 static int
dw_mipi_dsi2_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)917 dw_mipi_dsi2_encoder_atomic_check(struct drm_encoder *encoder,
918 struct drm_crtc_state *crtc_state,
919 struct drm_connector_state *conn_state)
920 {
921
922 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
923 struct dw_mipi_dsi2 *dsi2 = encoder_to_dsi2(encoder);
924 struct drm_connector *connector = conn_state->connector;
925 struct drm_display_info *info = &connector->display_info;
926
927 switch (dsi2->format) {
928 case MIPI_DSI_FMT_RGB888:
929 s->output_mode = ROCKCHIP_OUT_MODE_P888;
930 break;
931 case MIPI_DSI_FMT_RGB666:
932 s->output_mode = ROCKCHIP_OUT_MODE_P666;
933 break;
934 case MIPI_DSI_FMT_RGB565:
935 s->output_mode = ROCKCHIP_OUT_MODE_P565;
936 break;
937 default:
938 WARN_ON(1);
939 return -EINVAL;
940 }
941
942 if (info->num_bus_formats)
943 s->bus_format = info->bus_formats[0];
944 else
945 s->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
946
947 s->output_type = DRM_MODE_CONNECTOR_DSI;
948 s->output_if |= dsi2->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0;
949 s->bus_flags = info->bus_flags;
950
951 s->tv_state = &conn_state->tv;
952 s->color_space = V4L2_COLORSPACE_DEFAULT;
953
954 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) {
955 s->output_flags |= ROCKCHIP_OUTPUT_MIPI_DS_MODE;
956 s->soft_te = dsi2->te_gpio ? true : false;
957 s->hold_mode = true;
958 }
959
960 if (dsi2->slave) {
961 s->output_flags |= ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE;
962 if (dsi2->data_swap)
963 s->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP;
964
965 s->output_if |= VOP_OUTPUT_IF_MIPI1;
966 }
967
968 if (dsi2->dual_connector_split) {
969 s->output_flags |= ROCKCHIP_OUTPUT_DUAL_CONNECTOR_SPLIT_MODE;
970
971 if (dsi2->left_display)
972 s->output_if_left_panel |= dsi2->id ?
973 VOP_OUTPUT_IF_MIPI1 :
974 VOP_OUTPUT_IF_MIPI0;
975 }
976
977 if (dsi2->dsc_enable) {
978 s->dsc_enable = 1;
979 s->dsc_sink_cap.version_major = dsi2->version_major;
980 s->dsc_sink_cap.version_minor = dsi2->version_minor;
981 s->dsc_sink_cap.slice_width = dsi2->slice_width;
982 s->dsc_sink_cap.slice_height = dsi2->slice_height;
983 /* only can support rgb888 panel now */
984 s->dsc_sink_cap.target_bits_per_pixel_x16 = 8 << 4;
985 s->dsc_sink_cap.native_420 = 0;
986
987 memcpy(&s->pps, dsi2->pps, sizeof(struct drm_dsc_picture_parameter_set));
988 }
989
990 return 0;
991 }
992
dw_mipi_dsi2_loader_protect(struct dw_mipi_dsi2 * dsi2,bool on)993 static void dw_mipi_dsi2_loader_protect(struct dw_mipi_dsi2 *dsi2, bool on)
994 {
995 if (on) {
996 pm_runtime_get_sync(dsi2->dev);
997 phy_init(dsi2->dcphy);
998 dsi2->phy_enabled = true;
999 if (dsi2->dcphy)
1000 dsi2->dcphy->power_count++;
1001 } else {
1002 pm_runtime_put(dsi2->dev);
1003 phy_exit(dsi2->dcphy);
1004 dsi2->phy_enabled = false;
1005 if (dsi2->dcphy)
1006 dsi2->dcphy->power_count--;
1007 }
1008
1009 if (dsi2->slave)
1010 dw_mipi_dsi2_loader_protect(dsi2->slave, on);
1011 }
1012
dw_mipi_dsi2_encoder_loader_protect(struct drm_encoder * encoder,bool on)1013 static int dw_mipi_dsi2_encoder_loader_protect(struct drm_encoder *encoder,
1014 bool on)
1015 {
1016 struct dw_mipi_dsi2 *dsi2 = encoder_to_dsi2(encoder);
1017
1018 if (dsi2->panel)
1019 panel_simple_loader_protect(dsi2->panel);
1020
1021 dw_mipi_dsi2_loader_protect(dsi2, on);
1022
1023 return 0;
1024 }
1025
1026 static const struct drm_encoder_helper_funcs
1027 dw_mipi_dsi2_encoder_helper_funcs = {
1028 .atomic_enable = dw_mipi_dsi2_encoder_atomic_enable,
1029 .atomic_disable = dw_mipi_dsi2_encoder_atomic_disable,
1030 .atomic_check = dw_mipi_dsi2_encoder_atomic_check,
1031 };
1032
dw_mipi_dsi2_connector_get_modes(struct drm_connector * connector)1033 static int dw_mipi_dsi2_connector_get_modes(struct drm_connector *connector)
1034 {
1035 struct dw_mipi_dsi2 *dsi2 = con_to_dsi2(connector);
1036
1037 if (dsi2->bridge && (dsi2->bridge->ops & DRM_BRIDGE_OP_MODES))
1038 return drm_bridge_get_modes(dsi2->bridge, connector);
1039
1040 if (dsi2->panel)
1041 return drm_panel_get_modes(dsi2->panel, connector);
1042
1043 return -EINVAL;
1044 }
1045
1046 static enum drm_mode_status
dw_mipi_dsi2_connector_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)1047 dw_mipi_dsi2_connector_mode_valid(struct drm_connector *connector,
1048 struct drm_display_mode *mode)
1049 {
1050 struct dw_mipi_dsi2 *dsi2 = con_to_dsi2(connector);
1051 struct videomode vm;
1052 u8 min_pixels = dsi2->slave ? 8 : 4;
1053
1054 drm_display_mode_to_videomode(mode, &vm);
1055
1056 if (vm.vactive > 16383)
1057 return MODE_VIRTUAL_Y;
1058
1059 if (vm.vsync_len > 1023)
1060 return MODE_VSYNC_WIDE;
1061
1062 if (vm.vback_porch > 1023 || vm.vfront_porch > 1023)
1063 return MODE_VBLANK_WIDE;
1064
1065 /*
1066 * the minimum region size (HSA,HBP,HACT,HFP) is 4 pixels
1067 * which is the ip known issues and limitations.
1068 */
1069 if (!(vm.hsync_len < min_pixels || vm.hback_porch < min_pixels ||
1070 vm.hfront_porch < min_pixels || vm.hactive < min_pixels))
1071 return MODE_OK;
1072
1073 if (vm.hsync_len < min_pixels)
1074 vm.hsync_len = min_pixels;
1075
1076 if (vm.hback_porch < min_pixels)
1077 vm.hback_porch = min_pixels;
1078
1079 if (vm.hfront_porch < min_pixels)
1080 vm.hfront_porch = min_pixels;
1081
1082 if (vm.hactive < min_pixels)
1083 vm.hactive = min_pixels;
1084
1085 drm_display_mode_from_videomode(&vm, mode);
1086
1087 return MODE_OK;
1088 }
1089
1090 static struct drm_connector_helper_funcs dw_mipi_dsi2_connector_helper_funcs = {
1091 .get_modes = dw_mipi_dsi2_connector_get_modes,
1092 .mode_valid = dw_mipi_dsi2_connector_mode_valid,
1093 };
1094
1095 static enum drm_connector_status
dw_mipi_dsi2_connector_detect(struct drm_connector * connector,bool force)1096 dw_mipi_dsi2_connector_detect(struct drm_connector *connector, bool force)
1097 {
1098 struct dw_mipi_dsi2 *dsi2 = con_to_dsi2(connector);
1099
1100 if (dsi2->bridge && (dsi2->bridge->ops & DRM_BRIDGE_OP_DETECT))
1101 return drm_bridge_detect(dsi2->bridge);
1102
1103 return connector_status_connected;
1104 }
1105
dw_mipi_dsi2_drm_connector_destroy(struct drm_connector * connector)1106 static void dw_mipi_dsi2_drm_connector_destroy(struct drm_connector *connector)
1107 {
1108 drm_connector_unregister(connector);
1109 drm_connector_cleanup(connector);
1110 }
1111
1112 static int
dw_mipi_dsi2_atomic_connector_get_property(struct drm_connector * connector,const struct drm_connector_state * state,struct drm_property * property,uint64_t * val)1113 dw_mipi_dsi2_atomic_connector_get_property(struct drm_connector *connector,
1114 const struct drm_connector_state *state,
1115 struct drm_property *property,
1116 uint64_t *val)
1117 {
1118 struct rockchip_drm_private *private = connector->dev->dev_private;
1119 struct dw_mipi_dsi2 *dsi2 = con_to_dsi2(connector);
1120
1121 if (property == private->split_area_prop) {
1122 switch (dsi2->split_area) {
1123 case 1:
1124 *val = ROCKCHIP_DRM_SPLIT_LEFT_SIDE;
1125 break;
1126 case 2:
1127 *val = ROCKCHIP_DRM_SPLIT_RIGHT_SIDE;
1128 break;
1129 default:
1130 *val = ROCKCHIP_DRM_SPLIT_UNSET;
1131 break;
1132 }
1133 }
1134
1135 return 0;
1136 }
1137
1138 static const struct drm_connector_funcs dw_mipi_dsi2_atomic_connector_funcs = {
1139 .fill_modes = drm_helper_probe_single_connector_modes,
1140 .detect = dw_mipi_dsi2_connector_detect,
1141 .destroy = dw_mipi_dsi2_drm_connector_destroy,
1142 .reset = drm_atomic_helper_connector_reset,
1143 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1144 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1145 .atomic_get_property = dw_mipi_dsi2_atomic_connector_get_property,
1146 };
1147
dw_mipi_dsi2_dual_channel_probe(struct dw_mipi_dsi2 * dsi2)1148 static int dw_mipi_dsi2_dual_channel_probe(struct dw_mipi_dsi2 *dsi2)
1149 {
1150 struct device_node *np;
1151 struct platform_device *secondary;
1152
1153 np = of_parse_phandle(dsi2->dev->of_node, "rockchip,dual-channel", 0);
1154 if (np) {
1155 dsi2->data_swap = of_property_read_bool(dsi2->dev->of_node,
1156 "rockchip,data-swap");
1157 secondary = of_find_device_by_node(np);
1158 dsi2->slave = platform_get_drvdata(secondary);
1159 of_node_put(np);
1160
1161 if (!dsi2->slave)
1162 return -EPROBE_DEFER;
1163
1164 dsi2->slave->master = dsi2;
1165 dsi2->lanes /= 2;
1166
1167 dsi2->slave->lanes = dsi2->lanes;
1168 dsi2->slave->channel = dsi2->channel;
1169 dsi2->slave->format = dsi2->format;
1170 dsi2->slave->mode_flags = dsi2->mode_flags;
1171 }
1172
1173 return 0;
1174 }
1175
dw_mipi_dsi2_te_irq_handler(int irq,void * dev_id)1176 static irqreturn_t dw_mipi_dsi2_te_irq_handler(int irq, void *dev_id)
1177 {
1178 struct dw_mipi_dsi2 *dsi2 = (struct dw_mipi_dsi2 *)dev_id;
1179 struct drm_encoder *encoder = &dsi2->encoder;
1180
1181 if (encoder->crtc)
1182 rockchip_drm_te_handle(encoder->crtc);
1183
1184 return IRQ_HANDLED;
1185 }
1186
dw_mipi_dsi2_get_dsc_params_from_sink(struct dw_mipi_dsi2 * dsi2,struct drm_panel * panel,struct drm_bridge * bridge)1187 static int dw_mipi_dsi2_get_dsc_params_from_sink(struct dw_mipi_dsi2 *dsi2,
1188 struct drm_panel *panel,
1189 struct drm_bridge *bridge)
1190 {
1191 struct drm_dsc_picture_parameter_set *pps = NULL;
1192 struct device_node *np = NULL;
1193 struct cmd_header *header;
1194 const void *data;
1195 char *d;
1196 uint8_t *dsc_packed_pps;
1197 int len;
1198
1199 if (!panel && !bridge)
1200 return -ENODEV;
1201
1202 if (panel)
1203 np = panel->dev->of_node;
1204 else
1205 np = bridge->of_node;
1206
1207 dsi2->c_option = of_property_read_bool(np, "phy-c-option");
1208 dsi2->scrambling_en = of_property_read_bool(np, "scrambling-enable");
1209 dsi2->dsc_enable = of_property_read_bool(np, "compressed-data");
1210
1211 if (dsi2->slave) {
1212 dsi2->slave->c_option = dsi2->c_option;
1213 dsi2->slave->scrambling_en = dsi2->scrambling_en;
1214 dsi2->slave->dsc_enable = dsi2->dsc_enable;
1215 }
1216
1217 of_property_read_u32(np, "slice-width", &dsi2->slice_width);
1218 of_property_read_u32(np, "slice-height", &dsi2->slice_height);
1219 of_property_read_u8(np, "version-major", &dsi2->version_major);
1220 of_property_read_u8(np, "version-minor", &dsi2->version_minor);
1221
1222 data = of_get_property(np, "panel-init-sequence", &len);
1223 if (!data)
1224 return -EINVAL;
1225
1226 d = devm_kmemdup(dsi2->dev, data, len, GFP_KERNEL);
1227 if (!d)
1228 return -ENOMEM;
1229
1230 while (len > sizeof(*header)) {
1231 header = (struct cmd_header *)d;
1232 d += sizeof(*header);
1233 len -= sizeof(*header);
1234
1235 if (header->payload_length > len)
1236 return -EINVAL;
1237
1238 if (header->cmd_type == MIPI_DSI_PICTURE_PARAMETER_SET) {
1239 dsc_packed_pps = devm_kmemdup(dsi2->dev, d,
1240 header->payload_length, GFP_KERNEL);
1241 if (!dsc_packed_pps)
1242 return -ENOMEM;
1243
1244 pps = (struct drm_dsc_picture_parameter_set *)dsc_packed_pps;
1245 break;
1246 }
1247
1248 d += header->payload_length;
1249 len -= header->payload_length;
1250 }
1251
1252 dsi2->pps = pps;
1253
1254 return 0;
1255 }
1256
dw_mipi_dsi2_connector_init(struct dw_mipi_dsi2 * dsi2)1257 static int dw_mipi_dsi2_connector_init(struct dw_mipi_dsi2 *dsi2)
1258 {
1259 struct drm_encoder *encoder = &dsi2->encoder;
1260 struct drm_connector *connector = &dsi2->connector;
1261 struct drm_device *drm_dev = dsi2->drm_dev;
1262 struct device *dev = dsi2->dev;
1263 int ret;
1264
1265 ret = drm_connector_init(drm_dev, connector,
1266 &dw_mipi_dsi2_atomic_connector_funcs,
1267 DRM_MODE_CONNECTOR_DSI);
1268 if (ret) {
1269 DRM_DEV_ERROR(dev, "Failed to initialize connector\n");
1270 return ret;
1271 }
1272
1273 drm_connector_helper_add(connector,
1274 &dw_mipi_dsi2_connector_helper_funcs);
1275 ret = drm_connector_attach_encoder(connector, encoder);
1276 if (ret < 0) {
1277 DRM_DEV_ERROR(dev, "Failed to attach encoder: %d\n", ret);
1278 goto connector_cleanup;
1279 }
1280
1281 return 0;
1282
1283 connector_cleanup:
1284 connector->funcs->destroy(connector);
1285
1286 return ret;
1287 }
1288
dw_mipi_dsi2_register_sub_dev(struct dw_mipi_dsi2 * dsi2,struct drm_connector * connector)1289 static int dw_mipi_dsi2_register_sub_dev(struct dw_mipi_dsi2 *dsi2,
1290 struct drm_connector *connector)
1291 {
1292 struct rockchip_drm_private *private;
1293 struct device *dev = dsi2->dev;
1294
1295 private = connector->dev->dev_private;
1296
1297 if (dsi2->split_area)
1298 drm_object_attach_property(&connector->base,
1299 private->split_area_prop,
1300 dsi2->split_area);
1301
1302 dsi2->sub_dev.connector = connector;
1303 dsi2->sub_dev.of_node = dev->of_node;
1304 dsi2->sub_dev.loader_protect = dw_mipi_dsi2_encoder_loader_protect;
1305 rockchip_drm_register_sub_dev(&dsi2->sub_dev);
1306
1307 return 0;
1308 }
1309
dw_mipi_dsi2_bind(struct device * dev,struct device * master,void * data)1310 static int dw_mipi_dsi2_bind(struct device *dev, struct device *master,
1311 void *data)
1312 {
1313 struct dw_mipi_dsi2 *dsi2 = dev_get_drvdata(dev);
1314 struct drm_device *drm_dev = data;
1315 struct drm_encoder *encoder = &dsi2->encoder;
1316 struct device_node *of_node = dsi2->dev->of_node;
1317 struct drm_connector *connector = NULL;
1318 enum drm_bridge_attach_flags flags;
1319 int ret;
1320
1321 dsi2->drm_dev = drm_dev;
1322 ret = dw_mipi_dsi2_dual_channel_probe(dsi2);
1323 if (ret)
1324 return ret;
1325
1326 if (dsi2->master)
1327 return 0;
1328
1329 ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1,
1330 &dsi2->panel, &dsi2->bridge);
1331 if (ret) {
1332 DRM_DEV_ERROR(dev, "Failed to find panel or bridge: %d\n", ret);
1333 return ret;
1334 }
1335
1336 dw_mipi_dsi2_get_dsc_params_from_sink(dsi2, dsi2->panel, dsi2->bridge);
1337 encoder->possible_crtcs = rockchip_drm_of_find_possible_crtcs(drm_dev,
1338 of_node);
1339
1340 ret = drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_DSI);
1341 if (ret) {
1342 DRM_ERROR("Failed to initialize encoder with drm\n");
1343 return ret;
1344 }
1345
1346 drm_encoder_helper_add(encoder, &dw_mipi_dsi2_encoder_helper_funcs);
1347
1348 if (dsi2->bridge) {
1349 struct list_head *connector_list =
1350 &drm_dev->mode_config.connector_list;
1351
1352 dsi2->bridge->driver_private = &dsi2->host;
1353 dsi2->bridge->encoder = encoder;
1354
1355 flags = dsi2->bridge->ops & DRM_BRIDGE_OP_MODES ?
1356 DRM_BRIDGE_ATTACH_NO_CONNECTOR : 0;
1357 ret = drm_bridge_attach(encoder, dsi2->bridge, NULL, flags);
1358 if (ret) {
1359 DRM_DEV_ERROR(dev,
1360 "Failed to attach bridge: %d\n", ret);
1361 goto encoder_cleanup;
1362 }
1363
1364 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
1365 list_for_each_entry(connector, connector_list, head)
1366 if (drm_connector_has_possible_encoder(connector,
1367 encoder))
1368 break;
1369 }
1370
1371 if (dsi2->panel || (dsi2->bridge && (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))) {
1372 ret = dw_mipi_dsi2_connector_init(dsi2);
1373 if (ret)
1374 goto encoder_cleanup;
1375
1376 connector = &dsi2->connector;
1377 }
1378
1379 if (connector) {
1380 ret = dw_mipi_dsi2_register_sub_dev(dsi2, connector);
1381 if (ret)
1382 goto encoder_cleanup;
1383 }
1384
1385 pm_runtime_enable(dsi2->dev);
1386 if (dsi2->slave)
1387 pm_runtime_enable(dsi2->slave->dev);
1388
1389 return 0;
1390
1391 encoder_cleanup:
1392 encoder->funcs->destroy(encoder);
1393
1394 return ret;
1395 }
1396
dw_mipi_dsi2_unbind(struct device * dev,struct device * master,void * data)1397 static void dw_mipi_dsi2_unbind(struct device *dev, struct device *master,
1398 void *data)
1399 {
1400 struct dw_mipi_dsi2 *dsi2 = dev_get_drvdata(dev);
1401
1402 if (dsi2->sub_dev.connector) {
1403 rockchip_drm_unregister_sub_dev(&dsi2->sub_dev);
1404
1405 if (dsi2->connector.funcs)
1406 dsi2->connector.funcs->destroy(&dsi2->connector);
1407 }
1408
1409 pm_runtime_disable(dsi2->dev);
1410 if (dsi2->slave)
1411 pm_runtime_disable(dsi2->slave->dev);
1412
1413 dsi2->encoder.funcs->destroy(&dsi2->encoder);
1414 }
1415
1416 static const struct component_ops dw_mipi_dsi2_ops = {
1417 .bind = dw_mipi_dsi2_bind,
1418 .unbind = dw_mipi_dsi2_unbind,
1419 };
1420
1421 struct dsi2_irq_data {
1422 u32 offeset;
1423 char *irq_src;
1424 };
1425
1426 static const struct dsi2_irq_data dw_mipi_dsi2_irq_data[] = {
1427 {DSI2_INT_ST_PHY, "int_st_phy"},
1428 {DSI2_INT_ST_TO, "int_st_to"},
1429 {DSI2_INT_ST_ACK, "int_st_ack"},
1430 {DSI2_INT_ST_IPI, "int_st_ipi"},
1431 {DSI2_INT_ST_FIFO, "int_st_fifo"},
1432 {DSI2_INT_ST_PRI, "int_st_pri"},
1433 {DSI2_INT_ST_CRI, "int_st_cri"},
1434 };
1435
dw_mipi_dsi2_irq_handler(int irq,void * dev_id)1436 static irqreturn_t dw_mipi_dsi2_irq_handler(int irq, void *dev_id)
1437 {
1438
1439 struct dw_mipi_dsi2 *dsi2 = dev_id;
1440 u32 int_st;
1441 unsigned int i;
1442
1443 regmap_read(dsi2->regmap, INT_ST_MAIN, &int_st);
1444
1445 for (i = 0; i < ARRAY_SIZE(dw_mipi_dsi2_irq_data); i++)
1446 if (int_st & BIT(i))
1447 DRM_DEV_DEBUG(dsi2->dev, "%s\n",
1448 dw_mipi_dsi2_irq_data[i].irq_src);
1449
1450 return IRQ_HANDLED;
1451 }
1452
1453 static const struct regmap_config dw_mipi_dsi2_regmap_config = {
1454 .name = "host",
1455 .reg_bits = 32,
1456 .val_bits = 32,
1457 .reg_stride = 4,
1458 .fast_io = true,
1459 .max_register = DSI2_MAX_REGISGER,
1460 };
1461
dw_mipi_dsi2_host_attach(struct mipi_dsi_host * host,struct mipi_dsi_device * device)1462 static int dw_mipi_dsi2_host_attach(struct mipi_dsi_host *host,
1463 struct mipi_dsi_device *device)
1464 {
1465 struct dw_mipi_dsi2 *dsi2 = host_to_dsi2(host);
1466
1467 if (dsi2->master)
1468 return 0;
1469
1470 if (device->lanes < 1 || device->lanes > 8)
1471 return -EINVAL;
1472
1473 dsi2->client = device->dev.of_node;
1474 dsi2->lanes = device->lanes;
1475 dsi2->channel = device->channel;
1476 dsi2->format = device->format;
1477 dsi2->mode_flags = device->mode_flags;
1478
1479 return 0;
1480 }
1481
dw_mipi_dsi2_host_detach(struct mipi_dsi_host * host,struct mipi_dsi_device * device)1482 static int dw_mipi_dsi2_host_detach(struct mipi_dsi_host *host,
1483 struct mipi_dsi_device *device)
1484 {
1485 return 0;
1486 }
1487
dw_mipi_dsi2_read_from_fifo(struct dw_mipi_dsi2 * dsi2,const struct mipi_dsi_msg * msg)1488 static int dw_mipi_dsi2_read_from_fifo(struct dw_mipi_dsi2 *dsi2,
1489 const struct mipi_dsi_msg *msg)
1490 {
1491 u8 *payload = msg->rx_buf;
1492 u8 data_type;
1493 u16 wc;
1494 int i, j, ret, len = msg->rx_len;
1495 unsigned int vrefresh = drm_mode_vrefresh(&dsi2->mode);
1496 u32 val;
1497
1498 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_CORE_STATUS,
1499 val, val & CRI_RD_DATA_AVAIL,
1500 0, DIV_ROUND_UP(1000000, vrefresh));
1501 if (ret) {
1502 DRM_DEV_ERROR(dsi2->dev, "CRI has no available read data\n");
1503 return ret;
1504 }
1505
1506 regmap_read(dsi2->regmap, DSI2_CRI_RX_HDR, &val);
1507 data_type = val & 0x3f;
1508
1509 if (mipi_dsi_packet_format_is_short(data_type)) {
1510 for (i = 0; i < len && i < 2; i++)
1511 payload[i] = (val >> (8 * (i + 1))) & 0xff;
1512
1513 return 0;
1514 }
1515
1516 wc = (val >> 8) & 0xffff;
1517 /* Receive payload */
1518 for (i = 0; i < len && i < wc; i += 4) {
1519 regmap_read(dsi2->regmap, DSI2_CRI_RX_PLD, &val);
1520 for (j = 0; j < 4 && j + i < len && j + i < wc; j++)
1521 payload[i + j] = val >> (8 * j);
1522 }
1523
1524 return 0;
1525 }
1526
dw_mipi_dsi2_transfer(struct dw_mipi_dsi2 * dsi2,const struct mipi_dsi_msg * msg)1527 static ssize_t dw_mipi_dsi2_transfer(struct dw_mipi_dsi2 *dsi2,
1528 const struct mipi_dsi_msg *msg)
1529 {
1530 struct mipi_dsi_packet packet;
1531 int ret;
1532 u32 val;
1533 u32 mode;
1534
1535 regmap_update_bits(dsi2->regmap, DSI2_DSI_VID_TX_CFG,
1536 LPDT_DISPLAY_CMD_EN,
1537 msg->flags & MIPI_DSI_MSG_USE_LPM ?
1538 LPDT_DISPLAY_CMD_EN : 0);
1539
1540 /* create a packet to the DSI protocol */
1541 ret = mipi_dsi_create_packet(&packet, msg);
1542 if (ret) {
1543 DRM_DEV_ERROR(dsi2->dev, "failed to create packet: %d\n", ret);
1544 return ret;
1545 }
1546
1547 ret = cri_fifos_wait_avail(dsi2);
1548 if (ret)
1549 return ret;
1550
1551 /* Send payload */
1552 while (DIV_ROUND_UP(packet.payload_length, 4)) {
1553 /* check cri interface is not busy */
1554 if (packet.payload_length < 4) {
1555 /* send residu payload */
1556 val = 0;
1557 memcpy(&val, packet.payload, packet.payload_length);
1558 regmap_write(dsi2->regmap, DSI2_CRI_TX_PLD, val);
1559 packet.payload_length = 0;
1560 } else {
1561 val = get_unaligned_le32(packet.payload);
1562 regmap_write(dsi2->regmap, DSI2_CRI_TX_PLD, val);
1563 packet.payload += 4;
1564 packet.payload_length -= 4;
1565 }
1566 }
1567
1568 /* Send packet header */
1569 mode = CMD_TX_MODE(msg->flags & MIPI_DSI_MSG_USE_LPM ? 1 : 0);
1570 val = get_unaligned_le32(packet.header);
1571
1572 regmap_write(dsi2->regmap, DSI2_CRI_TX_HDR, mode | val);
1573
1574 ret = cri_fifos_wait_avail(dsi2);
1575 if (ret)
1576 return ret;
1577
1578 if (msg->rx_len) {
1579 ret = dw_mipi_dsi2_read_from_fifo(dsi2, msg);
1580 if (ret < 0)
1581 return ret;
1582 }
1583
1584 if (dsi2->slave)
1585 dw_mipi_dsi2_transfer(dsi2->slave, msg);
1586
1587 return msg->tx_len;
1588 }
1589
dw_mipi_dsi2_host_transfer(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)1590 static ssize_t dw_mipi_dsi2_host_transfer(struct mipi_dsi_host *host,
1591 const struct mipi_dsi_msg *msg)
1592 {
1593 struct dw_mipi_dsi2 *dsi2 = host_to_dsi2(host);
1594
1595 return dw_mipi_dsi2_transfer(dsi2, msg);
1596 }
1597
1598 static const struct mipi_dsi_host_ops dw_mipi_dsi2_host_ops = {
1599 .attach = dw_mipi_dsi2_host_attach,
1600 .detach = dw_mipi_dsi2_host_detach,
1601 .transfer = dw_mipi_dsi2_host_transfer,
1602 };
1603
dw_mipi_dsi2_probe(struct platform_device * pdev)1604 static int dw_mipi_dsi2_probe(struct platform_device *pdev)
1605 {
1606 struct device *dev = &pdev->dev;
1607 struct dw_mipi_dsi2 *dsi2;
1608 struct resource *res;
1609 void __iomem *regs;
1610 int id;
1611 int ret;
1612
1613 dsi2 = devm_kzalloc(dev, sizeof(*dsi2), GFP_KERNEL);
1614 if (!dsi2)
1615 return -ENOMEM;
1616
1617 id = of_alias_get_id(dev->of_node, "dsi");
1618 if (id < 0)
1619 id = 0;
1620
1621 dsi2->dev = dev;
1622 dsi2->id = id;
1623 dsi2->pdata = of_device_get_match_data(dev);
1624 platform_set_drvdata(pdev, dsi2);
1625
1626 if (device_property_read_bool(dev, "dual-connector-split")) {
1627 dsi2->dual_connector_split = true;
1628
1629 if (device_property_read_bool(dev, "left-display"))
1630 dsi2->left_display = true;
1631 }
1632
1633 if (device_property_read_u32(dev, "split-area", &dsi2->split_area))
1634 dsi2->split_area = 0;
1635
1636 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1637 regs = devm_ioremap_resource(dev, res);
1638 if (IS_ERR(regs))
1639 return PTR_ERR(regs);
1640
1641 dsi2->irq = platform_get_irq(pdev, 0);
1642 if (dsi2->irq < 0)
1643 return dsi2->irq;
1644
1645 dsi2->pclk = devm_clk_get(dev, "pclk");
1646 if (IS_ERR(dsi2->pclk)) {
1647 ret = PTR_ERR(dsi2->pclk);
1648 DRM_DEV_ERROR(dev, "Unable to get pclk: %d\n", ret);
1649 return ret;
1650 }
1651
1652 dsi2->sys_clk = devm_clk_get(dev, "sys_clk");
1653 if (IS_ERR(dsi2->sys_clk)) {
1654 ret = PTR_ERR(dsi2->sys_clk);
1655 DRM_DEV_ERROR(dev, "Unable to get sys_clk: %d\n", ret);
1656 return ret;
1657 }
1658
1659 dsi2->regmap = devm_regmap_init_mmio(dev, regs,
1660 &dw_mipi_dsi2_regmap_config);
1661 if (IS_ERR(dsi2->regmap)) {
1662 ret = PTR_ERR(dsi2->regmap);
1663 DRM_DEV_ERROR(dev, "failed to init register map: %d\n", ret);
1664 return ret;
1665 }
1666
1667 dsi2->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
1668 "rockchip,grf");
1669 if (IS_ERR(dsi2->grf)) {
1670 ret = PTR_ERR(dsi2->grf);
1671 DRM_DEV_ERROR(dsi2->dev, "Unable to get grf: %d\n", ret);
1672 return ret;
1673 }
1674
1675 dsi2->apb_rst = devm_reset_control_get(dev, "apb");
1676 if (IS_ERR(dsi2->apb_rst)) {
1677 ret = PTR_ERR(dsi2->apb_rst);
1678 DRM_DEV_ERROR(dev,
1679 "Unable to get reset control: %d\n", ret);
1680 return ret;
1681 }
1682
1683 dsi2->dcphy = devm_phy_optional_get(dev, "dcphy");
1684 if (IS_ERR(dsi2->dcphy)) {
1685 ret = PTR_ERR(dsi2->dcphy);
1686 DRM_DEV_ERROR(dev, "failed to get mipi dcphy: %d\n", ret);
1687 return ret;
1688 }
1689
1690 dsi2->te_gpio = devm_gpiod_get_optional(dsi2->dev, "te", GPIOD_IN);
1691 if (IS_ERR(dsi2->te_gpio))
1692 dsi2->te_gpio = NULL;
1693
1694 if (dsi2->te_gpio) {
1695 ret = devm_request_threaded_irq(dsi2->dev, gpiod_to_irq(dsi2->te_gpio),
1696 dw_mipi_dsi2_te_irq_handler, NULL,
1697 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1698 "PANEL-TE", dsi2);
1699 if (ret) {
1700 dev_err(dsi2->dev, "failed to request TE IRQ: %d\n", ret);
1701 return ret;
1702 }
1703 }
1704
1705 ret = devm_request_irq(dev, dsi2->irq, dw_mipi_dsi2_irq_handler,
1706 IRQF_SHARED, dev_name(dev), dsi2);
1707 if (ret) {
1708 DRM_DEV_ERROR(dev, "failed to request irq: %d\n", ret);
1709 return ret;
1710 }
1711
1712 dsi2->host.ops = &dw_mipi_dsi2_host_ops;
1713 dsi2->host.dev = dev;
1714 ret = mipi_dsi_host_register(&dsi2->host);
1715 if (ret) {
1716 DRM_DEV_ERROR(dev, "Failed to register MIPI host: %d\n", ret);
1717 return ret;
1718 }
1719
1720 return component_add(&pdev->dev, &dw_mipi_dsi2_ops);
1721 }
1722
dw_mipi_dsi2_remove(struct platform_device * pdev)1723 static int dw_mipi_dsi2_remove(struct platform_device *pdev)
1724 {
1725 return 0;
1726 }
1727
dw_mipi_dsi2_runtime_suspend(struct device * dev)1728 static __maybe_unused int dw_mipi_dsi2_runtime_suspend(struct device *dev)
1729 {
1730 struct dw_mipi_dsi2 *dsi2 = dev_get_drvdata(dev);
1731
1732 clk_disable_unprepare(dsi2->pclk);
1733 clk_disable_unprepare(dsi2->sys_clk);
1734
1735 return 0;
1736 }
1737
dw_mipi_dsi2_runtime_resume(struct device * dev)1738 static __maybe_unused int dw_mipi_dsi2_runtime_resume(struct device *dev)
1739 {
1740 struct dw_mipi_dsi2 *dsi2 = dev_get_drvdata(dev);
1741
1742 clk_prepare_enable(dsi2->pclk);
1743 clk_prepare_enable(dsi2->sys_clk);
1744
1745 return 0;
1746 }
1747
1748 static const struct dev_pm_ops dw_mipi_dsi2_rockchip_pm_ops = {
1749 SET_RUNTIME_PM_OPS(dw_mipi_dsi2_runtime_suspend,
1750 dw_mipi_dsi2_runtime_resume, NULL)
1751 };
1752
1753 static const u32 rk3588_dsi0_grf_reg_fields[MAX_FIELDS] = {
1754 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0000, 11, 11),
1755 [GATING_EN] = GRF_REG_FIELD(0x0000, 10, 10),
1756 [IPI_SHUTDN] = GRF_REG_FIELD(0x0000, 9, 9),
1757 [IPI_COLORM] = GRF_REG_FIELD(0x0000, 8, 8),
1758 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0000, 4, 7),
1759 [IPI_FORMAT] = GRF_REG_FIELD(0x0000, 0, 3),
1760 };
1761
1762 static const u32 rk3588_dsi1_grf_reg_fields[MAX_FIELDS] = {
1763 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0004, 11, 11),
1764 [GATING_EN] = GRF_REG_FIELD(0x0004, 10, 10),
1765 [IPI_SHUTDN] = GRF_REG_FIELD(0x0004, 9, 9),
1766 [IPI_COLORM] = GRF_REG_FIELD(0x0004, 8, 8),
1767 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0004, 4, 7),
1768 [IPI_FORMAT] = GRF_REG_FIELD(0x0004, 0, 3),
1769 };
1770
1771 static const struct dw_mipi_dsi2_plat_data rk3588_mipi_dsi2_plat_data = {
1772 .dsi0_grf_reg_fields = rk3588_dsi0_grf_reg_fields,
1773 .dsi1_grf_reg_fields = rk3588_dsi1_grf_reg_fields,
1774 .dphy_max_bit_rate_per_lane = 4500000000ULL,
1775 .cphy_max_symbol_rate_per_lane = 2000000000ULL,
1776 };
1777
1778 static const struct of_device_id dw_mipi_dsi2_dt_ids[] = {
1779 {
1780 .compatible = "rockchip,rk3588-mipi-dsi2",
1781 .data = &rk3588_mipi_dsi2_plat_data,
1782 },
1783 {}
1784 };
1785 MODULE_DEVICE_TABLE(of, dw_mipi_dsi2_dt_ids);
1786
1787 struct platform_driver dw_mipi_dsi2_rockchip_driver = {
1788 .probe = dw_mipi_dsi2_probe,
1789 .remove = dw_mipi_dsi2_remove,
1790 .driver = {
1791 .of_match_table = dw_mipi_dsi2_dt_ids,
1792 .pm = &dw_mipi_dsi2_rockchip_pm_ops,
1793 .name = "dw-mipi-dsi2",
1794 },
1795 };
1796