1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * rcar_lvds_regs.h -- R-Car LVDS Interface Registers Definitions 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013-2015 Renesas Electronics Corporation 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __RCAR_LVDS_REGS_H__ 11*4882a593Smuzhiyun #define __RCAR_LVDS_REGS_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define LVDCR0 0x0000 14*4882a593Smuzhiyun #define LVDCR0_DUSEL (1 << 15) 15*4882a593Smuzhiyun #define LVDCR0_DMD (1 << 12) /* Gen2 only */ 16*4882a593Smuzhiyun #define LVDCR0_LVMD_MASK (0xf << 8) 17*4882a593Smuzhiyun #define LVDCR0_LVMD_SHIFT 8 18*4882a593Smuzhiyun #define LVDCR0_PLLON (1 << 4) 19*4882a593Smuzhiyun #define LVDCR0_PWD (1 << 2) /* Gen3 only */ 20*4882a593Smuzhiyun #define LVDCR0_BEN (1 << 2) /* Gen2 only */ 21*4882a593Smuzhiyun #define LVDCR0_LVEN (1 << 1) 22*4882a593Smuzhiyun #define LVDCR0_LVRES (1 << 0) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define LVDCR1 0x0004 25*4882a593Smuzhiyun #define LVDCR1_CKSEL (1 << 15) /* Gen2 only */ 26*4882a593Smuzhiyun #define LVDCR1_CHSTBY(n) (3 << (2 + (n) * 2)) 27*4882a593Smuzhiyun #define LVDCR1_CLKSTBY (3 << 0) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define LVDPLLCR 0x0008 30*4882a593Smuzhiyun /* Gen2 & V3M */ 31*4882a593Smuzhiyun #define LVDPLLCR_CEEN (1 << 14) 32*4882a593Smuzhiyun #define LVDPLLCR_FBEN (1 << 13) 33*4882a593Smuzhiyun #define LVDPLLCR_COSEL (1 << 12) 34*4882a593Smuzhiyun #define LVDPLLCR_PLLDLYCNT_150M (0x1bf << 0) 35*4882a593Smuzhiyun #define LVDPLLCR_PLLDLYCNT_121M (0x22c << 0) 36*4882a593Smuzhiyun #define LVDPLLCR_PLLDLYCNT_60M (0x77b << 0) 37*4882a593Smuzhiyun #define LVDPLLCR_PLLDLYCNT_38M (0x69a << 0) 38*4882a593Smuzhiyun #define LVDPLLCR_PLLDLYCNT_MASK (0x7ff << 0) 39*4882a593Smuzhiyun /* Gen3 but V3M,D3 and E3 */ 40*4882a593Smuzhiyun #define LVDPLLCR_PLLDIVCNT_42M (0x014cb << 0) 41*4882a593Smuzhiyun #define LVDPLLCR_PLLDIVCNT_85M (0x00a45 << 0) 42*4882a593Smuzhiyun #define LVDPLLCR_PLLDIVCNT_128M (0x006c3 << 0) 43*4882a593Smuzhiyun #define LVDPLLCR_PLLDIVCNT_148M (0x046c1 << 0) 44*4882a593Smuzhiyun #define LVDPLLCR_PLLDIVCNT_MASK (0x7ffff << 0) 45*4882a593Smuzhiyun /* D3 and E3 */ 46*4882a593Smuzhiyun #define LVDPLLCR_PLLON (1 << 22) 47*4882a593Smuzhiyun #define LVDPLLCR_PLLSEL_PLL0 (0 << 20) 48*4882a593Smuzhiyun #define LVDPLLCR_PLLSEL_LVX (1 << 20) 49*4882a593Smuzhiyun #define LVDPLLCR_PLLSEL_PLL1 (2 << 20) 50*4882a593Smuzhiyun #define LVDPLLCR_CKSEL_LVX (1 << 17) 51*4882a593Smuzhiyun #define LVDPLLCR_CKSEL_EXTAL (3 << 17) 52*4882a593Smuzhiyun #define LVDPLLCR_CKSEL_DU_DOTCLKIN(n) ((5 + (n) * 2) << 17) 53*4882a593Smuzhiyun #define LVDPLLCR_OCKSEL (1 << 16) 54*4882a593Smuzhiyun #define LVDPLLCR_STP_CLKOUTE (1 << 14) 55*4882a593Smuzhiyun #define LVDPLLCR_OUTCLKSEL (1 << 12) 56*4882a593Smuzhiyun #define LVDPLLCR_CLKOUT (1 << 11) 57*4882a593Smuzhiyun #define LVDPLLCR_PLLE(n) ((n) << 10) 58*4882a593Smuzhiyun #define LVDPLLCR_PLLN(n) ((n) << 3) 59*4882a593Smuzhiyun #define LVDPLLCR_PLLM(n) ((n) << 0) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define LVDCTRCR 0x000c 62*4882a593Smuzhiyun #define LVDCTRCR_CTR3SEL_ZERO (0 << 12) 63*4882a593Smuzhiyun #define LVDCTRCR_CTR3SEL_ODD (1 << 12) 64*4882a593Smuzhiyun #define LVDCTRCR_CTR3SEL_CDE (2 << 12) 65*4882a593Smuzhiyun #define LVDCTRCR_CTR3SEL_MASK (7 << 12) 66*4882a593Smuzhiyun #define LVDCTRCR_CTR2SEL_DISP (0 << 8) 67*4882a593Smuzhiyun #define LVDCTRCR_CTR2SEL_ODD (1 << 8) 68*4882a593Smuzhiyun #define LVDCTRCR_CTR2SEL_CDE (2 << 8) 69*4882a593Smuzhiyun #define LVDCTRCR_CTR2SEL_HSYNC (3 << 8) 70*4882a593Smuzhiyun #define LVDCTRCR_CTR2SEL_VSYNC (4 << 8) 71*4882a593Smuzhiyun #define LVDCTRCR_CTR2SEL_MASK (7 << 8) 72*4882a593Smuzhiyun #define LVDCTRCR_CTR1SEL_VSYNC (0 << 4) 73*4882a593Smuzhiyun #define LVDCTRCR_CTR1SEL_DISP (1 << 4) 74*4882a593Smuzhiyun #define LVDCTRCR_CTR1SEL_ODD (2 << 4) 75*4882a593Smuzhiyun #define LVDCTRCR_CTR1SEL_CDE (3 << 4) 76*4882a593Smuzhiyun #define LVDCTRCR_CTR1SEL_HSYNC (4 << 4) 77*4882a593Smuzhiyun #define LVDCTRCR_CTR1SEL_MASK (7 << 4) 78*4882a593Smuzhiyun #define LVDCTRCR_CTR0SEL_HSYNC (0 << 0) 79*4882a593Smuzhiyun #define LVDCTRCR_CTR0SEL_VSYNC (1 << 0) 80*4882a593Smuzhiyun #define LVDCTRCR_CTR0SEL_DISP (2 << 0) 81*4882a593Smuzhiyun #define LVDCTRCR_CTR0SEL_ODD (3 << 0) 82*4882a593Smuzhiyun #define LVDCTRCR_CTR0SEL_CDE (4 << 0) 83*4882a593Smuzhiyun #define LVDCTRCR_CTR0SEL_MASK (7 << 0) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define LVDCHCR 0x0010 86*4882a593Smuzhiyun #define LVDCHCR_CHSEL_CH(n, c) ((((c) - (n)) & 3) << ((n) * 4)) 87*4882a593Smuzhiyun #define LVDCHCR_CHSEL_MASK(n) (3 << ((n) * 4)) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* All registers below are specific to D3 and E3 */ 90*4882a593Smuzhiyun #define LVDSTRIPE 0x0014 91*4882a593Smuzhiyun #define LVDSTRIPE_ST_TRGSEL_DISP (0 << 2) 92*4882a593Smuzhiyun #define LVDSTRIPE_ST_TRGSEL_HSYNC_R (1 << 2) 93*4882a593Smuzhiyun #define LVDSTRIPE_ST_TRGSEL_HSYNC_F (2 << 2) 94*4882a593Smuzhiyun #define LVDSTRIPE_ST_SWAP (1 << 1) 95*4882a593Smuzhiyun #define LVDSTRIPE_ST_ON (1 << 0) 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define LVDSCR 0x0018 98*4882a593Smuzhiyun #define LVDSCR_DEPTH(n) (((n) - 1) << 29) 99*4882a593Smuzhiyun #define LVDSCR_BANDSET (1 << 28) 100*4882a593Smuzhiyun #define LVDSCR_TWGCNT(n) ((((n) - 256) / 16) << 24) 101*4882a593Smuzhiyun #define LVDSCR_SDIV(n) ((n) << 22) 102*4882a593Smuzhiyun #define LVDSCR_MODE (1 << 21) 103*4882a593Smuzhiyun #define LVDSCR_RSTN (1 << 20) 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #define LVDDIV 0x001c 106*4882a593Smuzhiyun #define LVDDIV_DIVSEL (1 << 8) 107*4882a593Smuzhiyun #define LVDDIV_DIVRESET (1 << 7) 108*4882a593Smuzhiyun #define LVDDIV_DIVSTP (1 << 6) 109*4882a593Smuzhiyun #define LVDDIV_DIV(n) ((n) << 0) 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #endif /* __RCAR_LVDS_REGS_H__ */ 112