1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * R-Car Gen3 HDMI PHY
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2016 Renesas Electronics Corporation
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/platform_device.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <drm/bridge/dw_hdmi.h>
15*4882a593Smuzhiyun #include <drm/drm_modes.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define RCAR_HDMI_PHY_OPMODE_PLLCFG 0x06 /* Mode of operation and PLL dividers */
18*4882a593Smuzhiyun #define RCAR_HDMI_PHY_PLLCURRGMPCTRL 0x10 /* PLL current and Gmp (conductance) */
19*4882a593Smuzhiyun #define RCAR_HDMI_PHY_PLLDIVCTRL 0x11 /* PLL dividers */
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun struct rcar_hdmi_phy_params {
22*4882a593Smuzhiyun unsigned long mpixelclock;
23*4882a593Smuzhiyun u16 opmode_div; /* Mode of operation and PLL dividers */
24*4882a593Smuzhiyun u16 curr_gmp; /* PLL current and Gmp (conductance) */
25*4882a593Smuzhiyun u16 div; /* PLL dividers */
26*4882a593Smuzhiyun };
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun static const struct rcar_hdmi_phy_params rcar_hdmi_phy_params[] = {
29*4882a593Smuzhiyun { 35500000, 0x0003, 0x0344, 0x0328 },
30*4882a593Smuzhiyun { 44900000, 0x0003, 0x0285, 0x0128 },
31*4882a593Smuzhiyun { 71000000, 0x0002, 0x1184, 0x0314 },
32*4882a593Smuzhiyun { 90000000, 0x0002, 0x1144, 0x0114 },
33*4882a593Smuzhiyun { 140250000, 0x0001, 0x20c4, 0x030a },
34*4882a593Smuzhiyun { 182750000, 0x0001, 0x2084, 0x010a },
35*4882a593Smuzhiyun { 281250000, 0x0000, 0x0084, 0x0305 },
36*4882a593Smuzhiyun { 297000000, 0x0000, 0x0084, 0x0105 },
37*4882a593Smuzhiyun { ~0UL, 0x0000, 0x0000, 0x0000 },
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun static enum drm_mode_status
rcar_hdmi_mode_valid(struct dw_hdmi * hdmi,void * data,const struct drm_display_info * info,const struct drm_display_mode * mode)41*4882a593Smuzhiyun rcar_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data,
42*4882a593Smuzhiyun const struct drm_display_info *info,
43*4882a593Smuzhiyun const struct drm_display_mode *mode)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun /*
46*4882a593Smuzhiyun * The maximum supported clock frequency is 297 MHz, as shown in the PHY
47*4882a593Smuzhiyun * parameters table.
48*4882a593Smuzhiyun */
49*4882a593Smuzhiyun if (mode->clock > 297000)
50*4882a593Smuzhiyun return MODE_CLOCK_HIGH;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun return MODE_OK;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
rcar_hdmi_phy_configure(struct dw_hdmi * hdmi,void * data,unsigned long mpixelclock)55*4882a593Smuzhiyun static int rcar_hdmi_phy_configure(struct dw_hdmi *hdmi, void *data,
56*4882a593Smuzhiyun unsigned long mpixelclock)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun const struct rcar_hdmi_phy_params *params = rcar_hdmi_phy_params;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun for (; params->mpixelclock != ~0UL; ++params) {
61*4882a593Smuzhiyun if (mpixelclock <= params->mpixelclock)
62*4882a593Smuzhiyun break;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun if (params->mpixelclock == ~0UL)
66*4882a593Smuzhiyun return -EINVAL;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun dw_hdmi_phy_i2c_write(hdmi, params->opmode_div,
69*4882a593Smuzhiyun RCAR_HDMI_PHY_OPMODE_PLLCFG);
70*4882a593Smuzhiyun dw_hdmi_phy_i2c_write(hdmi, params->curr_gmp,
71*4882a593Smuzhiyun RCAR_HDMI_PHY_PLLCURRGMPCTRL);
72*4882a593Smuzhiyun dw_hdmi_phy_i2c_write(hdmi, params->div, RCAR_HDMI_PHY_PLLDIVCTRL);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun return 0;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun static const struct dw_hdmi_plat_data rcar_dw_hdmi_plat_data = {
78*4882a593Smuzhiyun .mode_valid = rcar_hdmi_mode_valid,
79*4882a593Smuzhiyun .configure_phy = rcar_hdmi_phy_configure,
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun
rcar_dw_hdmi_probe(struct platform_device * pdev)82*4882a593Smuzhiyun static int rcar_dw_hdmi_probe(struct platform_device *pdev)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun struct dw_hdmi *hdmi;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun hdmi = dw_hdmi_probe(pdev, &rcar_dw_hdmi_plat_data);
87*4882a593Smuzhiyun if (IS_ERR(hdmi))
88*4882a593Smuzhiyun return PTR_ERR(hdmi);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun platform_set_drvdata(pdev, hdmi);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun return 0;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
rcar_dw_hdmi_remove(struct platform_device * pdev)95*4882a593Smuzhiyun static int rcar_dw_hdmi_remove(struct platform_device *pdev)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun struct dw_hdmi *hdmi = platform_get_drvdata(pdev);
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun dw_hdmi_remove(hdmi);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun return 0;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun static const struct of_device_id rcar_dw_hdmi_of_table[] = {
105*4882a593Smuzhiyun { .compatible = "renesas,rcar-gen3-hdmi" },
106*4882a593Smuzhiyun { /* Sentinel */ },
107*4882a593Smuzhiyun };
108*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, rcar_dw_hdmi_of_table);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun static struct platform_driver rcar_dw_hdmi_platform_driver = {
111*4882a593Smuzhiyun .probe = rcar_dw_hdmi_probe,
112*4882a593Smuzhiyun .remove = rcar_dw_hdmi_remove,
113*4882a593Smuzhiyun .driver = {
114*4882a593Smuzhiyun .name = "rcar-dw-hdmi",
115*4882a593Smuzhiyun .of_match_table = rcar_dw_hdmi_of_table,
116*4882a593Smuzhiyun },
117*4882a593Smuzhiyun };
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun module_platform_driver(rcar_dw_hdmi_platform_driver);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
122*4882a593Smuzhiyun MODULE_DESCRIPTION("Renesas R-Car Gen3 HDMI Encoder Driver");
123*4882a593Smuzhiyun MODULE_LICENSE("GPL");
124