1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * rcar_du_drv.h -- R-Car Display Unit DRM driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2013-2015 Renesas Electronics Corporation
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #ifndef __RCAR_DU_DRV_H__
11*4882a593Smuzhiyun #define __RCAR_DU_DRV_H__
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun #include <linux/wait.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include "rcar_cmm.h"
17*4882a593Smuzhiyun #include "rcar_du_crtc.h"
18*4882a593Smuzhiyun #include "rcar_du_group.h"
19*4882a593Smuzhiyun #include "rcar_du_vsp.h"
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun struct clk;
22*4882a593Smuzhiyun struct device;
23*4882a593Smuzhiyun struct drm_bridge;
24*4882a593Smuzhiyun struct drm_device;
25*4882a593Smuzhiyun struct drm_property;
26*4882a593Smuzhiyun struct rcar_du_device;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define RCAR_DU_FEATURE_CRTC_IRQ_CLOCK BIT(0) /* Per-CRTC IRQ and clock */
29*4882a593Smuzhiyun #define RCAR_DU_FEATURE_VSP1_SOURCE BIT(1) /* Has inputs from VSP1 */
30*4882a593Smuzhiyun #define RCAR_DU_FEATURE_INTERLACED BIT(2) /* HW supports interlaced */
31*4882a593Smuzhiyun #define RCAR_DU_FEATURE_TVM_SYNC BIT(3) /* Has TV switch/sync modes */
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #define RCAR_DU_QUIRK_ALIGN_128B BIT(0) /* Align pitches to 128 bytes */
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /*
36*4882a593Smuzhiyun * struct rcar_du_output_routing - Output routing specification
37*4882a593Smuzhiyun * @possible_crtcs: bitmask of possible CRTCs for the output
38*4882a593Smuzhiyun * @port: device tree port number corresponding to this output route
39*4882a593Smuzhiyun *
40*4882a593Smuzhiyun * The DU has 5 possible outputs (DPAD0/1, LVDS0/1, TCON). Output routing data
41*4882a593Smuzhiyun * specify the valid SoC outputs, which CRTCs can drive the output, and the type
42*4882a593Smuzhiyun * of in-SoC encoder for the output.
43*4882a593Smuzhiyun */
44*4882a593Smuzhiyun struct rcar_du_output_routing {
45*4882a593Smuzhiyun unsigned int possible_crtcs;
46*4882a593Smuzhiyun unsigned int port;
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /*
50*4882a593Smuzhiyun * struct rcar_du_device_info - DU model-specific information
51*4882a593Smuzhiyun * @gen: device generation (2 or 3)
52*4882a593Smuzhiyun * @features: device features (RCAR_DU_FEATURE_*)
53*4882a593Smuzhiyun * @quirks: device quirks (RCAR_DU_QUIRK_*)
54*4882a593Smuzhiyun * @channels_mask: bit mask of available DU channels
55*4882a593Smuzhiyun * @routes: array of CRTC to output routes, indexed by output (RCAR_DU_OUTPUT_*)
56*4882a593Smuzhiyun * @num_lvds: number of internal LVDS encoders
57*4882a593Smuzhiyun * @dpll_mask: bit mask of DU channels equipped with a DPLL
58*4882a593Smuzhiyun * @lvds_clk_mask: bitmask of channels that can use the LVDS clock as dot clock
59*4882a593Smuzhiyun */
60*4882a593Smuzhiyun struct rcar_du_device_info {
61*4882a593Smuzhiyun unsigned int gen;
62*4882a593Smuzhiyun unsigned int features;
63*4882a593Smuzhiyun unsigned int quirks;
64*4882a593Smuzhiyun unsigned int channels_mask;
65*4882a593Smuzhiyun struct rcar_du_output_routing routes[RCAR_DU_OUTPUT_MAX];
66*4882a593Smuzhiyun unsigned int num_lvds;
67*4882a593Smuzhiyun unsigned int dpll_mask;
68*4882a593Smuzhiyun unsigned int lvds_clk_mask;
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun #define RCAR_DU_MAX_CRTCS 4
72*4882a593Smuzhiyun #define RCAR_DU_MAX_GROUPS DIV_ROUND_UP(RCAR_DU_MAX_CRTCS, 2)
73*4882a593Smuzhiyun #define RCAR_DU_MAX_VSPS 4
74*4882a593Smuzhiyun #define RCAR_DU_MAX_LVDS 2
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun struct rcar_du_device {
77*4882a593Smuzhiyun struct device *dev;
78*4882a593Smuzhiyun const struct rcar_du_device_info *info;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun void __iomem *mmio;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun struct drm_device *ddev;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun struct rcar_du_crtc crtcs[RCAR_DU_MAX_CRTCS];
85*4882a593Smuzhiyun unsigned int num_crtcs;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun struct rcar_du_group groups[RCAR_DU_MAX_GROUPS];
88*4882a593Smuzhiyun struct platform_device *cmms[RCAR_DU_MAX_CRTCS];
89*4882a593Smuzhiyun struct rcar_du_vsp vsps[RCAR_DU_MAX_VSPS];
90*4882a593Smuzhiyun struct drm_bridge *lvds[RCAR_DU_MAX_LVDS];
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun struct {
93*4882a593Smuzhiyun struct drm_property *colorkey;
94*4882a593Smuzhiyun } props;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun unsigned int dpad0_source;
97*4882a593Smuzhiyun unsigned int dpad1_source;
98*4882a593Smuzhiyun unsigned int vspd1_sink;
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun
rcar_du_has(struct rcar_du_device * rcdu,unsigned int feature)101*4882a593Smuzhiyun static inline bool rcar_du_has(struct rcar_du_device *rcdu,
102*4882a593Smuzhiyun unsigned int feature)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun return rcdu->info->features & feature;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
rcar_du_needs(struct rcar_du_device * rcdu,unsigned int quirk)107*4882a593Smuzhiyun static inline bool rcar_du_needs(struct rcar_du_device *rcdu,
108*4882a593Smuzhiyun unsigned int quirk)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun return rcdu->info->quirks & quirk;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
rcar_du_read(struct rcar_du_device * rcdu,u32 reg)113*4882a593Smuzhiyun static inline u32 rcar_du_read(struct rcar_du_device *rcdu, u32 reg)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun return ioread32(rcdu->mmio + reg);
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
rcar_du_write(struct rcar_du_device * rcdu,u32 reg,u32 data)118*4882a593Smuzhiyun static inline void rcar_du_write(struct rcar_du_device *rcdu, u32 reg, u32 data)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun iowrite32(data, rcdu->mmio + reg);
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun #endif /* __RCAR_DU_DRV_H__ */
124