1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * rcar_du_crtc.h -- R-Car Display Unit CRTCs 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013-2015 Renesas Electronics Corporation 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __RCAR_DU_CRTC_H__ 11*4882a593Smuzhiyun #define __RCAR_DU_CRTC_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <linux/mutex.h> 14*4882a593Smuzhiyun #include <linux/spinlock.h> 15*4882a593Smuzhiyun #include <linux/wait.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include <drm/drm_crtc.h> 18*4882a593Smuzhiyun #include <drm/drm_writeback.h> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #include <media/vsp1.h> 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun struct rcar_du_group; 23*4882a593Smuzhiyun struct rcar_du_vsp; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /** 26*4882a593Smuzhiyun * struct rcar_du_crtc - the CRTC, representing a DU superposition processor 27*4882a593Smuzhiyun * @crtc: base DRM CRTC 28*4882a593Smuzhiyun * @dev: the DU device 29*4882a593Smuzhiyun * @clock: the CRTC functional clock 30*4882a593Smuzhiyun * @extclock: external pixel dot clock (optional) 31*4882a593Smuzhiyun * @mmio_offset: offset of the CRTC registers in the DU MMIO block 32*4882a593Smuzhiyun * @index: CRTC hardware index 33*4882a593Smuzhiyun * @initialized: whether the CRTC has been initialized and clocks enabled 34*4882a593Smuzhiyun * @dsysr: cached value of the DSYSR register 35*4882a593Smuzhiyun * @vblank_enable: whether vblank events are enabled on this CRTC 36*4882a593Smuzhiyun * @event: event to post when the pending page flip completes 37*4882a593Smuzhiyun * @flip_wait: wait queue used to signal page flip completion 38*4882a593Smuzhiyun * @vblank_lock: protects vblank_wait and vblank_count 39*4882a593Smuzhiyun * @vblank_wait: wait queue used to signal vertical blanking 40*4882a593Smuzhiyun * @vblank_count: number of vertical blanking interrupts to wait for 41*4882a593Smuzhiyun * @group: CRTC group this CRTC belongs to 42*4882a593Smuzhiyun * @cmm: CMM associated with this CRTC 43*4882a593Smuzhiyun * @vsp: VSP feeding video to this CRTC 44*4882a593Smuzhiyun * @vsp_pipe: index of the VSP pipeline feeding video to this CRTC 45*4882a593Smuzhiyun * @writeback: the writeback connector 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun struct rcar_du_crtc { 48*4882a593Smuzhiyun struct drm_crtc crtc; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun struct rcar_du_device *dev; 51*4882a593Smuzhiyun struct clk *clock; 52*4882a593Smuzhiyun struct clk *extclock; 53*4882a593Smuzhiyun unsigned int mmio_offset; 54*4882a593Smuzhiyun unsigned int index; 55*4882a593Smuzhiyun bool initialized; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun u32 dsysr; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun bool vblank_enable; 60*4882a593Smuzhiyun struct drm_pending_vblank_event *event; 61*4882a593Smuzhiyun wait_queue_head_t flip_wait; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun spinlock_t vblank_lock; 64*4882a593Smuzhiyun wait_queue_head_t vblank_wait; 65*4882a593Smuzhiyun unsigned int vblank_count; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun struct rcar_du_group *group; 68*4882a593Smuzhiyun struct platform_device *cmm; 69*4882a593Smuzhiyun struct rcar_du_vsp *vsp; 70*4882a593Smuzhiyun unsigned int vsp_pipe; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun const char *const *sources; 73*4882a593Smuzhiyun unsigned int sources_count; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun struct drm_writeback_connector writeback; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define to_rcar_crtc(c) container_of(c, struct rcar_du_crtc, crtc) 79*4882a593Smuzhiyun #define wb_to_rcar_crtc(c) container_of(c, struct rcar_du_crtc, writeback) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /** 82*4882a593Smuzhiyun * struct rcar_du_crtc_state - Driver-specific CRTC state 83*4882a593Smuzhiyun * @state: base DRM CRTC state 84*4882a593Smuzhiyun * @crc: CRC computation configuration 85*4882a593Smuzhiyun * @outputs: bitmask of the outputs (enum rcar_du_output) driven by this CRTC 86*4882a593Smuzhiyun */ 87*4882a593Smuzhiyun struct rcar_du_crtc_state { 88*4882a593Smuzhiyun struct drm_crtc_state state; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun struct vsp1_du_crc_config crc; 91*4882a593Smuzhiyun unsigned int outputs; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define to_rcar_crtc_state(s) container_of(s, struct rcar_du_crtc_state, state) 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun enum rcar_du_output { 97*4882a593Smuzhiyun RCAR_DU_OUTPUT_DPAD0, 98*4882a593Smuzhiyun RCAR_DU_OUTPUT_DPAD1, 99*4882a593Smuzhiyun RCAR_DU_OUTPUT_LVDS0, 100*4882a593Smuzhiyun RCAR_DU_OUTPUT_LVDS1, 101*4882a593Smuzhiyun RCAR_DU_OUTPUT_HDMI0, 102*4882a593Smuzhiyun RCAR_DU_OUTPUT_HDMI1, 103*4882a593Smuzhiyun RCAR_DU_OUTPUT_TCON, 104*4882a593Smuzhiyun RCAR_DU_OUTPUT_MAX, 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int swindex, 108*4882a593Smuzhiyun unsigned int hwindex); 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc); 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun void rcar_du_crtc_dsysr_clr_set(struct rcar_du_crtc *rcrtc, u32 clr, u32 set); 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #endif /* __RCAR_DU_CRTC_H__ */ 115