1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2012 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * Authors: Alex Deucher 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun #ifndef _TRINITYD_H_ 25*4882a593Smuzhiyun #define _TRINITYD_H_ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* pm registers */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* cg */ 30*4882a593Smuzhiyun #define CG_CGTT_LOCAL_0 0x0 31*4882a593Smuzhiyun #define CG_CGTT_LOCAL_1 0x1 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* smc */ 34*4882a593Smuzhiyun #define SMU_SCLK_DPM_STATE_0_CNTL_0 0x1f000 35*4882a593Smuzhiyun # define STATE_VALID(x) ((x) << 0) 36*4882a593Smuzhiyun # define STATE_VALID_MASK (0xff << 0) 37*4882a593Smuzhiyun # define STATE_VALID_SHIFT 0 38*4882a593Smuzhiyun # define CLK_DIVIDER(x) ((x) << 8) 39*4882a593Smuzhiyun # define CLK_DIVIDER_MASK (0xff << 8) 40*4882a593Smuzhiyun # define CLK_DIVIDER_SHIFT 8 41*4882a593Smuzhiyun # define VID(x) ((x) << 16) 42*4882a593Smuzhiyun # define VID_MASK (0xff << 16) 43*4882a593Smuzhiyun # define VID_SHIFT 16 44*4882a593Smuzhiyun # define LVRT(x) ((x) << 24) 45*4882a593Smuzhiyun # define LVRT_MASK (0xff << 24) 46*4882a593Smuzhiyun # define LVRT_SHIFT 24 47*4882a593Smuzhiyun #define SMU_SCLK_DPM_STATE_0_CNTL_1 0x1f004 48*4882a593Smuzhiyun # define DS_DIV(x) ((x) << 0) 49*4882a593Smuzhiyun # define DS_DIV_MASK (0xff << 0) 50*4882a593Smuzhiyun # define DS_DIV_SHIFT 0 51*4882a593Smuzhiyun # define DS_SH_DIV(x) ((x) << 8) 52*4882a593Smuzhiyun # define DS_SH_DIV_MASK (0xff << 8) 53*4882a593Smuzhiyun # define DS_SH_DIV_SHIFT 8 54*4882a593Smuzhiyun # define DISPLAY_WM(x) ((x) << 16) 55*4882a593Smuzhiyun # define DISPLAY_WM_MASK (0xff << 16) 56*4882a593Smuzhiyun # define DISPLAY_WM_SHIFT 16 57*4882a593Smuzhiyun # define VCE_WM(x) ((x) << 24) 58*4882a593Smuzhiyun # define VCE_WM_MASK (0xff << 24) 59*4882a593Smuzhiyun # define VCE_WM_SHIFT 24 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define SMU_SCLK_DPM_STATE_0_CNTL_3 0x1f00c 62*4882a593Smuzhiyun # define GNB_SLOW(x) ((x) << 0) 63*4882a593Smuzhiyun # define GNB_SLOW_MASK (0xff << 0) 64*4882a593Smuzhiyun # define GNB_SLOW_SHIFT 0 65*4882a593Smuzhiyun # define FORCE_NBPS1(x) ((x) << 8) 66*4882a593Smuzhiyun # define FORCE_NBPS1_MASK (0xff << 8) 67*4882a593Smuzhiyun # define FORCE_NBPS1_SHIFT 8 68*4882a593Smuzhiyun #define SMU_SCLK_DPM_STATE_0_AT 0x1f010 69*4882a593Smuzhiyun # define AT(x) ((x) << 0) 70*4882a593Smuzhiyun # define AT_MASK (0xff << 0) 71*4882a593Smuzhiyun # define AT_SHIFT 0 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define SMU_SCLK_DPM_STATE_0_PG_CNTL 0x1f014 74*4882a593Smuzhiyun # define PD_SCLK_DIVIDER(x) ((x) << 16) 75*4882a593Smuzhiyun # define PD_SCLK_DIVIDER_MASK (0xff << 16) 76*4882a593Smuzhiyun # define PD_SCLK_DIVIDER_SHIFT 16 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define SMU_SCLK_DPM_STATE_1_CNTL_0 0x1f020 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define SMU_SCLK_DPM_CNTL 0x1f100 81*4882a593Smuzhiyun # define SCLK_DPM_EN(x) ((x) << 0) 82*4882a593Smuzhiyun # define SCLK_DPM_EN_MASK (0xff << 0) 83*4882a593Smuzhiyun # define SCLK_DPM_EN_SHIFT 0 84*4882a593Smuzhiyun # define SCLK_DPM_BOOT_STATE(x) ((x) << 16) 85*4882a593Smuzhiyun # define SCLK_DPM_BOOT_STATE_MASK (0xff << 16) 86*4882a593Smuzhiyun # define SCLK_DPM_BOOT_STATE_SHIFT 16 87*4882a593Smuzhiyun # define VOLTAGE_CHG_EN(x) ((x) << 24) 88*4882a593Smuzhiyun # define VOLTAGE_CHG_EN_MASK (0xff << 24) 89*4882a593Smuzhiyun # define VOLTAGE_CHG_EN_SHIFT 24 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define SMU_SCLK_DPM_TT_CNTL 0x1f108 92*4882a593Smuzhiyun # define SCLK_TT_EN(x) ((x) << 0) 93*4882a593Smuzhiyun # define SCLK_TT_EN_MASK (0xff << 0) 94*4882a593Smuzhiyun # define SCLK_TT_EN_SHIFT 0 95*4882a593Smuzhiyun #define SMU_SCLK_DPM_TTT 0x1f10c 96*4882a593Smuzhiyun # define LT(x) ((x) << 0) 97*4882a593Smuzhiyun # define LT_MASK (0xffff << 0) 98*4882a593Smuzhiyun # define LT_SHIFT 0 99*4882a593Smuzhiyun # define HT(x) ((x) << 16) 100*4882a593Smuzhiyun # define HT_MASK (0xffff << 16) 101*4882a593Smuzhiyun # define HT_SHIFT 16 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define SMU_UVD_DPM_STATES 0x1f1a0 104*4882a593Smuzhiyun #define SMU_UVD_DPM_CNTL 0x1f1a4 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #define SMU_S_PG_CNTL 0x1f118 107*4882a593Smuzhiyun # define DS_PG_EN(x) ((x) << 16) 108*4882a593Smuzhiyun # define DS_PG_EN_MASK (0xff << 16) 109*4882a593Smuzhiyun # define DS_PG_EN_SHIFT 16 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #define GFX_POWER_GATING_CNTL 0x1f38c 112*4882a593Smuzhiyun # define PDS_DIV(x) ((x) << 0) 113*4882a593Smuzhiyun # define PDS_DIV_MASK (0xff << 0) 114*4882a593Smuzhiyun # define PDS_DIV_SHIFT 0 115*4882a593Smuzhiyun # define SSSD(x) ((x) << 8) 116*4882a593Smuzhiyun # define SSSD_MASK (0xff << 8) 117*4882a593Smuzhiyun # define SSSD_SHIFT 8 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define PM_CONFIG 0x1f428 120*4882a593Smuzhiyun # define SVI_Mode (1 << 29) 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun #define PM_I_CNTL_1 0x1f464 123*4882a593Smuzhiyun # define SCLK_DPM(x) ((x) << 0) 124*4882a593Smuzhiyun # define SCLK_DPM_MASK (0xff << 0) 125*4882a593Smuzhiyun # define SCLK_DPM_SHIFT 0 126*4882a593Smuzhiyun # define DS_PG_CNTL(x) ((x) << 16) 127*4882a593Smuzhiyun # define DS_PG_CNTL_MASK (0xff << 16) 128*4882a593Smuzhiyun # define DS_PG_CNTL_SHIFT 16 129*4882a593Smuzhiyun #define PM_TP 0x1f468 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #define NB_PSTATE_CONFIG 0x1f5f8 132*4882a593Smuzhiyun # define Dpm0PgNbPsLo(x) ((x) << 0) 133*4882a593Smuzhiyun # define Dpm0PgNbPsLo_MASK (3 << 0) 134*4882a593Smuzhiyun # define Dpm0PgNbPsLo_SHIFT 0 135*4882a593Smuzhiyun # define Dpm0PgNbPsHi(x) ((x) << 2) 136*4882a593Smuzhiyun # define Dpm0PgNbPsHi_MASK (3 << 2) 137*4882a593Smuzhiyun # define Dpm0PgNbPsHi_SHIFT 2 138*4882a593Smuzhiyun # define DpmXNbPsLo(x) ((x) << 4) 139*4882a593Smuzhiyun # define DpmXNbPsLo_MASK (3 << 4) 140*4882a593Smuzhiyun # define DpmXNbPsLo_SHIFT 4 141*4882a593Smuzhiyun # define DpmXNbPsHi(x) ((x) << 6) 142*4882a593Smuzhiyun # define DpmXNbPsHi_MASK (3 << 6) 143*4882a593Smuzhiyun # define DpmXNbPsHi_SHIFT 6 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun #define DC_CAC_VALUE 0x1f908 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun #define GPU_CAC_AVRG_CNTL 0x1f920 148*4882a593Smuzhiyun # define WINDOW_SIZE(x) ((x) << 0) 149*4882a593Smuzhiyun # define WINDOW_SIZE_MASK (0xff << 0) 150*4882a593Smuzhiyun # define WINDOW_SIZE_SHIFT 0 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun #define CC_SMU_MISC_FUSES 0xe0001004 153*4882a593Smuzhiyun # define MinSClkDid(x) ((x) << 2) 154*4882a593Smuzhiyun # define MinSClkDid_MASK (0x7f << 2) 155*4882a593Smuzhiyun # define MinSClkDid_SHIFT 2 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun #define CC_SMU_TST_EFUSE1_MISC 0xe000101c 158*4882a593Smuzhiyun # define RB_BACKEND_DISABLE(x) ((x) << 16) 159*4882a593Smuzhiyun # define RB_BACKEND_DISABLE_MASK (3 << 16) 160*4882a593Smuzhiyun # define RB_BACKEND_DISABLE_SHIFT 16 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun #define SMU_SCRATCH_A 0xe0003024 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun #define SMU_SCRATCH0 0xe0003040 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun /* mmio */ 167*4882a593Smuzhiyun #define SMC_INT_REQ 0x220 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun #define SMC_MESSAGE_0 0x22c 170*4882a593Smuzhiyun #define SMC_RESP_0 0x230 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun #define GENERAL_PWRMGT 0x670 173*4882a593Smuzhiyun # define GLOBAL_PWRMGT_EN (1 << 0) 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun #define SCLK_PWRMGT_CNTL 0x678 176*4882a593Smuzhiyun # define DYN_PWR_DOWN_EN (1 << 2) 177*4882a593Smuzhiyun # define RESET_BUSY_CNT (1 << 4) 178*4882a593Smuzhiyun # define RESET_SCLK_CNT (1 << 5) 179*4882a593Smuzhiyun # define DYN_GFX_CLK_OFF_EN (1 << 7) 180*4882a593Smuzhiyun # define GFX_CLK_FORCE_ON (1 << 8) 181*4882a593Smuzhiyun # define DYNAMIC_PM_EN (1 << 21) 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun #define TARGET_AND_CURRENT_PROFILE_INDEX 0x684 184*4882a593Smuzhiyun # define TARGET_STATE(x) ((x) << 0) 185*4882a593Smuzhiyun # define TARGET_STATE_MASK (0xf << 0) 186*4882a593Smuzhiyun # define TARGET_STATE_SHIFT 0 187*4882a593Smuzhiyun # define CURRENT_STATE(x) ((x) << 4) 188*4882a593Smuzhiyun # define CURRENT_STATE_MASK (0xf << 4) 189*4882a593Smuzhiyun # define CURRENT_STATE_SHIFT 4 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun #define CG_GIPOTS 0x6d8 192*4882a593Smuzhiyun # define CG_GIPOT(x) ((x) << 16) 193*4882a593Smuzhiyun # define CG_GIPOT_MASK (0xffff << 16) 194*4882a593Smuzhiyun # define CG_GIPOT_SHIFT 16 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun #define CG_PG_CTRL 0x6e0 197*4882a593Smuzhiyun # define SP(x) ((x) << 0) 198*4882a593Smuzhiyun # define SP_MASK (0xffff << 0) 199*4882a593Smuzhiyun # define SP_SHIFT 0 200*4882a593Smuzhiyun # define SU(x) ((x) << 16) 201*4882a593Smuzhiyun # define SU_MASK (0xffff << 16) 202*4882a593Smuzhiyun # define SU_SHIFT 16 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun #define CG_MISC_REG 0x708 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun #define CG_THERMAL_INT_CTRL 0x738 207*4882a593Smuzhiyun # define DIG_THERM_INTH(x) ((x) << 0) 208*4882a593Smuzhiyun # define DIG_THERM_INTH_MASK (0xff << 0) 209*4882a593Smuzhiyun # define DIG_THERM_INTH_SHIFT 0 210*4882a593Smuzhiyun # define DIG_THERM_INTL(x) ((x) << 8) 211*4882a593Smuzhiyun # define DIG_THERM_INTL_MASK (0xff << 8) 212*4882a593Smuzhiyun # define DIG_THERM_INTL_SHIFT 8 213*4882a593Smuzhiyun # define THERM_INTH_MASK (1 << 24) 214*4882a593Smuzhiyun # define THERM_INTL_MASK (1 << 25) 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun #define CG_CG_VOLTAGE_CNTL 0x770 217*4882a593Smuzhiyun # define EN (1 << 9) 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun #define HW_REV 0x5564 220*4882a593Smuzhiyun # define ATI_REV_ID_MASK (0xf << 28) 221*4882a593Smuzhiyun # define ATI_REV_ID_SHIFT 28 222*4882a593Smuzhiyun /* 0 = A0, 1 = A1, 2 = B0, 3 = C0, etc. */ 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun #define CGTS_SM_CTRL_REG 0x9150 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun #define GB_ADDR_CONFIG 0x98f8 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun #endif 229