1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2012 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun #ifndef __TRINITY_DPM_H__ 24*4882a593Smuzhiyun #define __TRINITY_DPM_H__ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #include "sumo_dpm.h" 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define TRINITY_SIZEOF_DPM_STATE_TABLE (SMU_SCLK_DPM_STATE_1_CNTL_0 - SMU_SCLK_DPM_STATE_0_CNTL_0) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun struct trinity_pl { 31*4882a593Smuzhiyun u32 sclk; 32*4882a593Smuzhiyun u8 vddc_index; 33*4882a593Smuzhiyun u8 ds_divider_index; 34*4882a593Smuzhiyun u8 ss_divider_index; 35*4882a593Smuzhiyun u8 allow_gnb_slow; 36*4882a593Smuzhiyun u8 force_nbp_state; 37*4882a593Smuzhiyun u8 display_wm; 38*4882a593Smuzhiyun u8 vce_wm; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define TRINITY_POWERSTATE_FLAGS_NBPS_FORCEHIGH (1 << 0) 42*4882a593Smuzhiyun #define TRINITY_POWERSTATE_FLAGS_NBPS_LOCKTOHIGH (1 << 1) 43*4882a593Smuzhiyun #define TRINITY_POWERSTATE_FLAGS_NBPS_LOCKTOLOW (1 << 2) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define TRINITY_POWERSTATE_FLAGS_BAPM_DISABLE (1 << 0) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun struct trinity_ps { 48*4882a593Smuzhiyun u32 num_levels; 49*4882a593Smuzhiyun struct trinity_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS]; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun u32 nbps_flags; 52*4882a593Smuzhiyun u32 bapm_flags; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun u8 Dpm0PgNbPsLo; 55*4882a593Smuzhiyun u8 Dpm0PgNbPsHi; 56*4882a593Smuzhiyun u8 DpmXNbPsLo; 57*4882a593Smuzhiyun u8 DpmXNbPsHi; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun u32 vclk_low_divider; 60*4882a593Smuzhiyun u32 vclk_high_divider; 61*4882a593Smuzhiyun u32 dclk_low_divider; 62*4882a593Smuzhiyun u32 dclk_high_divider; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define TRINITY_NUM_NBPSTATES 4 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun struct trinity_uvd_clock_table_entry 68*4882a593Smuzhiyun { 69*4882a593Smuzhiyun u32 vclk; 70*4882a593Smuzhiyun u32 dclk; 71*4882a593Smuzhiyun u8 vclk_did; 72*4882a593Smuzhiyun u8 dclk_did; 73*4882a593Smuzhiyun u8 rsv[2]; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun struct trinity_sys_info { 77*4882a593Smuzhiyun u32 bootup_uma_clk; 78*4882a593Smuzhiyun u32 bootup_sclk; 79*4882a593Smuzhiyun u32 min_sclk; 80*4882a593Smuzhiyun u32 dentist_vco_freq; 81*4882a593Smuzhiyun u32 nb_dpm_enable; 82*4882a593Smuzhiyun u32 nbp_mclk[TRINITY_NUM_NBPSTATES]; 83*4882a593Smuzhiyun u32 nbp_nclk[TRINITY_NUM_NBPSTATES]; 84*4882a593Smuzhiyun u16 nbp_voltage_index[TRINITY_NUM_NBPSTATES]; 85*4882a593Smuzhiyun u16 bootup_nb_voltage_index; 86*4882a593Smuzhiyun u8 htc_tmp_lmt; 87*4882a593Smuzhiyun u8 htc_hyst_lmt; 88*4882a593Smuzhiyun struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table; 89*4882a593Smuzhiyun struct sumo_vid_mapping_table vid_mapping_table; 90*4882a593Smuzhiyun u32 uma_channel_number; 91*4882a593Smuzhiyun struct trinity_uvd_clock_table_entry uvd_clock_table_entries[4]; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun struct trinity_power_info { 95*4882a593Smuzhiyun u32 at[SUMO_MAX_HARDWARE_POWERLEVELS]; 96*4882a593Smuzhiyun u32 dpm_interval; 97*4882a593Smuzhiyun u32 thermal_auto_throttling; 98*4882a593Smuzhiyun struct trinity_sys_info sys_info; 99*4882a593Smuzhiyun struct trinity_pl boot_pl; 100*4882a593Smuzhiyun u32 min_sclk_did; 101*4882a593Smuzhiyun bool enable_nbps_policy; 102*4882a593Smuzhiyun bool voltage_drop_in_dce; 103*4882a593Smuzhiyun bool override_dynamic_mgpg; 104*4882a593Smuzhiyun bool enable_gfx_clock_gating; 105*4882a593Smuzhiyun bool enable_gfx_power_gating; 106*4882a593Smuzhiyun bool enable_mg_clock_gating; 107*4882a593Smuzhiyun bool enable_gfx_dynamic_mgpg; 108*4882a593Smuzhiyun bool enable_auto_thermal_throttling; 109*4882a593Smuzhiyun bool enable_dpm; 110*4882a593Smuzhiyun bool enable_sclk_ds; 111*4882a593Smuzhiyun bool enable_bapm; 112*4882a593Smuzhiyun bool uvd_dpm; 113*4882a593Smuzhiyun struct radeon_ps current_rps; 114*4882a593Smuzhiyun struct trinity_ps current_ps; 115*4882a593Smuzhiyun struct radeon_ps requested_rps; 116*4882a593Smuzhiyun struct trinity_ps requested_ps; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define TRINITY_AT_DFLT 30 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /* trinity_smc.c */ 122*4882a593Smuzhiyun int trinity_dpm_bapm_enable(struct radeon_device *rdev, bool enable); 123*4882a593Smuzhiyun int trinity_dpm_config(struct radeon_device *rdev, bool enable); 124*4882a593Smuzhiyun int trinity_uvd_dpm_config(struct radeon_device *rdev); 125*4882a593Smuzhiyun int trinity_dpm_force_state(struct radeon_device *rdev, u32 n); 126*4882a593Smuzhiyun int trinity_dpm_n_levels_disabled(struct radeon_device *rdev, u32 n); 127*4882a593Smuzhiyun int trinity_dpm_no_forced_level(struct radeon_device *rdev); 128*4882a593Smuzhiyun int trinity_dce_enable_voltage_adjustment(struct radeon_device *rdev, 129*4882a593Smuzhiyun bool enable); 130*4882a593Smuzhiyun int trinity_gfx_dynamic_mgpg_config(struct radeon_device *rdev); 131*4882a593Smuzhiyun void trinity_acquire_mutex(struct radeon_device *rdev); 132*4882a593Smuzhiyun void trinity_release_mutex(struct radeon_device *rdev); 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #endif 135