1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2012 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * Authors: Alex Deucher 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun #ifndef _SUMOD_H_ 25*4882a593Smuzhiyun #define _SUMOD_H_ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* pm registers */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* rcu */ 30*4882a593Smuzhiyun #define RCU_FW_VERSION 0x30c 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define RCU_PWR_GATING_SEQ0 0x408 33*4882a593Smuzhiyun #define RCU_PWR_GATING_SEQ1 0x40c 34*4882a593Smuzhiyun #define RCU_PWR_GATING_CNTL 0x410 35*4882a593Smuzhiyun # define PWR_GATING_EN (1 << 0) 36*4882a593Smuzhiyun # define RSVD_MASK (0x3 << 1) 37*4882a593Smuzhiyun # define PCV(x) ((x) << 3) 38*4882a593Smuzhiyun # define PCV_MASK (0x1f << 3) 39*4882a593Smuzhiyun # define PCV_SHIFT 3 40*4882a593Smuzhiyun # define PCP(x) ((x) << 8) 41*4882a593Smuzhiyun # define PCP_MASK (0xf << 8) 42*4882a593Smuzhiyun # define PCP_SHIFT 8 43*4882a593Smuzhiyun # define RPW(x) ((x) << 16) 44*4882a593Smuzhiyun # define RPW_MASK (0xf << 16) 45*4882a593Smuzhiyun # define RPW_SHIFT 16 46*4882a593Smuzhiyun # define ID(x) ((x) << 24) 47*4882a593Smuzhiyun # define ID_MASK (0xf << 24) 48*4882a593Smuzhiyun # define ID_SHIFT 24 49*4882a593Smuzhiyun # define PGS(x) ((x) << 28) 50*4882a593Smuzhiyun # define PGS_MASK (0xf << 28) 51*4882a593Smuzhiyun # define PGS_SHIFT 28 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define RCU_ALTVDDNB_NOTIFY 0x430 54*4882a593Smuzhiyun #define RCU_LCLK_SCALING_CNTL 0x434 55*4882a593Smuzhiyun # define LCLK_SCALING_EN (1 << 0) 56*4882a593Smuzhiyun # define LCLK_SCALING_TYPE (1 << 1) 57*4882a593Smuzhiyun # define LCLK_SCALING_TIMER_PRESCALER(x) ((x) << 4) 58*4882a593Smuzhiyun # define LCLK_SCALING_TIMER_PRESCALER_MASK (0xf << 4) 59*4882a593Smuzhiyun # define LCLK_SCALING_TIMER_PRESCALER_SHIFT 4 60*4882a593Smuzhiyun # define LCLK_SCALING_TIMER_PERIOD(x) ((x) << 16) 61*4882a593Smuzhiyun # define LCLK_SCALING_TIMER_PERIOD_MASK (0xf << 16) 62*4882a593Smuzhiyun # define LCLK_SCALING_TIMER_PERIOD_SHIFT 16 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define RCU_PWR_GATING_CNTL_2 0x4a0 65*4882a593Smuzhiyun # define MPPU(x) ((x) << 0) 66*4882a593Smuzhiyun # define MPPU_MASK (0xffff << 0) 67*4882a593Smuzhiyun # define MPPU_SHIFT 0 68*4882a593Smuzhiyun # define MPPD(x) ((x) << 16) 69*4882a593Smuzhiyun # define MPPD_MASK (0xffff << 16) 70*4882a593Smuzhiyun # define MPPD_SHIFT 16 71*4882a593Smuzhiyun #define RCU_PWR_GATING_CNTL_3 0x4a4 72*4882a593Smuzhiyun # define DPPU(x) ((x) << 0) 73*4882a593Smuzhiyun # define DPPU_MASK (0xffff << 0) 74*4882a593Smuzhiyun # define DPPU_SHIFT 0 75*4882a593Smuzhiyun # define DPPD(x) ((x) << 16) 76*4882a593Smuzhiyun # define DPPD_MASK (0xffff << 16) 77*4882a593Smuzhiyun # define DPPD_SHIFT 16 78*4882a593Smuzhiyun #define RCU_PWR_GATING_CNTL_4 0x4a8 79*4882a593Smuzhiyun # define RT(x) ((x) << 0) 80*4882a593Smuzhiyun # define RT_MASK (0xffff << 0) 81*4882a593Smuzhiyun # define RT_SHIFT 0 82*4882a593Smuzhiyun # define IT(x) ((x) << 16) 83*4882a593Smuzhiyun # define IT_MASK (0xffff << 16) 84*4882a593Smuzhiyun # define IT_SHIFT 16 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* yes these two have the same address */ 87*4882a593Smuzhiyun #define RCU_PWR_GATING_CNTL_5 0x504 88*4882a593Smuzhiyun #define RCU_GPU_BOOST_DISABLE 0x508 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define MCU_M3ARB_INDEX 0x504 91*4882a593Smuzhiyun #define MCU_M3ARB_PARAMS 0x508 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define RCU_GNB_PWR_REP_TIMER_CNTL 0x50C 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define RCU_SclkDpmTdpLimit01 0x514 96*4882a593Smuzhiyun #define RCU_SclkDpmTdpLimit23 0x518 97*4882a593Smuzhiyun #define RCU_SclkDpmTdpLimit47 0x51C 98*4882a593Smuzhiyun #define RCU_SclkDpmTdpLimitPG 0x520 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define GNB_TDP_LIMIT 0x540 101*4882a593Smuzhiyun #define RCU_BOOST_MARGIN 0x544 102*4882a593Smuzhiyun #define RCU_THROTTLE_MARGIN 0x548 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define SMU_PCIE_PG_ARGS 0x58C 105*4882a593Smuzhiyun #define SMU_PCIE_PG_ARGS_2 0x598 106*4882a593Smuzhiyun #define SMU_PCIE_PG_ARGS_3 0x59C 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* mmio */ 109*4882a593Smuzhiyun #define RCU_STATUS 0x11c 110*4882a593Smuzhiyun # define GMC_PWR_GATER_BUSY (1 << 8) 111*4882a593Smuzhiyun # define GFX_PWR_GATER_BUSY (1 << 9) 112*4882a593Smuzhiyun # define UVD_PWR_GATER_BUSY (1 << 10) 113*4882a593Smuzhiyun # define PCIE_PWR_GATER_BUSY (1 << 11) 114*4882a593Smuzhiyun # define GMC_PWR_GATER_STATE (1 << 12) 115*4882a593Smuzhiyun # define GFX_PWR_GATER_STATE (1 << 13) 116*4882a593Smuzhiyun # define UVD_PWR_GATER_STATE (1 << 14) 117*4882a593Smuzhiyun # define PCIE_PWR_GATER_STATE (1 << 15) 118*4882a593Smuzhiyun # define GFX1_PWR_GATER_BUSY (1 << 16) 119*4882a593Smuzhiyun # define GFX2_PWR_GATER_BUSY (1 << 17) 120*4882a593Smuzhiyun # define GFX1_PWR_GATER_STATE (1 << 18) 121*4882a593Smuzhiyun # define GFX2_PWR_GATER_STATE (1 << 19) 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #define GFX_INT_REQ 0x120 124*4882a593Smuzhiyun # define INT_REQ (1 << 0) 125*4882a593Smuzhiyun # define SERV_INDEX(x) ((x) << 1) 126*4882a593Smuzhiyun # define SERV_INDEX_MASK (0xff << 1) 127*4882a593Smuzhiyun # define SERV_INDEX_SHIFT 1 128*4882a593Smuzhiyun #define GFX_INT_STATUS 0x124 129*4882a593Smuzhiyun # define INT_ACK (1 << 0) 130*4882a593Smuzhiyun # define INT_DONE (1 << 1) 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #define CG_SCLK_CNTL 0x600 133*4882a593Smuzhiyun # define SCLK_DIVIDER(x) ((x) << 0) 134*4882a593Smuzhiyun # define SCLK_DIVIDER_MASK (0x7f << 0) 135*4882a593Smuzhiyun # define SCLK_DIVIDER_SHIFT 0 136*4882a593Smuzhiyun #define CG_SCLK_STATUS 0x604 137*4882a593Smuzhiyun # define SCLK_OVERCLK_DETECT (1 << 2) 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun #define CG_DCLK_CNTL 0x610 140*4882a593Smuzhiyun # define DCLK_DIVIDER_MASK 0x7f 141*4882a593Smuzhiyun # define DCLK_DIR_CNTL_EN (1 << 8) 142*4882a593Smuzhiyun #define CG_DCLK_STATUS 0x614 143*4882a593Smuzhiyun # define DCLK_STATUS (1 << 0) 144*4882a593Smuzhiyun #define CG_VCLK_CNTL 0x618 145*4882a593Smuzhiyun # define VCLK_DIVIDER_MASK 0x7f 146*4882a593Smuzhiyun # define VCLK_DIR_CNTL_EN (1 << 8) 147*4882a593Smuzhiyun #define CG_VCLK_STATUS 0x61c 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun #define GENERAL_PWRMGT 0x63c 150*4882a593Smuzhiyun # define STATIC_PM_EN (1 << 1) 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun #define SCLK_PWRMGT_CNTL 0x644 153*4882a593Smuzhiyun # define SCLK_PWRMGT_OFF (1 << 0) 154*4882a593Smuzhiyun # define SCLK_LOW_D1 (1 << 1) 155*4882a593Smuzhiyun # define FIR_RESET (1 << 4) 156*4882a593Smuzhiyun # define FIR_FORCE_TREND_SEL (1 << 5) 157*4882a593Smuzhiyun # define FIR_TREND_MODE (1 << 6) 158*4882a593Smuzhiyun # define DYN_GFX_CLK_OFF_EN (1 << 7) 159*4882a593Smuzhiyun # define GFX_CLK_FORCE_ON (1 << 8) 160*4882a593Smuzhiyun # define GFX_CLK_REQUEST_OFF (1 << 9) 161*4882a593Smuzhiyun # define GFX_CLK_FORCE_OFF (1 << 10) 162*4882a593Smuzhiyun # define GFX_CLK_OFF_ACPI_D1 (1 << 11) 163*4882a593Smuzhiyun # define GFX_CLK_OFF_ACPI_D2 (1 << 12) 164*4882a593Smuzhiyun # define GFX_CLK_OFF_ACPI_D3 (1 << 13) 165*4882a593Smuzhiyun # define GFX_VOLTAGE_CHANGE_EN (1 << 16) 166*4882a593Smuzhiyun # define GFX_VOLTAGE_CHANGE_MODE (1 << 17) 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun #define TARGET_AND_CURRENT_PROFILE_INDEX 0x66c 169*4882a593Smuzhiyun # define TARG_SCLK_INDEX(x) ((x) << 6) 170*4882a593Smuzhiyun # define TARG_SCLK_INDEX_MASK (0x7 << 6) 171*4882a593Smuzhiyun # define TARG_SCLK_INDEX_SHIFT 6 172*4882a593Smuzhiyun # define CURR_SCLK_INDEX(x) ((x) << 9) 173*4882a593Smuzhiyun # define CURR_SCLK_INDEX_MASK (0x7 << 9) 174*4882a593Smuzhiyun # define CURR_SCLK_INDEX_SHIFT 9 175*4882a593Smuzhiyun # define TARG_INDEX(x) ((x) << 12) 176*4882a593Smuzhiyun # define TARG_INDEX_MASK (0x7 << 12) 177*4882a593Smuzhiyun # define TARG_INDEX_SHIFT 12 178*4882a593Smuzhiyun # define CURR_INDEX(x) ((x) << 15) 179*4882a593Smuzhiyun # define CURR_INDEX_MASK (0x7 << 15) 180*4882a593Smuzhiyun # define CURR_INDEX_SHIFT 15 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun #define CG_SCLK_DPM_CTRL 0x684 183*4882a593Smuzhiyun # define SCLK_FSTATE_0_DIV(x) ((x) << 0) 184*4882a593Smuzhiyun # define SCLK_FSTATE_0_DIV_MASK (0x7f << 0) 185*4882a593Smuzhiyun # define SCLK_FSTATE_0_DIV_SHIFT 0 186*4882a593Smuzhiyun # define SCLK_FSTATE_0_VLD (1 << 7) 187*4882a593Smuzhiyun # define SCLK_FSTATE_1_DIV(x) ((x) << 8) 188*4882a593Smuzhiyun # define SCLK_FSTATE_1_DIV_MASK (0x7f << 8) 189*4882a593Smuzhiyun # define SCLK_FSTATE_1_DIV_SHIFT 8 190*4882a593Smuzhiyun # define SCLK_FSTATE_1_VLD (1 << 15) 191*4882a593Smuzhiyun # define SCLK_FSTATE_2_DIV(x) ((x) << 16) 192*4882a593Smuzhiyun # define SCLK_FSTATE_2_DIV_MASK (0x7f << 16) 193*4882a593Smuzhiyun # define SCLK_FSTATE_2_DIV_SHIFT 16 194*4882a593Smuzhiyun # define SCLK_FSTATE_2_VLD (1 << 23) 195*4882a593Smuzhiyun # define SCLK_FSTATE_3_DIV(x) ((x) << 24) 196*4882a593Smuzhiyun # define SCLK_FSTATE_3_DIV_MASK (0x7f << 24) 197*4882a593Smuzhiyun # define SCLK_FSTATE_3_DIV_SHIFT 24 198*4882a593Smuzhiyun # define SCLK_FSTATE_3_VLD (1 << 31) 199*4882a593Smuzhiyun #define CG_SCLK_DPM_CTRL_2 0x688 200*4882a593Smuzhiyun #define CG_GCOOR 0x68c 201*4882a593Smuzhiyun # define PHC(x) ((x) << 0) 202*4882a593Smuzhiyun # define PHC_MASK (0x1f << 0) 203*4882a593Smuzhiyun # define PHC_SHIFT 0 204*4882a593Smuzhiyun # define SDC(x) ((x) << 9) 205*4882a593Smuzhiyun # define SDC_MASK (0x3ff << 9) 206*4882a593Smuzhiyun # define SDC_SHIFT 9 207*4882a593Smuzhiyun # define SU(x) ((x) << 23) 208*4882a593Smuzhiyun # define SU_MASK (0xf << 23) 209*4882a593Smuzhiyun # define SU_SHIFT 23 210*4882a593Smuzhiyun # define DIV_ID(x) ((x) << 28) 211*4882a593Smuzhiyun # define DIV_ID_MASK (0x7 << 28) 212*4882a593Smuzhiyun # define DIV_ID_SHIFT 28 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun #define CG_FTV 0x690 215*4882a593Smuzhiyun #define CG_FFCT_0 0x694 216*4882a593Smuzhiyun # define UTC_0(x) ((x) << 0) 217*4882a593Smuzhiyun # define UTC_0_MASK (0x3ff << 0) 218*4882a593Smuzhiyun # define UTC_0_SHIFT 0 219*4882a593Smuzhiyun # define DTC_0(x) ((x) << 10) 220*4882a593Smuzhiyun # define DTC_0_MASK (0x3ff << 10) 221*4882a593Smuzhiyun # define DTC_0_SHIFT 10 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun #define CG_GIT 0x6d8 224*4882a593Smuzhiyun # define CG_GICST(x) ((x) << 0) 225*4882a593Smuzhiyun # define CG_GICST_MASK (0xffff << 0) 226*4882a593Smuzhiyun # define CG_GICST_SHIFT 0 227*4882a593Smuzhiyun # define CG_GIPOT(x) ((x) << 16) 228*4882a593Smuzhiyun # define CG_GIPOT_MASK (0xffff << 16) 229*4882a593Smuzhiyun # define CG_GIPOT_SHIFT 16 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun #define CG_SCLK_DPM_CTRL_3 0x6e0 232*4882a593Smuzhiyun # define FORCE_SCLK_STATE(x) ((x) << 0) 233*4882a593Smuzhiyun # define FORCE_SCLK_STATE_MASK (0x7 << 0) 234*4882a593Smuzhiyun # define FORCE_SCLK_STATE_SHIFT 0 235*4882a593Smuzhiyun # define FORCE_SCLK_STATE_EN (1 << 3) 236*4882a593Smuzhiyun # define GNB_TT(x) ((x) << 8) 237*4882a593Smuzhiyun # define GNB_TT_MASK (0xff << 8) 238*4882a593Smuzhiyun # define GNB_TT_SHIFT 8 239*4882a593Smuzhiyun # define GNB_THERMTHRO_MASK (1 << 16) 240*4882a593Smuzhiyun # define CNB_THERMTHRO_MASK_SCLK (1 << 17) 241*4882a593Smuzhiyun # define DPM_SCLK_ENABLE (1 << 18) 242*4882a593Smuzhiyun # define GNB_SLOW_FSTATE_0_MASK (1 << 23) 243*4882a593Smuzhiyun # define GNB_SLOW_FSTATE_0_SHIFT 23 244*4882a593Smuzhiyun # define FORCE_NB_PSTATE_1 (1 << 31) 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun #define CG_SSP 0x6e8 247*4882a593Smuzhiyun # define SST(x) ((x) << 0) 248*4882a593Smuzhiyun # define SST_MASK (0xffff << 0) 249*4882a593Smuzhiyun # define SST_SHIFT 0 250*4882a593Smuzhiyun # define SSTU(x) ((x) << 16) 251*4882a593Smuzhiyun # define SSTU_MASK (0xffff << 16) 252*4882a593Smuzhiyun # define SSTU_SHIFT 16 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun #define CG_ACPI_CNTL 0x70c 255*4882a593Smuzhiyun # define SCLK_ACPI_DIV(x) ((x) << 0) 256*4882a593Smuzhiyun # define SCLK_ACPI_DIV_MASK (0x7f << 0) 257*4882a593Smuzhiyun # define SCLK_ACPI_DIV_SHIFT 0 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun #define CG_SCLK_DPM_CTRL_4 0x71c 260*4882a593Smuzhiyun # define DC_HDC(x) ((x) << 14) 261*4882a593Smuzhiyun # define DC_HDC_MASK (0x3fff << 14) 262*4882a593Smuzhiyun # define DC_HDC_SHIFT 14 263*4882a593Smuzhiyun # define DC_HU(x) ((x) << 28) 264*4882a593Smuzhiyun # define DC_HU_MASK (0xf << 28) 265*4882a593Smuzhiyun # define DC_HU_SHIFT 28 266*4882a593Smuzhiyun #define CG_SCLK_DPM_CTRL_5 0x720 267*4882a593Smuzhiyun # define SCLK_FSTATE_BOOTUP(x) ((x) << 0) 268*4882a593Smuzhiyun # define SCLK_FSTATE_BOOTUP_MASK (0x7 << 0) 269*4882a593Smuzhiyun # define SCLK_FSTATE_BOOTUP_SHIFT 0 270*4882a593Smuzhiyun # define TT_TP(x) ((x) << 3) 271*4882a593Smuzhiyun # define TT_TP_MASK (0xffff << 3) 272*4882a593Smuzhiyun # define TT_TP_SHIFT 3 273*4882a593Smuzhiyun # define TT_TU(x) ((x) << 19) 274*4882a593Smuzhiyun # define TT_TU_MASK (0xff << 19) 275*4882a593Smuzhiyun # define TT_TU_SHIFT 19 276*4882a593Smuzhiyun #define CG_SCLK_DPM_CTRL_6 0x724 277*4882a593Smuzhiyun #define CG_AT_0 0x728 278*4882a593Smuzhiyun # define CG_R(x) ((x) << 0) 279*4882a593Smuzhiyun # define CG_R_MASK (0xffff << 0) 280*4882a593Smuzhiyun # define CG_R_SHIFT 0 281*4882a593Smuzhiyun # define CG_L(x) ((x) << 16) 282*4882a593Smuzhiyun # define CG_L_MASK (0xffff << 16) 283*4882a593Smuzhiyun # define CG_L_SHIFT 16 284*4882a593Smuzhiyun #define CG_AT_1 0x72c 285*4882a593Smuzhiyun #define CG_AT_2 0x730 286*4882a593Smuzhiyun #define CG_THERMAL_INT 0x734 287*4882a593Smuzhiyun #define DIG_THERM_INTH(x) ((x) << 8) 288*4882a593Smuzhiyun #define DIG_THERM_INTH_MASK 0x0000FF00 289*4882a593Smuzhiyun #define DIG_THERM_INTH_SHIFT 8 290*4882a593Smuzhiyun #define DIG_THERM_INTL(x) ((x) << 16) 291*4882a593Smuzhiyun #define DIG_THERM_INTL_MASK 0x00FF0000 292*4882a593Smuzhiyun #define DIG_THERM_INTL_SHIFT 16 293*4882a593Smuzhiyun #define THERM_INT_MASK_HIGH (1 << 24) 294*4882a593Smuzhiyun #define THERM_INT_MASK_LOW (1 << 25) 295*4882a593Smuzhiyun #define CG_AT_3 0x738 296*4882a593Smuzhiyun #define CG_AT_4 0x73c 297*4882a593Smuzhiyun #define CG_AT_5 0x740 298*4882a593Smuzhiyun #define CG_AT_6 0x744 299*4882a593Smuzhiyun #define CG_AT_7 0x748 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun #define CG_BSP_0 0x750 302*4882a593Smuzhiyun # define BSP(x) ((x) << 0) 303*4882a593Smuzhiyun # define BSP_MASK (0xffff << 0) 304*4882a593Smuzhiyun # define BSP_SHIFT 0 305*4882a593Smuzhiyun # define BSU(x) ((x) << 16) 306*4882a593Smuzhiyun # define BSU_MASK (0xf << 16) 307*4882a593Smuzhiyun # define BSU_SHIFT 16 308*4882a593Smuzhiyun 309*4882a593Smuzhiyun #define CG_CG_VOLTAGE_CNTL 0x770 310*4882a593Smuzhiyun # define REQ (1 << 0) 311*4882a593Smuzhiyun # define LEVEL(x) ((x) << 1) 312*4882a593Smuzhiyun # define LEVEL_MASK (0x3 << 1) 313*4882a593Smuzhiyun # define LEVEL_SHIFT 1 314*4882a593Smuzhiyun # define CG_VOLTAGE_EN (1 << 3) 315*4882a593Smuzhiyun # define FORCE (1 << 4) 316*4882a593Smuzhiyun # define PERIOD(x) ((x) << 8) 317*4882a593Smuzhiyun # define PERIOD_MASK (0xffff << 8) 318*4882a593Smuzhiyun # define PERIOD_SHIFT 8 319*4882a593Smuzhiyun # define UNIT(x) ((x) << 24) 320*4882a593Smuzhiyun # define UNIT_MASK (0xf << 24) 321*4882a593Smuzhiyun # define UNIT_SHIFT 24 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun #define CG_ACPI_VOLTAGE_CNTL 0x780 324*4882a593Smuzhiyun # define ACPI_VOLTAGE_EN (1 << 8) 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun #define CG_DPM_VOLTAGE_CNTL 0x788 327*4882a593Smuzhiyun # define DPM_STATE0_LEVEL_MASK (0x3 << 0) 328*4882a593Smuzhiyun # define DPM_STATE0_LEVEL_SHIFT 0 329*4882a593Smuzhiyun # define DPM_VOLTAGE_EN (1 << 16) 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun #define CG_PWR_GATING_CNTL 0x7ac 332*4882a593Smuzhiyun # define DYN_PWR_DOWN_EN (1 << 0) 333*4882a593Smuzhiyun # define ACPI_PWR_DOWN_EN (1 << 1) 334*4882a593Smuzhiyun # define GFX_CLK_OFF_PWR_DOWN_EN (1 << 2) 335*4882a593Smuzhiyun # define IOC_DISGPU_PWR_DOWN_EN (1 << 3) 336*4882a593Smuzhiyun # define FORCE_POWR_ON (1 << 4) 337*4882a593Smuzhiyun # define PGP(x) ((x) << 8) 338*4882a593Smuzhiyun # define PGP_MASK (0xffff << 8) 339*4882a593Smuzhiyun # define PGP_SHIFT 8 340*4882a593Smuzhiyun # define PGU(x) ((x) << 24) 341*4882a593Smuzhiyun # define PGU_MASK (0xf << 24) 342*4882a593Smuzhiyun # define PGU_SHIFT 24 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun #define CG_CGTT_LOCAL_0 0x7d0 345*4882a593Smuzhiyun #define CG_CGTT_LOCAL_1 0x7d4 346*4882a593Smuzhiyun 347*4882a593Smuzhiyun #define DEEP_SLEEP_CNTL 0x818 348*4882a593Smuzhiyun # define R_DIS (1 << 3) 349*4882a593Smuzhiyun # define HS(x) ((x) << 4) 350*4882a593Smuzhiyun # define HS_MASK (0xfff << 4) 351*4882a593Smuzhiyun # define HS_SHIFT 4 352*4882a593Smuzhiyun # define ENABLE_DS (1 << 31) 353*4882a593Smuzhiyun #define DEEP_SLEEP_CNTL2 0x81c 354*4882a593Smuzhiyun # define LB_UFP_EN (1 << 0) 355*4882a593Smuzhiyun # define INOUT_C(x) ((x) << 4) 356*4882a593Smuzhiyun # define INOUT_C_MASK (0xff << 4) 357*4882a593Smuzhiyun # define INOUT_C_SHIFT 4 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun #define CG_SCRATCH2 0x824 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun #define CG_SCLK_DPM_CTRL_11 0x830 362*4882a593Smuzhiyun 363*4882a593Smuzhiyun #define HW_REV 0x5564 364*4882a593Smuzhiyun # define ATI_REV_ID_MASK (0xf << 28) 365*4882a593Smuzhiyun # define ATI_REV_ID_SHIFT 28 366*4882a593Smuzhiyun /* 0 = A0, 1 = A1, 2 = B0, 3 = C0, etc. */ 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun #define DOUT_SCRATCH3 0x611c 369*4882a593Smuzhiyun 370*4882a593Smuzhiyun #define GB_ADDR_CONFIG 0x98f8 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun #endif 373