xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/si_reg.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright 2010 Advanced Micro Devices, Inc.
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Permission is hereby granted, free of charge, to any person obtaining a
5*4882a593Smuzhiyun  * copy of this software and associated documentation files (the "Software"),
6*4882a593Smuzhiyun  * to deal in the Software without restriction, including without limitation
7*4882a593Smuzhiyun  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*4882a593Smuzhiyun  * and/or sell copies of the Software, and to permit persons to whom the
9*4882a593Smuzhiyun  * Software is furnished to do so, subject to the following conditions:
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * The above copyright notice and this permission notice shall be included in
12*4882a593Smuzhiyun  * all copies or substantial portions of the Software.
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*4882a593Smuzhiyun  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17*4882a593Smuzhiyun  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*4882a593Smuzhiyun  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*4882a593Smuzhiyun  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*4882a593Smuzhiyun  * OTHER DEALINGS IN THE SOFTWARE.
21*4882a593Smuzhiyun  *
22*4882a593Smuzhiyun  * Authors: Alex Deucher
23*4882a593Smuzhiyun  */
24*4882a593Smuzhiyun #ifndef __SI_REG_H__
25*4882a593Smuzhiyun #define __SI_REG_H__
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun /* SI */
28*4882a593Smuzhiyun #define SI_DC_GPIO_HPD_MASK                      0x65b0
29*4882a593Smuzhiyun #define SI_DC_GPIO_HPD_A                         0x65b4
30*4882a593Smuzhiyun #define SI_DC_GPIO_HPD_EN                        0x65b8
31*4882a593Smuzhiyun #define SI_DC_GPIO_HPD_Y                         0x65bc
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #define SI_GRPH_CONTROL                          0x6804
34*4882a593Smuzhiyun #       define SI_GRPH_DEPTH(x)                  (((x) & 0x3) << 0)
35*4882a593Smuzhiyun #       define SI_GRPH_DEPTH_8BPP                0
36*4882a593Smuzhiyun #       define SI_GRPH_DEPTH_16BPP               1
37*4882a593Smuzhiyun #       define SI_GRPH_DEPTH_32BPP               2
38*4882a593Smuzhiyun #       define SI_GRPH_NUM_BANKS(x)              (((x) & 0x3) << 2)
39*4882a593Smuzhiyun #       define SI_ADDR_SURF_2_BANK               0
40*4882a593Smuzhiyun #       define SI_ADDR_SURF_4_BANK               1
41*4882a593Smuzhiyun #       define SI_ADDR_SURF_8_BANK               2
42*4882a593Smuzhiyun #       define SI_ADDR_SURF_16_BANK              3
43*4882a593Smuzhiyun #       define SI_GRPH_Z(x)                      (((x) & 0x3) << 4)
44*4882a593Smuzhiyun #       define SI_GRPH_BANK_WIDTH(x)             (((x) & 0x3) << 6)
45*4882a593Smuzhiyun #       define SI_ADDR_SURF_BANK_WIDTH_1         0
46*4882a593Smuzhiyun #       define SI_ADDR_SURF_BANK_WIDTH_2         1
47*4882a593Smuzhiyun #       define SI_ADDR_SURF_BANK_WIDTH_4         2
48*4882a593Smuzhiyun #       define SI_ADDR_SURF_BANK_WIDTH_8         3
49*4882a593Smuzhiyun #       define SI_GRPH_FORMAT(x)                 (((x) & 0x7) << 8)
50*4882a593Smuzhiyun /* 8 BPP */
51*4882a593Smuzhiyun #       define SI_GRPH_FORMAT_INDEXED            0
52*4882a593Smuzhiyun /* 16 BPP */
53*4882a593Smuzhiyun #       define SI_GRPH_FORMAT_ARGB1555           0
54*4882a593Smuzhiyun #       define SI_GRPH_FORMAT_ARGB565            1
55*4882a593Smuzhiyun #       define SI_GRPH_FORMAT_ARGB4444           2
56*4882a593Smuzhiyun #       define SI_GRPH_FORMAT_AI88               3
57*4882a593Smuzhiyun #       define SI_GRPH_FORMAT_MONO16             4
58*4882a593Smuzhiyun #       define SI_GRPH_FORMAT_BGRA5551           5
59*4882a593Smuzhiyun /* 32 BPP */
60*4882a593Smuzhiyun #       define SI_GRPH_FORMAT_ARGB8888           0
61*4882a593Smuzhiyun #       define SI_GRPH_FORMAT_ARGB2101010        1
62*4882a593Smuzhiyun #       define SI_GRPH_FORMAT_32BPP_DIG          2
63*4882a593Smuzhiyun #       define SI_GRPH_FORMAT_8B_ARGB2101010     3
64*4882a593Smuzhiyun #       define SI_GRPH_FORMAT_BGRA1010102        4
65*4882a593Smuzhiyun #       define SI_GRPH_FORMAT_8B_BGRA1010102     5
66*4882a593Smuzhiyun #       define SI_GRPH_FORMAT_RGB111110          6
67*4882a593Smuzhiyun #       define SI_GRPH_FORMAT_BGR101111          7
68*4882a593Smuzhiyun #       define SI_GRPH_BANK_HEIGHT(x)            (((x) & 0x3) << 11)
69*4882a593Smuzhiyun #       define SI_ADDR_SURF_BANK_HEIGHT_1        0
70*4882a593Smuzhiyun #       define SI_ADDR_SURF_BANK_HEIGHT_2        1
71*4882a593Smuzhiyun #       define SI_ADDR_SURF_BANK_HEIGHT_4        2
72*4882a593Smuzhiyun #       define SI_ADDR_SURF_BANK_HEIGHT_8        3
73*4882a593Smuzhiyun #       define SI_GRPH_TILE_SPLIT(x)             (((x) & 0x7) << 13)
74*4882a593Smuzhiyun #       define SI_ADDR_SURF_TILE_SPLIT_64B       0
75*4882a593Smuzhiyun #       define SI_ADDR_SURF_TILE_SPLIT_128B      1
76*4882a593Smuzhiyun #       define SI_ADDR_SURF_TILE_SPLIT_256B      2
77*4882a593Smuzhiyun #       define SI_ADDR_SURF_TILE_SPLIT_512B      3
78*4882a593Smuzhiyun #       define SI_ADDR_SURF_TILE_SPLIT_1KB       4
79*4882a593Smuzhiyun #       define SI_ADDR_SURF_TILE_SPLIT_2KB       5
80*4882a593Smuzhiyun #       define SI_ADDR_SURF_TILE_SPLIT_4KB       6
81*4882a593Smuzhiyun #       define SI_GRPH_MACRO_TILE_ASPECT(x)      (((x) & 0x3) << 18)
82*4882a593Smuzhiyun #       define SI_ADDR_SURF_MACRO_TILE_ASPECT_1  0
83*4882a593Smuzhiyun #       define SI_ADDR_SURF_MACRO_TILE_ASPECT_2  1
84*4882a593Smuzhiyun #       define SI_ADDR_SURF_MACRO_TILE_ASPECT_4  2
85*4882a593Smuzhiyun #       define SI_ADDR_SURF_MACRO_TILE_ASPECT_8  3
86*4882a593Smuzhiyun #       define SI_GRPH_ARRAY_MODE(x)             (((x) & 0x7) << 20)
87*4882a593Smuzhiyun #       define SI_GRPH_ARRAY_LINEAR_GENERAL      0
88*4882a593Smuzhiyun #       define SI_GRPH_ARRAY_LINEAR_ALIGNED      1
89*4882a593Smuzhiyun #       define SI_GRPH_ARRAY_1D_TILED_THIN1      2
90*4882a593Smuzhiyun #       define SI_GRPH_ARRAY_2D_TILED_THIN1      4
91*4882a593Smuzhiyun #       define SI_GRPH_PIPE_CONFIG(x)		 (((x) & 0x1f) << 24)
92*4882a593Smuzhiyun #       define SI_ADDR_SURF_P2			 0
93*4882a593Smuzhiyun #       define SI_ADDR_SURF_P4_8x16		 4
94*4882a593Smuzhiyun #       define SI_ADDR_SURF_P4_16x16		 5
95*4882a593Smuzhiyun #       define SI_ADDR_SURF_P4_16x32		 6
96*4882a593Smuzhiyun #       define SI_ADDR_SURF_P4_32x32		 7
97*4882a593Smuzhiyun #       define SI_ADDR_SURF_P8_16x16_8x16	 8
98*4882a593Smuzhiyun #       define SI_ADDR_SURF_P8_16x32_8x16	 9
99*4882a593Smuzhiyun #       define SI_ADDR_SURF_P8_32x32_8x16	 10
100*4882a593Smuzhiyun #       define SI_ADDR_SURF_P8_16x32_16x16	 11
101*4882a593Smuzhiyun #       define SI_ADDR_SURF_P8_32x32_16x16	 12
102*4882a593Smuzhiyun #       define SI_ADDR_SURF_P8_32x32_16x32	 13
103*4882a593Smuzhiyun #       define SI_ADDR_SURF_P8_32x64_32x32	 14
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun #endif
106