1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2011 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun #ifndef __RV770_DPM_H__ 24*4882a593Smuzhiyun #define __RV770_DPM_H__ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #include "radeon.h" 27*4882a593Smuzhiyun #include "rv770_smc.h" 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun struct rv770_clock_registers { 30*4882a593Smuzhiyun u32 cg_spll_func_cntl; 31*4882a593Smuzhiyun u32 cg_spll_func_cntl_2; 32*4882a593Smuzhiyun u32 cg_spll_func_cntl_3; 33*4882a593Smuzhiyun u32 cg_spll_spread_spectrum; 34*4882a593Smuzhiyun u32 cg_spll_spread_spectrum_2; 35*4882a593Smuzhiyun u32 mpll_ad_func_cntl; 36*4882a593Smuzhiyun u32 mpll_ad_func_cntl_2; 37*4882a593Smuzhiyun u32 mpll_dq_func_cntl; 38*4882a593Smuzhiyun u32 mpll_dq_func_cntl_2; 39*4882a593Smuzhiyun u32 mclk_pwrmgt_cntl; 40*4882a593Smuzhiyun u32 dll_cntl; 41*4882a593Smuzhiyun u32 mpll_ss1; 42*4882a593Smuzhiyun u32 mpll_ss2; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun struct rv730_clock_registers { 46*4882a593Smuzhiyun u32 cg_spll_func_cntl; 47*4882a593Smuzhiyun u32 cg_spll_func_cntl_2; 48*4882a593Smuzhiyun u32 cg_spll_func_cntl_3; 49*4882a593Smuzhiyun u32 cg_spll_spread_spectrum; 50*4882a593Smuzhiyun u32 cg_spll_spread_spectrum_2; 51*4882a593Smuzhiyun u32 mclk_pwrmgt_cntl; 52*4882a593Smuzhiyun u32 dll_cntl; 53*4882a593Smuzhiyun u32 mpll_func_cntl; 54*4882a593Smuzhiyun u32 mpll_func_cntl2; 55*4882a593Smuzhiyun u32 mpll_func_cntl3; 56*4882a593Smuzhiyun u32 mpll_ss; 57*4882a593Smuzhiyun u32 mpll_ss2; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun union r7xx_clock_registers { 61*4882a593Smuzhiyun struct rv770_clock_registers rv770; 62*4882a593Smuzhiyun struct rv730_clock_registers rv730; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun struct vddc_table_entry { 66*4882a593Smuzhiyun u16 vddc; 67*4882a593Smuzhiyun u8 vddc_index; 68*4882a593Smuzhiyun u8 high_smio; 69*4882a593Smuzhiyun u32 low_smio; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define MAX_NO_OF_MVDD_VALUES 2 73*4882a593Smuzhiyun #define MAX_NO_VREG_STEPS 32 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun struct rv7xx_power_info { 76*4882a593Smuzhiyun /* flags */ 77*4882a593Smuzhiyun bool mem_gddr5; 78*4882a593Smuzhiyun bool pcie_gen2; 79*4882a593Smuzhiyun bool dynamic_pcie_gen2; 80*4882a593Smuzhiyun bool acpi_pcie_gen2; 81*4882a593Smuzhiyun bool boot_in_gen2; 82*4882a593Smuzhiyun bool voltage_control; /* vddc */ 83*4882a593Smuzhiyun bool mvdd_control; 84*4882a593Smuzhiyun bool sclk_ss; 85*4882a593Smuzhiyun bool mclk_ss; 86*4882a593Smuzhiyun bool dynamic_ss; 87*4882a593Smuzhiyun bool gfx_clock_gating; 88*4882a593Smuzhiyun bool mg_clock_gating; 89*4882a593Smuzhiyun bool mgcgtssm; 90*4882a593Smuzhiyun bool power_gating; 91*4882a593Smuzhiyun bool thermal_protection; 92*4882a593Smuzhiyun bool display_gap; 93*4882a593Smuzhiyun bool dcodt; 94*4882a593Smuzhiyun bool ulps; 95*4882a593Smuzhiyun /* registers */ 96*4882a593Smuzhiyun union r7xx_clock_registers clk_regs; 97*4882a593Smuzhiyun u32 s0_vid_lower_smio_cntl; 98*4882a593Smuzhiyun /* voltage */ 99*4882a593Smuzhiyun u32 vddc_mask_low; 100*4882a593Smuzhiyun u32 mvdd_mask_low; 101*4882a593Smuzhiyun u32 mvdd_split_frequency; 102*4882a593Smuzhiyun u32 mvdd_low_smio[MAX_NO_OF_MVDD_VALUES]; 103*4882a593Smuzhiyun u16 max_vddc; 104*4882a593Smuzhiyun u16 max_vddc_in_table; 105*4882a593Smuzhiyun u16 min_vddc_in_table; 106*4882a593Smuzhiyun struct vddc_table_entry vddc_table[MAX_NO_VREG_STEPS]; 107*4882a593Smuzhiyun u8 valid_vddc_entries; 108*4882a593Smuzhiyun /* dc odt */ 109*4882a593Smuzhiyun u32 mclk_odt_threshold; 110*4882a593Smuzhiyun u8 odt_value_0[2]; 111*4882a593Smuzhiyun u8 odt_value_1[2]; 112*4882a593Smuzhiyun /* stored values */ 113*4882a593Smuzhiyun u32 boot_sclk; 114*4882a593Smuzhiyun u16 acpi_vddc; 115*4882a593Smuzhiyun u32 ref_div; 116*4882a593Smuzhiyun u32 active_auto_throttle_sources; 117*4882a593Smuzhiyun u32 mclk_stutter_mode_threshold; 118*4882a593Smuzhiyun u32 mclk_strobe_mode_threshold; 119*4882a593Smuzhiyun u32 mclk_edc_enable_threshold; 120*4882a593Smuzhiyun u32 bsp; 121*4882a593Smuzhiyun u32 bsu; 122*4882a593Smuzhiyun u32 pbsp; 123*4882a593Smuzhiyun u32 pbsu; 124*4882a593Smuzhiyun u32 dsp; 125*4882a593Smuzhiyun u32 psp; 126*4882a593Smuzhiyun u32 asi; 127*4882a593Smuzhiyun u32 pasi; 128*4882a593Smuzhiyun u32 vrc; 129*4882a593Smuzhiyun u32 restricted_levels; 130*4882a593Smuzhiyun u32 rlp; 131*4882a593Smuzhiyun u32 rmp; 132*4882a593Smuzhiyun u32 lhp; 133*4882a593Smuzhiyun u32 lmp; 134*4882a593Smuzhiyun /* smc offsets */ 135*4882a593Smuzhiyun u16 state_table_start; 136*4882a593Smuzhiyun u16 soft_regs_start; 137*4882a593Smuzhiyun u16 sram_end; 138*4882a593Smuzhiyun /* scratch structs */ 139*4882a593Smuzhiyun RV770_SMC_STATETABLE smc_statetable; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun struct rv7xx_pl { 143*4882a593Smuzhiyun u32 sclk; 144*4882a593Smuzhiyun u32 mclk; 145*4882a593Smuzhiyun u16 vddc; 146*4882a593Smuzhiyun u16 vddci; /* eg+ only */ 147*4882a593Smuzhiyun u32 flags; 148*4882a593Smuzhiyun enum radeon_pcie_gen pcie_gen; /* si+ only */ 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun struct rv7xx_ps { 152*4882a593Smuzhiyun struct rv7xx_pl high; 153*4882a593Smuzhiyun struct rv7xx_pl medium; 154*4882a593Smuzhiyun struct rv7xx_pl low; 155*4882a593Smuzhiyun bool dc_compatible; 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun #define RV770_RLP_DFLT 10 159*4882a593Smuzhiyun #define RV770_RMP_DFLT 25 160*4882a593Smuzhiyun #define RV770_LHP_DFLT 25 161*4882a593Smuzhiyun #define RV770_LMP_DFLT 10 162*4882a593Smuzhiyun #define RV770_VRC_DFLT 0x003f 163*4882a593Smuzhiyun #define RV770_ASI_DFLT 1000 164*4882a593Smuzhiyun #define RV770_HASI_DFLT 200000 165*4882a593Smuzhiyun #define RV770_MGCGTTLOCAL0_DFLT 0x00100000 166*4882a593Smuzhiyun #define RV7XX_MGCGTTLOCAL0_DFLT 0 167*4882a593Smuzhiyun #define RV770_MGCGTTLOCAL1_DFLT 0xFFFF0000 168*4882a593Smuzhiyun #define RV770_MGCGCGTSSMCTRL_DFLT 0x55940000 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun #define MVDD_LOW_INDEX 0 171*4882a593Smuzhiyun #define MVDD_HIGH_INDEX 1 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun #define MVDD_LOW_VALUE 0 174*4882a593Smuzhiyun #define MVDD_HIGH_VALUE 0xffff 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun #define RV770_DEFAULT_VCLK_FREQ 53300 /* 10 khz */ 177*4882a593Smuzhiyun #define RV770_DEFAULT_DCLK_FREQ 40000 /* 10 khz */ 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun /* rv730/rv710 */ 180*4882a593Smuzhiyun int rv730_populate_sclk_value(struct radeon_device *rdev, 181*4882a593Smuzhiyun u32 engine_clock, 182*4882a593Smuzhiyun RV770_SMC_SCLK_VALUE *sclk); 183*4882a593Smuzhiyun int rv730_populate_mclk_value(struct radeon_device *rdev, 184*4882a593Smuzhiyun u32 engine_clock, u32 memory_clock, 185*4882a593Smuzhiyun LPRV7XX_SMC_MCLK_VALUE mclk); 186*4882a593Smuzhiyun void rv730_read_clock_registers(struct radeon_device *rdev); 187*4882a593Smuzhiyun int rv730_populate_smc_acpi_state(struct radeon_device *rdev, 188*4882a593Smuzhiyun RV770_SMC_STATETABLE *table); 189*4882a593Smuzhiyun int rv730_populate_smc_initial_state(struct radeon_device *rdev, 190*4882a593Smuzhiyun struct radeon_ps *radeon_initial_state, 191*4882a593Smuzhiyun RV770_SMC_STATETABLE *table); 192*4882a593Smuzhiyun void rv730_program_memory_timing_parameters(struct radeon_device *rdev, 193*4882a593Smuzhiyun struct radeon_ps *radeon_state); 194*4882a593Smuzhiyun void rv730_power_gating_enable(struct radeon_device *rdev, 195*4882a593Smuzhiyun bool enable); 196*4882a593Smuzhiyun void rv730_start_dpm(struct radeon_device *rdev); 197*4882a593Smuzhiyun void rv730_stop_dpm(struct radeon_device *rdev); 198*4882a593Smuzhiyun void rv730_program_dcodt(struct radeon_device *rdev, bool use_dcodt); 199*4882a593Smuzhiyun void rv730_get_odt_values(struct radeon_device *rdev); 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun /* rv740 */ 202*4882a593Smuzhiyun int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, 203*4882a593Smuzhiyun RV770_SMC_SCLK_VALUE *sclk); 204*4882a593Smuzhiyun int rv740_populate_mclk_value(struct radeon_device *rdev, 205*4882a593Smuzhiyun u32 engine_clock, u32 memory_clock, 206*4882a593Smuzhiyun RV7XX_SMC_MCLK_VALUE *mclk); 207*4882a593Smuzhiyun void rv740_read_clock_registers(struct radeon_device *rdev); 208*4882a593Smuzhiyun int rv740_populate_smc_acpi_state(struct radeon_device *rdev, 209*4882a593Smuzhiyun RV770_SMC_STATETABLE *table); 210*4882a593Smuzhiyun void rv740_enable_mclk_spread_spectrum(struct radeon_device *rdev, 211*4882a593Smuzhiyun bool enable); 212*4882a593Smuzhiyun u8 rv740_get_mclk_frequency_ratio(u32 memory_clock); 213*4882a593Smuzhiyun u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock); 214*4882a593Smuzhiyun u32 rv740_get_decoded_reference_divider(u32 encoded_ref); 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun /* rv770 */ 217*4882a593Smuzhiyun u32 rv770_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf); 218*4882a593Smuzhiyun int rv770_populate_vddc_value(struct radeon_device *rdev, u16 vddc, 219*4882a593Smuzhiyun RV770_SMC_VOLTAGE_VALUE *voltage); 220*4882a593Smuzhiyun int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 221*4882a593Smuzhiyun RV770_SMC_VOLTAGE_VALUE *voltage); 222*4882a593Smuzhiyun u8 rv770_get_seq_value(struct radeon_device *rdev, 223*4882a593Smuzhiyun struct rv7xx_pl *pl); 224*4882a593Smuzhiyun int rv770_populate_initial_mvdd_value(struct radeon_device *rdev, 225*4882a593Smuzhiyun RV770_SMC_VOLTAGE_VALUE *voltage); 226*4882a593Smuzhiyun u32 rv770_calculate_memory_refresh_rate(struct radeon_device *rdev, 227*4882a593Smuzhiyun u32 engine_clock); 228*4882a593Smuzhiyun void rv770_program_response_times(struct radeon_device *rdev); 229*4882a593Smuzhiyun int rv770_populate_smc_sp(struct radeon_device *rdev, 230*4882a593Smuzhiyun struct radeon_ps *radeon_state, 231*4882a593Smuzhiyun RV770_SMC_SWSTATE *smc_state); 232*4882a593Smuzhiyun int rv770_populate_smc_t(struct radeon_device *rdev, 233*4882a593Smuzhiyun struct radeon_ps *radeon_state, 234*4882a593Smuzhiyun RV770_SMC_SWSTATE *smc_state); 235*4882a593Smuzhiyun void rv770_read_voltage_smio_registers(struct radeon_device *rdev); 236*4882a593Smuzhiyun void rv770_get_memory_type(struct radeon_device *rdev); 237*4882a593Smuzhiyun void r7xx_start_smc(struct radeon_device *rdev); 238*4882a593Smuzhiyun u8 rv770_get_memory_module_index(struct radeon_device *rdev); 239*4882a593Smuzhiyun void rv770_get_max_vddc(struct radeon_device *rdev); 240*4882a593Smuzhiyun void rv770_get_pcie_gen2_status(struct radeon_device *rdev); 241*4882a593Smuzhiyun void rv770_enable_acpi_pm(struct radeon_device *rdev); 242*4882a593Smuzhiyun void rv770_restore_cgcg(struct radeon_device *rdev); 243*4882a593Smuzhiyun bool rv770_dpm_enabled(struct radeon_device *rdev); 244*4882a593Smuzhiyun void rv770_enable_voltage_control(struct radeon_device *rdev, 245*4882a593Smuzhiyun bool enable); 246*4882a593Smuzhiyun void rv770_enable_backbias(struct radeon_device *rdev, 247*4882a593Smuzhiyun bool enable); 248*4882a593Smuzhiyun void rv770_enable_thermal_protection(struct radeon_device *rdev, 249*4882a593Smuzhiyun bool enable); 250*4882a593Smuzhiyun void rv770_enable_auto_throttle_source(struct radeon_device *rdev, 251*4882a593Smuzhiyun enum radeon_dpm_auto_throttle_src source, 252*4882a593Smuzhiyun bool enable); 253*4882a593Smuzhiyun void rv770_setup_bsp(struct radeon_device *rdev); 254*4882a593Smuzhiyun void rv770_program_git(struct radeon_device *rdev); 255*4882a593Smuzhiyun void rv770_program_tp(struct radeon_device *rdev); 256*4882a593Smuzhiyun void rv770_program_tpp(struct radeon_device *rdev); 257*4882a593Smuzhiyun void rv770_program_sstp(struct radeon_device *rdev); 258*4882a593Smuzhiyun void rv770_program_engine_speed_parameters(struct radeon_device *rdev); 259*4882a593Smuzhiyun void rv770_program_vc(struct radeon_device *rdev); 260*4882a593Smuzhiyun void rv770_clear_vc(struct radeon_device *rdev); 261*4882a593Smuzhiyun int rv770_upload_firmware(struct radeon_device *rdev); 262*4882a593Smuzhiyun void rv770_stop_dpm(struct radeon_device *rdev); 263*4882a593Smuzhiyun void r7xx_stop_smc(struct radeon_device *rdev); 264*4882a593Smuzhiyun void rv770_reset_smio_status(struct radeon_device *rdev); 265*4882a593Smuzhiyun int rv770_restrict_performance_levels_before_switch(struct radeon_device *rdev); 266*4882a593Smuzhiyun int rv770_dpm_force_performance_level(struct radeon_device *rdev, 267*4882a593Smuzhiyun enum radeon_dpm_forced_level level); 268*4882a593Smuzhiyun int rv770_halt_smc(struct radeon_device *rdev); 269*4882a593Smuzhiyun int rv770_resume_smc(struct radeon_device *rdev); 270*4882a593Smuzhiyun int rv770_set_sw_state(struct radeon_device *rdev); 271*4882a593Smuzhiyun int rv770_set_boot_state(struct radeon_device *rdev); 272*4882a593Smuzhiyun int rv7xx_parse_power_table(struct radeon_device *rdev); 273*4882a593Smuzhiyun void rv770_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev, 274*4882a593Smuzhiyun struct radeon_ps *new_ps, 275*4882a593Smuzhiyun struct radeon_ps *old_ps); 276*4882a593Smuzhiyun void rv770_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev, 277*4882a593Smuzhiyun struct radeon_ps *new_ps, 278*4882a593Smuzhiyun struct radeon_ps *old_ps); 279*4882a593Smuzhiyun void rv770_get_engine_memory_ss(struct radeon_device *rdev); 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun /* smc */ 282*4882a593Smuzhiyun int rv770_write_smc_soft_register(struct radeon_device *rdev, 283*4882a593Smuzhiyun u16 reg_offset, u32 value); 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun #endif 286