1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2013 Advanced Micro Devices, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a
5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"),
6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation
7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the
9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions:
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in
12*4882a593Smuzhiyun * all copies or substantial portions of the Software.
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE.
21*4882a593Smuzhiyun *
22*4882a593Smuzhiyun * Authors: Alex Deucher
23*4882a593Smuzhiyun */
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #include "radeon.h"
26*4882a593Smuzhiyun #include "radeon_asic.h"
27*4882a593Smuzhiyun #include "rv770d.h"
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /**
30*4882a593Smuzhiyun * rv770_copy_dma - copy pages using the DMA engine
31*4882a593Smuzhiyun *
32*4882a593Smuzhiyun * @rdev: radeon_device pointer
33*4882a593Smuzhiyun * @src_offset: src GPU address
34*4882a593Smuzhiyun * @dst_offset: dst GPU address
35*4882a593Smuzhiyun * @num_gpu_pages: number of GPU pages to xfer
36*4882a593Smuzhiyun * @resv: reservation object to sync to
37*4882a593Smuzhiyun *
38*4882a593Smuzhiyun * Copy GPU paging using the DMA engine (r7xx).
39*4882a593Smuzhiyun * Used by the radeon ttm implementation to move pages if
40*4882a593Smuzhiyun * registered as the asic copy callback.
41*4882a593Smuzhiyun */
rv770_copy_dma(struct radeon_device * rdev,uint64_t src_offset,uint64_t dst_offset,unsigned num_gpu_pages,struct dma_resv * resv)42*4882a593Smuzhiyun struct radeon_fence *rv770_copy_dma(struct radeon_device *rdev,
43*4882a593Smuzhiyun uint64_t src_offset, uint64_t dst_offset,
44*4882a593Smuzhiyun unsigned num_gpu_pages,
45*4882a593Smuzhiyun struct dma_resv *resv)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun struct radeon_fence *fence;
48*4882a593Smuzhiyun struct radeon_sync sync;
49*4882a593Smuzhiyun int ring_index = rdev->asic->copy.dma_ring_index;
50*4882a593Smuzhiyun struct radeon_ring *ring = &rdev->ring[ring_index];
51*4882a593Smuzhiyun u32 size_in_dw, cur_size_in_dw;
52*4882a593Smuzhiyun int i, num_loops;
53*4882a593Smuzhiyun int r = 0;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun radeon_sync_create(&sync);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
58*4882a593Smuzhiyun num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFF);
59*4882a593Smuzhiyun r = radeon_ring_lock(rdev, ring, num_loops * 5 + 8);
60*4882a593Smuzhiyun if (r) {
61*4882a593Smuzhiyun DRM_ERROR("radeon: moving bo (%d).\n", r);
62*4882a593Smuzhiyun radeon_sync_free(rdev, &sync, NULL);
63*4882a593Smuzhiyun return ERR_PTR(r);
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun radeon_sync_resv(rdev, &sync, resv, false);
67*4882a593Smuzhiyun radeon_sync_rings(rdev, &sync, ring->idx);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun for (i = 0; i < num_loops; i++) {
70*4882a593Smuzhiyun cur_size_in_dw = size_in_dw;
71*4882a593Smuzhiyun if (cur_size_in_dw > 0xFFFF)
72*4882a593Smuzhiyun cur_size_in_dw = 0xFFFF;
73*4882a593Smuzhiyun size_in_dw -= cur_size_in_dw;
74*4882a593Smuzhiyun radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
75*4882a593Smuzhiyun radeon_ring_write(ring, dst_offset & 0xfffffffc);
76*4882a593Smuzhiyun radeon_ring_write(ring, src_offset & 0xfffffffc);
77*4882a593Smuzhiyun radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
78*4882a593Smuzhiyun radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
79*4882a593Smuzhiyun src_offset += cur_size_in_dw * 4;
80*4882a593Smuzhiyun dst_offset += cur_size_in_dw * 4;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun r = radeon_fence_emit(rdev, &fence, ring->idx);
84*4882a593Smuzhiyun if (r) {
85*4882a593Smuzhiyun radeon_ring_unlock_undo(rdev, ring);
86*4882a593Smuzhiyun radeon_sync_free(rdev, &sync, NULL);
87*4882a593Smuzhiyun return ERR_PTR(r);
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun radeon_ring_unlock_commit(rdev, ring, false);
91*4882a593Smuzhiyun radeon_sync_free(rdev, &sync, fence);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun return fence;
94*4882a593Smuzhiyun }
95