1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2011 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun #ifndef RV6XXD_H 24*4882a593Smuzhiyun #define RV6XXD_H 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* RV6xx power management */ 27*4882a593Smuzhiyun #define SPLL_CNTL_MODE 0x60c 28*4882a593Smuzhiyun # define SPLL_DIV_SYNC (1 << 5) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define GENERAL_PWRMGT 0x618 31*4882a593Smuzhiyun # define GLOBAL_PWRMGT_EN (1 << 0) 32*4882a593Smuzhiyun # define STATIC_PM_EN (1 << 1) 33*4882a593Smuzhiyun # define MOBILE_SU (1 << 2) 34*4882a593Smuzhiyun # define THERMAL_PROTECTION_DIS (1 << 3) 35*4882a593Smuzhiyun # define THERMAL_PROTECTION_TYPE (1 << 4) 36*4882a593Smuzhiyun # define ENABLE_GEN2PCIE (1 << 5) 37*4882a593Smuzhiyun # define SW_GPIO_INDEX(x) ((x) << 6) 38*4882a593Smuzhiyun # define SW_GPIO_INDEX_MASK (3 << 6) 39*4882a593Smuzhiyun # define LOW_VOLT_D2_ACPI (1 << 8) 40*4882a593Smuzhiyun # define LOW_VOLT_D3_ACPI (1 << 9) 41*4882a593Smuzhiyun # define VOLT_PWRMGT_EN (1 << 10) 42*4882a593Smuzhiyun # define BACKBIAS_PAD_EN (1 << 16) 43*4882a593Smuzhiyun # define BACKBIAS_VALUE (1 << 17) 44*4882a593Smuzhiyun # define BACKBIAS_DPM_CNTL (1 << 18) 45*4882a593Smuzhiyun # define DYN_SPREAD_SPECTRUM_EN (1 << 21) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define MCLK_PWRMGT_CNTL 0x624 48*4882a593Smuzhiyun # define MPLL_PWRMGT_OFF (1 << 0) 49*4882a593Smuzhiyun # define YCLK_TURNOFF (1 << 1) 50*4882a593Smuzhiyun # define MPLL_TURNOFF (1 << 2) 51*4882a593Smuzhiyun # define SU_MCLK_USE_BCLK (1 << 3) 52*4882a593Smuzhiyun # define DLL_READY (1 << 4) 53*4882a593Smuzhiyun # define MC_BUSY (1 << 5) 54*4882a593Smuzhiyun # define MC_INT_CNTL (1 << 7) 55*4882a593Smuzhiyun # define MRDCKA_SLEEP (1 << 8) 56*4882a593Smuzhiyun # define MRDCKB_SLEEP (1 << 9) 57*4882a593Smuzhiyun # define MRDCKC_SLEEP (1 << 10) 58*4882a593Smuzhiyun # define MRDCKD_SLEEP (1 << 11) 59*4882a593Smuzhiyun # define MRDCKE_SLEEP (1 << 12) 60*4882a593Smuzhiyun # define MRDCKF_SLEEP (1 << 13) 61*4882a593Smuzhiyun # define MRDCKG_SLEEP (1 << 14) 62*4882a593Smuzhiyun # define MRDCKH_SLEEP (1 << 15) 63*4882a593Smuzhiyun # define MRDCKA_RESET (1 << 16) 64*4882a593Smuzhiyun # define MRDCKB_RESET (1 << 17) 65*4882a593Smuzhiyun # define MRDCKC_RESET (1 << 18) 66*4882a593Smuzhiyun # define MRDCKD_RESET (1 << 19) 67*4882a593Smuzhiyun # define MRDCKE_RESET (1 << 20) 68*4882a593Smuzhiyun # define MRDCKF_RESET (1 << 21) 69*4882a593Smuzhiyun # define MRDCKG_RESET (1 << 22) 70*4882a593Smuzhiyun # define MRDCKH_RESET (1 << 23) 71*4882a593Smuzhiyun # define DLL_READY_READ (1 << 24) 72*4882a593Smuzhiyun # define USE_DISPLAY_GAP (1 << 25) 73*4882a593Smuzhiyun # define USE_DISPLAY_URGENT_NORMAL (1 << 26) 74*4882a593Smuzhiyun # define USE_DISPLAY_GAP_CTXSW (1 << 27) 75*4882a593Smuzhiyun # define MPLL_TURNOFF_D2 (1 << 28) 76*4882a593Smuzhiyun # define USE_DISPLAY_URGENT_CTXSW (1 << 29) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define MPLL_FREQ_LEVEL_0 0x6e8 79*4882a593Smuzhiyun # define LEVEL0_MPLL_POST_DIV(x) ((x) << 0) 80*4882a593Smuzhiyun # define LEVEL0_MPLL_POST_DIV_MASK (0xff << 0) 81*4882a593Smuzhiyun # define LEVEL0_MPLL_FB_DIV(x) ((x) << 8) 82*4882a593Smuzhiyun # define LEVEL0_MPLL_FB_DIV_MASK (0xfff << 8) 83*4882a593Smuzhiyun # define LEVEL0_MPLL_REF_DIV(x) ((x) << 20) 84*4882a593Smuzhiyun # define LEVEL0_MPLL_REF_DIV_MASK (0x3f << 20) 85*4882a593Smuzhiyun # define LEVEL0_MPLL_DIV_EN (1 << 28) 86*4882a593Smuzhiyun # define LEVEL0_DLL_BYPASS (1 << 29) 87*4882a593Smuzhiyun # define LEVEL0_DLL_RESET (1 << 30) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define VID_RT 0x6f8 90*4882a593Smuzhiyun # define VID_CRT(x) ((x) << 0) 91*4882a593Smuzhiyun # define VID_CRT_MASK (0x1fff << 0) 92*4882a593Smuzhiyun # define VID_CRTU(x) ((x) << 13) 93*4882a593Smuzhiyun # define VID_CRTU_MASK (7 << 13) 94*4882a593Smuzhiyun # define SSTU(x) ((x) << 16) 95*4882a593Smuzhiyun # define SSTU_MASK (7 << 16) 96*4882a593Smuzhiyun # define VID_SWT(x) ((x) << 19) 97*4882a593Smuzhiyun # define VID_SWT_MASK (0x1f << 19) 98*4882a593Smuzhiyun # define BRT(x) ((x) << 24) 99*4882a593Smuzhiyun # define BRT_MASK (0xff << 24) 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define TARGET_AND_CURRENT_PROFILE_INDEX 0x70c 102*4882a593Smuzhiyun # define TARGET_PROFILE_INDEX_MASK (3 << 0) 103*4882a593Smuzhiyun # define TARGET_PROFILE_INDEX_SHIFT 0 104*4882a593Smuzhiyun # define CURRENT_PROFILE_INDEX_MASK (3 << 2) 105*4882a593Smuzhiyun # define CURRENT_PROFILE_INDEX_SHIFT 2 106*4882a593Smuzhiyun # define DYN_PWR_ENTER_INDEX(x) ((x) << 4) 107*4882a593Smuzhiyun # define DYN_PWR_ENTER_INDEX_MASK (3 << 4) 108*4882a593Smuzhiyun # define DYN_PWR_ENTER_INDEX_SHIFT 4 109*4882a593Smuzhiyun # define CURR_MCLK_INDEX_MASK (3 << 6) 110*4882a593Smuzhiyun # define CURR_MCLK_INDEX_SHIFT 6 111*4882a593Smuzhiyun # define CURR_SCLK_INDEX_MASK (0x1f << 8) 112*4882a593Smuzhiyun # define CURR_SCLK_INDEX_SHIFT 8 113*4882a593Smuzhiyun # define CURR_VID_INDEX_MASK (3 << 13) 114*4882a593Smuzhiyun # define CURR_VID_INDEX_SHIFT 13 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #define VID_UPPER_GPIO_CNTL 0x740 117*4882a593Smuzhiyun # define CTXSW_UPPER_GPIO_VALUES(x) ((x) << 0) 118*4882a593Smuzhiyun # define CTXSW_UPPER_GPIO_VALUES_MASK (7 << 0) 119*4882a593Smuzhiyun # define HIGH_UPPER_GPIO_VALUES(x) ((x) << 3) 120*4882a593Smuzhiyun # define HIGH_UPPER_GPIO_VALUES_MASK (7 << 3) 121*4882a593Smuzhiyun # define MEDIUM_UPPER_GPIO_VALUES(x) ((x) << 6) 122*4882a593Smuzhiyun # define MEDIUM_UPPER_GPIO_VALUES_MASK (7 << 6) 123*4882a593Smuzhiyun # define LOW_UPPER_GPIO_VALUES(x) ((x) << 9) 124*4882a593Smuzhiyun # define LOW_UPPER_GPIO_VALUES_MASK (7 << 9) 125*4882a593Smuzhiyun # define CTXSW_BACKBIAS_VALUE (1 << 12) 126*4882a593Smuzhiyun # define HIGH_BACKBIAS_VALUE (1 << 13) 127*4882a593Smuzhiyun # define MEDIUM_BACKBIAS_VALUE (1 << 14) 128*4882a593Smuzhiyun # define LOW_BACKBIAS_VALUE (1 << 15) 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #define CG_DISPLAY_GAP_CNTL 0x7dc 131*4882a593Smuzhiyun # define DISP1_GAP(x) ((x) << 0) 132*4882a593Smuzhiyun # define DISP1_GAP_MASK (3 << 0) 133*4882a593Smuzhiyun # define DISP2_GAP(x) ((x) << 2) 134*4882a593Smuzhiyun # define DISP2_GAP_MASK (3 << 2) 135*4882a593Smuzhiyun # define VBI_TIMER_COUNT(x) ((x) << 4) 136*4882a593Smuzhiyun # define VBI_TIMER_COUNT_MASK (0x3fff << 4) 137*4882a593Smuzhiyun # define VBI_TIMER_UNIT(x) ((x) << 20) 138*4882a593Smuzhiyun # define VBI_TIMER_UNIT_MASK (7 << 20) 139*4882a593Smuzhiyun # define DISP1_GAP_MCHG(x) ((x) << 24) 140*4882a593Smuzhiyun # define DISP1_GAP_MCHG_MASK (3 << 24) 141*4882a593Smuzhiyun # define DISP2_GAP_MCHG(x) ((x) << 26) 142*4882a593Smuzhiyun # define DISP2_GAP_MCHG_MASK (3 << 26) 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun #define CG_THERMAL_CTRL 0x7f0 145*4882a593Smuzhiyun # define DPM_EVENT_SRC(x) ((x) << 0) 146*4882a593Smuzhiyun # define DPM_EVENT_SRC_MASK (7 << 0) 147*4882a593Smuzhiyun # define THERM_INC_CLK (1 << 3) 148*4882a593Smuzhiyun # define TOFFSET(x) ((x) << 4) 149*4882a593Smuzhiyun # define TOFFSET_MASK (0xff << 4) 150*4882a593Smuzhiyun # define DIG_THERM_DPM(x) ((x) << 12) 151*4882a593Smuzhiyun # define DIG_THERM_DPM_MASK (0xff << 12) 152*4882a593Smuzhiyun # define CTF_SEL(x) ((x) << 20) 153*4882a593Smuzhiyun # define CTF_SEL_MASK (7 << 20) 154*4882a593Smuzhiyun # define CTF_PAD_POLARITY (1 << 23) 155*4882a593Smuzhiyun # define CTF_PAD_EN (1 << 24) 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun #define CG_SPLL_SPREAD_SPECTRUM_LOW 0x820 158*4882a593Smuzhiyun # define SSEN (1 << 0) 159*4882a593Smuzhiyun # define CLKS(x) ((x) << 3) 160*4882a593Smuzhiyun # define CLKS_MASK (0xff << 3) 161*4882a593Smuzhiyun # define CLKS_SHIFT 3 162*4882a593Smuzhiyun # define CLKV(x) ((x) << 11) 163*4882a593Smuzhiyun # define CLKV_MASK (0x7ff << 11) 164*4882a593Smuzhiyun # define CLKV_SHIFT 11 165*4882a593Smuzhiyun #define CG_MPLL_SPREAD_SPECTRUM 0x830 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun #define CITF_CNTL 0x200c 168*4882a593Smuzhiyun # define BLACKOUT_RD (1 << 0) 169*4882a593Smuzhiyun # define BLACKOUT_WR (1 << 1) 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun #define RAMCFG 0x2408 172*4882a593Smuzhiyun #define NOOFBANK_SHIFT 0 173*4882a593Smuzhiyun #define NOOFBANK_MASK 0x00000001 174*4882a593Smuzhiyun #define NOOFRANK_SHIFT 1 175*4882a593Smuzhiyun #define NOOFRANK_MASK 0x00000002 176*4882a593Smuzhiyun #define NOOFROWS_SHIFT 2 177*4882a593Smuzhiyun #define NOOFROWS_MASK 0x0000001C 178*4882a593Smuzhiyun #define NOOFCOLS_SHIFT 5 179*4882a593Smuzhiyun #define NOOFCOLS_MASK 0x00000060 180*4882a593Smuzhiyun #define CHANSIZE_SHIFT 7 181*4882a593Smuzhiyun #define CHANSIZE_MASK 0x00000080 182*4882a593Smuzhiyun #define BURSTLENGTH_SHIFT 8 183*4882a593Smuzhiyun #define BURSTLENGTH_MASK 0x00000100 184*4882a593Smuzhiyun #define CHANSIZE_OVERRIDE (1 << 10) 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun #define SQM_RATIO 0x2424 187*4882a593Smuzhiyun # define STATE0(x) ((x) << 0) 188*4882a593Smuzhiyun # define STATE0_MASK (0xff << 0) 189*4882a593Smuzhiyun # define STATE1(x) ((x) << 8) 190*4882a593Smuzhiyun # define STATE1_MASK (0xff << 8) 191*4882a593Smuzhiyun # define STATE2(x) ((x) << 16) 192*4882a593Smuzhiyun # define STATE2_MASK (0xff << 16) 193*4882a593Smuzhiyun # define STATE3(x) ((x) << 24) 194*4882a593Smuzhiyun # define STATE3_MASK (0xff << 24) 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun #define ARB_RFSH_CNTL 0x2460 197*4882a593Smuzhiyun # define ENABLE (1 << 0) 198*4882a593Smuzhiyun #define ARB_RFSH_RATE 0x2464 199*4882a593Smuzhiyun # define POWERMODE0(x) ((x) << 0) 200*4882a593Smuzhiyun # define POWERMODE0_MASK (0xff << 0) 201*4882a593Smuzhiyun # define POWERMODE1(x) ((x) << 8) 202*4882a593Smuzhiyun # define POWERMODE1_MASK (0xff << 8) 203*4882a593Smuzhiyun # define POWERMODE2(x) ((x) << 16) 204*4882a593Smuzhiyun # define POWERMODE2_MASK (0xff << 16) 205*4882a593Smuzhiyun # define POWERMODE3(x) ((x) << 24) 206*4882a593Smuzhiyun # define POWERMODE3_MASK (0xff << 24) 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun #define MC_SEQ_DRAM 0x2608 209*4882a593Smuzhiyun # define CKE_DYN (1 << 12) 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun #define MC_SEQ_CMD 0x26c4 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun #define MC_SEQ_RESERVE_S 0x2890 214*4882a593Smuzhiyun #define MC_SEQ_RESERVE_M 0x2894 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun #define LVTMA_DATA_SYNCHRONIZATION 0x7adc 217*4882a593Smuzhiyun # define LVTMA_PFREQCHG (1 << 8) 218*4882a593Smuzhiyun #define DCE3_LVTMA_DATA_SYNCHRONIZATION 0x7f98 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun /* PCIE indirect regs */ 221*4882a593Smuzhiyun #define PCIE_P_CNTL 0x40 222*4882a593Smuzhiyun # define P_PLL_PWRDN_IN_L1L23 (1 << 3) 223*4882a593Smuzhiyun # define P_PLL_BUF_PDNB (1 << 4) 224*4882a593Smuzhiyun # define P_PLL_PDNB (1 << 9) 225*4882a593Smuzhiyun # define P_ALLOW_PRX_FRONTEND_SHUTOFF (1 << 12) 226*4882a593Smuzhiyun /* PCIE PORT indirect regs */ 227*4882a593Smuzhiyun #define PCIE_LC_CNTL 0xa0 228*4882a593Smuzhiyun # define LC_L0S_INACTIVITY(x) ((x) << 8) 229*4882a593Smuzhiyun # define LC_L0S_INACTIVITY_MASK (0xf << 8) 230*4882a593Smuzhiyun # define LC_L0S_INACTIVITY_SHIFT 8 231*4882a593Smuzhiyun # define LC_L1_INACTIVITY(x) ((x) << 12) 232*4882a593Smuzhiyun # define LC_L1_INACTIVITY_MASK (0xf << 12) 233*4882a593Smuzhiyun # define LC_L1_INACTIVITY_SHIFT 12 234*4882a593Smuzhiyun # define LC_PMI_TO_L1_DIS (1 << 16) 235*4882a593Smuzhiyun # define LC_ASPM_TO_L1_DIS (1 << 24) 236*4882a593Smuzhiyun #define PCIE_LC_SPEED_CNTL 0xa4 237*4882a593Smuzhiyun # define LC_GEN2_EN (1 << 0) 238*4882a593Smuzhiyun # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 7) 239*4882a593Smuzhiyun # define LC_CURRENT_DATA_RATE (1 << 11) 240*4882a593Smuzhiyun # define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12) 241*4882a593Smuzhiyun # define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12) 242*4882a593Smuzhiyun # define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12 243*4882a593Smuzhiyun # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 244*4882a593Smuzhiyun # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun #endif 247