1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2011 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * Authors: Alex Deucher 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #ifndef __RV6XX_DPM_H__ 26*4882a593Smuzhiyun #define __RV6XX_DPM_H__ 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #include "r600_dpm.h" 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* Represents a single SCLK step. */ 31*4882a593Smuzhiyun struct rv6xx_sclk_stepping 32*4882a593Smuzhiyun { 33*4882a593Smuzhiyun u32 vco_frequency; 34*4882a593Smuzhiyun u32 post_divider; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun struct rv6xx_pm_hw_state { 38*4882a593Smuzhiyun u32 sclks[R600_PM_NUMBER_OF_ACTIVITY_LEVELS]; 39*4882a593Smuzhiyun u32 mclks[R600_PM_NUMBER_OF_MCLKS]; 40*4882a593Smuzhiyun u16 vddc[R600_PM_NUMBER_OF_VOLTAGE_LEVELS]; 41*4882a593Smuzhiyun bool backbias[R600_PM_NUMBER_OF_VOLTAGE_LEVELS]; 42*4882a593Smuzhiyun bool pcie_gen2[R600_PM_NUMBER_OF_ACTIVITY_LEVELS]; 43*4882a593Smuzhiyun u8 high_sclk_index; 44*4882a593Smuzhiyun u8 medium_sclk_index; 45*4882a593Smuzhiyun u8 low_sclk_index; 46*4882a593Smuzhiyun u8 high_mclk_index; 47*4882a593Smuzhiyun u8 medium_mclk_index; 48*4882a593Smuzhiyun u8 low_mclk_index; 49*4882a593Smuzhiyun u8 high_vddc_index; 50*4882a593Smuzhiyun u8 medium_vddc_index; 51*4882a593Smuzhiyun u8 low_vddc_index; 52*4882a593Smuzhiyun u8 rp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS]; 53*4882a593Smuzhiyun u8 lp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS]; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun struct rv6xx_power_info { 57*4882a593Smuzhiyun /* flags */ 58*4882a593Smuzhiyun bool voltage_control; 59*4882a593Smuzhiyun bool sclk_ss; 60*4882a593Smuzhiyun bool mclk_ss; 61*4882a593Smuzhiyun bool dynamic_ss; 62*4882a593Smuzhiyun bool dynamic_pcie_gen2; 63*4882a593Smuzhiyun bool thermal_protection; 64*4882a593Smuzhiyun bool display_gap; 65*4882a593Smuzhiyun bool gfx_clock_gating; 66*4882a593Smuzhiyun /* clk values */ 67*4882a593Smuzhiyun u32 fb_div_scale; 68*4882a593Smuzhiyun u32 spll_ref_div; 69*4882a593Smuzhiyun u32 mpll_ref_div; 70*4882a593Smuzhiyun u32 bsu; 71*4882a593Smuzhiyun u32 bsp; 72*4882a593Smuzhiyun /* */ 73*4882a593Smuzhiyun u32 active_auto_throttle_sources; 74*4882a593Smuzhiyun /* current power state */ 75*4882a593Smuzhiyun u32 restricted_levels; 76*4882a593Smuzhiyun struct rv6xx_pm_hw_state hw; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun struct rv6xx_pl { 80*4882a593Smuzhiyun u32 sclk; 81*4882a593Smuzhiyun u32 mclk; 82*4882a593Smuzhiyun u16 vddc; 83*4882a593Smuzhiyun u32 flags; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun struct rv6xx_ps { 87*4882a593Smuzhiyun struct rv6xx_pl high; 88*4882a593Smuzhiyun struct rv6xx_pl medium; 89*4882a593Smuzhiyun struct rv6xx_pl low; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define RV6XX_DEFAULT_VCLK_FREQ 40000 /* 10 khz */ 93*4882a593Smuzhiyun #define RV6XX_DEFAULT_DCLK_FREQ 30000 /* 10 khz */ 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #endif 96