1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2011 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun #ifndef __RS780D_H__ 24*4882a593Smuzhiyun #define __RS780D_H__ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define CG_SPLL_FUNC_CNTL 0x600 27*4882a593Smuzhiyun # define SPLL_RESET (1 << 0) 28*4882a593Smuzhiyun # define SPLL_SLEEP (1 << 1) 29*4882a593Smuzhiyun # define SPLL_REF_DIV(x) ((x) << 2) 30*4882a593Smuzhiyun # define SPLL_REF_DIV_MASK (7 << 2) 31*4882a593Smuzhiyun # define SPLL_REF_DIV_SHIFT 2 32*4882a593Smuzhiyun # define SPLL_FB_DIV(x) ((x) << 5) 33*4882a593Smuzhiyun # define SPLL_FB_DIV_MASK (0xff << 2) 34*4882a593Smuzhiyun # define SPLL_FB_DIV_SHIFT 2 35*4882a593Smuzhiyun # define SPLL_PULSEEN (1 << 13) 36*4882a593Smuzhiyun # define SPLL_PULSENUM(x) ((x) << 14) 37*4882a593Smuzhiyun # define SPLL_PULSENUM_MASK (3 << 14) 38*4882a593Smuzhiyun # define SPLL_SW_HILEN(x) ((x) << 16) 39*4882a593Smuzhiyun # define SPLL_SW_HILEN_MASK (0xf << 16) 40*4882a593Smuzhiyun # define SPLL_SW_HILEN_SHIFT 16 41*4882a593Smuzhiyun # define SPLL_SW_LOLEN(x) ((x) << 20) 42*4882a593Smuzhiyun # define SPLL_SW_LOLEN_MASK (0xf << 20) 43*4882a593Smuzhiyun # define SPLL_SW_LOLEN_SHIFT 20 44*4882a593Smuzhiyun # define SPLL_DIVEN (1 << 24) 45*4882a593Smuzhiyun # define SPLL_BYPASS_EN (1 << 25) 46*4882a593Smuzhiyun # define SPLL_CHG_STATUS (1 << 29) 47*4882a593Smuzhiyun # define SPLL_CTLREQ (1 << 30) 48*4882a593Smuzhiyun # define SPLL_CTLACK (1 << 31) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* RS780/RS880 PM */ 51*4882a593Smuzhiyun #define FVTHROT_CNTRL_REG 0x3000 52*4882a593Smuzhiyun #define DONT_WAIT_FOR_FBDIV_WRAP (1 << 0) 53*4882a593Smuzhiyun #define MINIMUM_CIP(x) ((x) << 1) 54*4882a593Smuzhiyun #define MINIMUM_CIP_SHIFT 1 55*4882a593Smuzhiyun #define MINIMUM_CIP_MASK 0x1fffffe 56*4882a593Smuzhiyun #define REFRESH_RATE_DIVISOR(x) ((x) << 25) 57*4882a593Smuzhiyun #define REFRESH_RATE_DIVISOR_SHIFT 25 58*4882a593Smuzhiyun #define REFRESH_RATE_DIVISOR_MASK (0x3 << 25) 59*4882a593Smuzhiyun #define ENABLE_FV_THROT (1 << 27) 60*4882a593Smuzhiyun #define ENABLE_FV_UPDATE (1 << 28) 61*4882a593Smuzhiyun #define TREND_SEL_MODE (1 << 29) 62*4882a593Smuzhiyun #define FORCE_TREND_SEL (1 << 30) 63*4882a593Smuzhiyun #define ENABLE_FV_THROT_IO (1 << 31) 64*4882a593Smuzhiyun #define FVTHROT_TARGET_REG 0x3004 65*4882a593Smuzhiyun #define TARGET_IDLE_COUNT(x) ((x) << 0) 66*4882a593Smuzhiyun #define TARGET_IDLE_COUNT_MASK 0xffffff 67*4882a593Smuzhiyun #define TARGET_IDLE_COUNT_SHIFT 0 68*4882a593Smuzhiyun #define FVTHROT_CB1 0x3008 69*4882a593Smuzhiyun #define FVTHROT_CB2 0x300c 70*4882a593Smuzhiyun #define FVTHROT_CB3 0x3010 71*4882a593Smuzhiyun #define FVTHROT_CB4 0x3014 72*4882a593Smuzhiyun #define FVTHROT_UTC0 0x3018 73*4882a593Smuzhiyun #define FVTHROT_UTC1 0x301c 74*4882a593Smuzhiyun #define FVTHROT_UTC2 0x3020 75*4882a593Smuzhiyun #define FVTHROT_UTC3 0x3024 76*4882a593Smuzhiyun #define FVTHROT_UTC4 0x3028 77*4882a593Smuzhiyun #define FVTHROT_DTC0 0x302c 78*4882a593Smuzhiyun #define FVTHROT_DTC1 0x3030 79*4882a593Smuzhiyun #define FVTHROT_DTC2 0x3034 80*4882a593Smuzhiyun #define FVTHROT_DTC3 0x3038 81*4882a593Smuzhiyun #define FVTHROT_DTC4 0x303c 82*4882a593Smuzhiyun #define FVTHROT_FBDIV_REG0 0x3040 83*4882a593Smuzhiyun #define MIN_FEEDBACK_DIV(x) ((x) << 0) 84*4882a593Smuzhiyun #define MIN_FEEDBACK_DIV_MASK 0xfff 85*4882a593Smuzhiyun #define MIN_FEEDBACK_DIV_SHIFT 0 86*4882a593Smuzhiyun #define MAX_FEEDBACK_DIV(x) ((x) << 12) 87*4882a593Smuzhiyun #define MAX_FEEDBACK_DIV_MASK (0xfff << 12) 88*4882a593Smuzhiyun #define MAX_FEEDBACK_DIV_SHIFT 12 89*4882a593Smuzhiyun #define FVTHROT_FBDIV_REG1 0x3044 90*4882a593Smuzhiyun #define MAX_FEEDBACK_STEP(x) ((x) << 0) 91*4882a593Smuzhiyun #define MAX_FEEDBACK_STEP_MASK 0xfff 92*4882a593Smuzhiyun #define MAX_FEEDBACK_STEP_SHIFT 0 93*4882a593Smuzhiyun #define STARTING_FEEDBACK_DIV(x) ((x) << 12) 94*4882a593Smuzhiyun #define STARTING_FEEDBACK_DIV_MASK (0xfff << 12) 95*4882a593Smuzhiyun #define STARTING_FEEDBACK_DIV_SHIFT 12 96*4882a593Smuzhiyun #define FORCE_FEEDBACK_DIV (1 << 24) 97*4882a593Smuzhiyun #define FVTHROT_FBDIV_REG2 0x3048 98*4882a593Smuzhiyun #define FORCED_FEEDBACK_DIV(x) ((x) << 0) 99*4882a593Smuzhiyun #define FORCED_FEEDBACK_DIV_MASK 0xfff 100*4882a593Smuzhiyun #define FORCED_FEEDBACK_DIV_SHIFT 0 101*4882a593Smuzhiyun #define FB_DIV_TIMER_VAL(x) ((x) << 12) 102*4882a593Smuzhiyun #define FB_DIV_TIMER_VAL_MASK (0xffff << 12) 103*4882a593Smuzhiyun #define FB_DIV_TIMER_VAL_SHIFT 12 104*4882a593Smuzhiyun #define FVTHROT_FB_US_REG0 0x304c 105*4882a593Smuzhiyun #define FVTHROT_FB_US_REG1 0x3050 106*4882a593Smuzhiyun #define FVTHROT_FB_DS_REG0 0x3054 107*4882a593Smuzhiyun #define FVTHROT_FB_DS_REG1 0x3058 108*4882a593Smuzhiyun #define FVTHROT_PWM_CTRL_REG0 0x305c 109*4882a593Smuzhiyun #define STARTING_PWM_HIGHTIME(x) ((x) << 0) 110*4882a593Smuzhiyun #define STARTING_PWM_HIGHTIME_MASK 0xfff 111*4882a593Smuzhiyun #define STARTING_PWM_HIGHTIME_SHIFT 0 112*4882a593Smuzhiyun #define NUMBER_OF_CYCLES_IN_PERIOD(x) ((x) << 12) 113*4882a593Smuzhiyun #define NUMBER_OF_CYCLES_IN_PERIOD_MASK (0xfff << 12) 114*4882a593Smuzhiyun #define NUMBER_OF_CYCLES_IN_PERIOD_SHIFT 12 115*4882a593Smuzhiyun #define FORCE_STARTING_PWM_HIGHTIME (1 << 24) 116*4882a593Smuzhiyun #define INVERT_PWM_WAVEFORM (1 << 25) 117*4882a593Smuzhiyun #define FVTHROT_PWM_CTRL_REG1 0x3060 118*4882a593Smuzhiyun #define MIN_PWM_HIGHTIME(x) ((x) << 0) 119*4882a593Smuzhiyun #define MIN_PWM_HIGHTIME_MASK 0xfff 120*4882a593Smuzhiyun #define MIN_PWM_HIGHTIME_SHIFT 0 121*4882a593Smuzhiyun #define MAX_PWM_HIGHTIME(x) ((x) << 12) 122*4882a593Smuzhiyun #define MAX_PWM_HIGHTIME_MASK (0xfff << 12) 123*4882a593Smuzhiyun #define MAX_PWM_HIGHTIME_SHIFT 12 124*4882a593Smuzhiyun #define FVTHROT_PWM_US_REG0 0x3064 125*4882a593Smuzhiyun #define FVTHROT_PWM_US_REG1 0x3068 126*4882a593Smuzhiyun #define FVTHROT_PWM_DS_REG0 0x306c 127*4882a593Smuzhiyun #define FVTHROT_PWM_DS_REG1 0x3070 128*4882a593Smuzhiyun #define FVTHROT_STATUS_REG0 0x3074 129*4882a593Smuzhiyun #define CURRENT_FEEDBACK_DIV_MASK 0xfff 130*4882a593Smuzhiyun #define CURRENT_FEEDBACK_DIV_SHIFT 0 131*4882a593Smuzhiyun #define FVTHROT_STATUS_REG1 0x3078 132*4882a593Smuzhiyun #define FVTHROT_STATUS_REG2 0x307c 133*4882a593Smuzhiyun #define CG_INTGFX_MISC 0x3080 134*4882a593Smuzhiyun #define FVTHROT_VBLANK_SEL (1 << 9) 135*4882a593Smuzhiyun #define FVTHROT_PWM_FEEDBACK_DIV_REG1 0x308c 136*4882a593Smuzhiyun #define RANGE0_PWM_FEEDBACK_DIV(x) ((x) << 0) 137*4882a593Smuzhiyun #define RANGE0_PWM_FEEDBACK_DIV_MASK 0xfff 138*4882a593Smuzhiyun #define RANGE0_PWM_FEEDBACK_DIV_SHIFT 0 139*4882a593Smuzhiyun #define RANGE_PWM_FEEDBACK_DIV_EN (1 << 12) 140*4882a593Smuzhiyun #define FVTHROT_PWM_FEEDBACK_DIV_REG2 0x3090 141*4882a593Smuzhiyun #define RANGE1_PWM_FEEDBACK_DIV(x) ((x) << 0) 142*4882a593Smuzhiyun #define RANGE1_PWM_FEEDBACK_DIV_MASK 0xfff 143*4882a593Smuzhiyun #define RANGE1_PWM_FEEDBACK_DIV_SHIFT 0 144*4882a593Smuzhiyun #define RANGE2_PWM_FEEDBACK_DIV(x) ((x) << 12) 145*4882a593Smuzhiyun #define RANGE2_PWM_FEEDBACK_DIV_MASK (0xfff << 12) 146*4882a593Smuzhiyun #define RANGE2_PWM_FEEDBACK_DIV_SHIFT 12 147*4882a593Smuzhiyun #define FVTHROT_PWM_FEEDBACK_DIV_REG3 0x3094 148*4882a593Smuzhiyun #define RANGE0_PWM(x) ((x) << 0) 149*4882a593Smuzhiyun #define RANGE0_PWM_MASK 0xfff 150*4882a593Smuzhiyun #define RANGE0_PWM_SHIFT 0 151*4882a593Smuzhiyun #define RANGE1_PWM(x) ((x) << 12) 152*4882a593Smuzhiyun #define RANGE1_PWM_MASK (0xfff << 12) 153*4882a593Smuzhiyun #define RANGE1_PWM_SHIFT 12 154*4882a593Smuzhiyun #define FVTHROT_PWM_FEEDBACK_DIV_REG4 0x3098 155*4882a593Smuzhiyun #define RANGE2_PWM(x) ((x) << 0) 156*4882a593Smuzhiyun #define RANGE2_PWM_MASK 0xfff 157*4882a593Smuzhiyun #define RANGE2_PWM_SHIFT 0 158*4882a593Smuzhiyun #define RANGE3_PWM(x) ((x) << 12) 159*4882a593Smuzhiyun #define RANGE3_PWM_MASK (0xfff << 12) 160*4882a593Smuzhiyun #define RANGE3_PWM_SHIFT 12 161*4882a593Smuzhiyun #define FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1 0x30ac 162*4882a593Smuzhiyun #define RANGE0_SLOW_CLK_FEEDBACK_DIV(x) ((x) << 0) 163*4882a593Smuzhiyun #define RANGE0_SLOW_CLK_FEEDBACK_DIV_MASK 0xfff 164*4882a593Smuzhiyun #define RANGE0_SLOW_CLK_FEEDBACK_DIV_SHIFT 0 165*4882a593Smuzhiyun #define RANGE_SLOW_CLK_FEEDBACK_DIV_EN (1 << 12) 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun #define GFX_MACRO_BYPASS_CNTL 0x30c0 168*4882a593Smuzhiyun #define SPLL_BYPASS_CNTL (1 << 0) 169*4882a593Smuzhiyun #define UPLL_BYPASS_CNTL (1 << 1) 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun #endif 172