1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2011 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun #ifndef __RS780_DPM_H__ 24*4882a593Smuzhiyun #define __RS780_DPM_H__ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun enum rs780_vddc_level { 27*4882a593Smuzhiyun RS780_VDDC_LEVEL_UNKNOWN = 0, 28*4882a593Smuzhiyun RS780_VDDC_LEVEL_LOW = 1, 29*4882a593Smuzhiyun RS780_VDDC_LEVEL_HIGH = 2, 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun struct igp_power_info { 33*4882a593Smuzhiyun /* flags */ 34*4882a593Smuzhiyun bool invert_pwm_required; 35*4882a593Smuzhiyun bool pwm_voltage_control; 36*4882a593Smuzhiyun bool voltage_control; 37*4882a593Smuzhiyun bool gfx_clock_gating; 38*4882a593Smuzhiyun /* stored values */ 39*4882a593Smuzhiyun u32 system_config; 40*4882a593Smuzhiyun u32 bootup_uma_clk; 41*4882a593Smuzhiyun u16 max_voltage; 42*4882a593Smuzhiyun u16 min_voltage; 43*4882a593Smuzhiyun u16 boot_voltage; 44*4882a593Smuzhiyun u16 inter_voltage_low; 45*4882a593Smuzhiyun u16 inter_voltage_high; 46*4882a593Smuzhiyun u16 num_of_cycles_in_period; 47*4882a593Smuzhiyun /* variable */ 48*4882a593Smuzhiyun int crtc_id; 49*4882a593Smuzhiyun int refresh_rate; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun struct igp_ps { 53*4882a593Smuzhiyun enum rs780_vddc_level min_voltage; 54*4882a593Smuzhiyun enum rs780_vddc_level max_voltage; 55*4882a593Smuzhiyun u32 sclk_low; 56*4882a593Smuzhiyun u32 sclk_high; 57*4882a593Smuzhiyun u32 flags; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define RS780_CGFTV_DFLT 0x0303000f 61*4882a593Smuzhiyun #define RS780_FBDIVTIMERVAL_DFLT 0x2710 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define RS780_FVTHROTUTC0_DFLT 0x04010040 64*4882a593Smuzhiyun #define RS780_FVTHROTUTC1_DFLT 0x04010040 65*4882a593Smuzhiyun #define RS780_FVTHROTUTC2_DFLT 0x04010040 66*4882a593Smuzhiyun #define RS780_FVTHROTUTC3_DFLT 0x04010040 67*4882a593Smuzhiyun #define RS780_FVTHROTUTC4_DFLT 0x04010040 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define RS780_FVTHROTDTC0_DFLT 0x04010040 70*4882a593Smuzhiyun #define RS780_FVTHROTDTC1_DFLT 0x04010040 71*4882a593Smuzhiyun #define RS780_FVTHROTDTC2_DFLT 0x04010040 72*4882a593Smuzhiyun #define RS780_FVTHROTDTC3_DFLT 0x04010040 73*4882a593Smuzhiyun #define RS780_FVTHROTDTC4_DFLT 0x04010040 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define RS780_FVTHROTFBUSREG0_DFLT 0x00001001 76*4882a593Smuzhiyun #define RS780_FVTHROTFBUSREG1_DFLT 0x00002002 77*4882a593Smuzhiyun #define RS780_FVTHROTFBDSREG0_DFLT 0x00004001 78*4882a593Smuzhiyun #define RS780_FVTHROTFBDSREG1_DFLT 0x00020010 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define RS780_FVTHROTPWMUSREG0_DFLT 0x00002001 81*4882a593Smuzhiyun #define RS780_FVTHROTPWMUSREG1_DFLT 0x00004003 82*4882a593Smuzhiyun #define RS780_FVTHROTPWMDSREG0_DFLT 0x00002001 83*4882a593Smuzhiyun #define RS780_FVTHROTPWMDSREG1_DFLT 0x00004003 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define RS780_FVTHROTPWMFBDIVRANGEREG0_DFLT 0x37 86*4882a593Smuzhiyun #define RS780_FVTHROTPWMFBDIVRANGEREG1_DFLT 0x4b 87*4882a593Smuzhiyun #define RS780_FVTHROTPWMFBDIVRANGEREG2_DFLT 0x8b 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define RS780D_FVTHROTPWMFBDIVRANGEREG0_DFLT 0x8b 90*4882a593Smuzhiyun #define RS780D_FVTHROTPWMFBDIVRANGEREG1_DFLT 0x8c 91*4882a593Smuzhiyun #define RS780D_FVTHROTPWMFBDIVRANGEREG2_DFLT 0xb5 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define RS880D_FVTHROTPWMFBDIVRANGEREG0_DFLT 0x8d 94*4882a593Smuzhiyun #define RS880D_FVTHROTPWMFBDIVRANGEREG1_DFLT 0x8e 95*4882a593Smuzhiyun #define RS880D_FVTHROTPWMFBDIVRANGEREG2_DFLT 0xBa 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define RS780_FVTHROTPWMRANGE0_GPIO_DFLT 0x1a 98*4882a593Smuzhiyun #define RS780_FVTHROTPWMRANGE1_GPIO_DFLT 0x1a 99*4882a593Smuzhiyun #define RS780_FVTHROTPWMRANGE2_GPIO_DFLT 0x0 100*4882a593Smuzhiyun #define RS780_FVTHROTPWMRANGE3_GPIO_DFLT 0x0 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #define RS780_SLOWCLKFEEDBACKDIV_DFLT 110 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define RS780_CGCLKGATING_DFLT 0x0000E204 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #define RS780_DEFAULT_VCLK_FREQ 53300 /* 10 khz */ 107*4882a593Smuzhiyun #define RS780_DEFAULT_DCLK_FREQ 40000 /* 10 khz */ 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #endif 110