1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2013 Advanced Micro Devices, Inc.
3*4882a593Smuzhiyun * All Rights Reserved.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a
6*4882a593Smuzhiyun * copy of this software and associated documentation files (the
7*4882a593Smuzhiyun * "Software"), to deal in the Software without restriction, including
8*4882a593Smuzhiyun * without limitation the rights to use, copy, modify, merge, publish,
9*4882a593Smuzhiyun * distribute, sub license, and/or sell copies of the Software, and to
10*4882a593Smuzhiyun * permit persons to whom the Software is furnished to do so, subject to
11*4882a593Smuzhiyun * the following conditions:
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16*4882a593Smuzhiyun * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17*4882a593Smuzhiyun * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18*4882a593Smuzhiyun * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19*4882a593Smuzhiyun * USE OR OTHER DEALINGS IN THE SOFTWARE.
20*4882a593Smuzhiyun *
21*4882a593Smuzhiyun * The above copyright notice and this permission notice (including the
22*4882a593Smuzhiyun * next paragraph) shall be included in all copies or substantial portions
23*4882a593Smuzhiyun * of the Software.
24*4882a593Smuzhiyun *
25*4882a593Smuzhiyun * Authors: Christian König <christian.koenig@amd.com>
26*4882a593Smuzhiyun */
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #include <linux/firmware.h>
29*4882a593Smuzhiyun #include <linux/module.h>
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #include <drm/drm.h>
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #include "radeon.h"
34*4882a593Smuzhiyun #include "radeon_asic.h"
35*4882a593Smuzhiyun #include "sid.h"
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* 1 second timeout */
38*4882a593Smuzhiyun #define VCE_IDLE_TIMEOUT_MS 1000
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /* Firmware Names */
41*4882a593Smuzhiyun #define FIRMWARE_TAHITI "radeon/TAHITI_vce.bin"
42*4882a593Smuzhiyun #define FIRMWARE_BONAIRE "radeon/BONAIRE_vce.bin"
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun MODULE_FIRMWARE(FIRMWARE_TAHITI);
45*4882a593Smuzhiyun MODULE_FIRMWARE(FIRMWARE_BONAIRE);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun static void radeon_vce_idle_work_handler(struct work_struct *work);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /**
50*4882a593Smuzhiyun * radeon_vce_init - allocate memory, load vce firmware
51*4882a593Smuzhiyun *
52*4882a593Smuzhiyun * @rdev: radeon_device pointer
53*4882a593Smuzhiyun *
54*4882a593Smuzhiyun * First step to get VCE online, allocate memory and load the firmware
55*4882a593Smuzhiyun */
radeon_vce_init(struct radeon_device * rdev)56*4882a593Smuzhiyun int radeon_vce_init(struct radeon_device *rdev)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun static const char *fw_version = "[ATI LIB=VCEFW,";
59*4882a593Smuzhiyun static const char *fb_version = "[ATI LIB=VCEFWSTATS,";
60*4882a593Smuzhiyun unsigned long size;
61*4882a593Smuzhiyun const char *fw_name, *c;
62*4882a593Smuzhiyun uint8_t start, mid, end;
63*4882a593Smuzhiyun int i, r;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun INIT_DELAYED_WORK(&rdev->vce.idle_work, radeon_vce_idle_work_handler);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun switch (rdev->family) {
68*4882a593Smuzhiyun case CHIP_TAHITI:
69*4882a593Smuzhiyun case CHIP_PITCAIRN:
70*4882a593Smuzhiyun case CHIP_VERDE:
71*4882a593Smuzhiyun case CHIP_OLAND:
72*4882a593Smuzhiyun case CHIP_ARUBA:
73*4882a593Smuzhiyun fw_name = FIRMWARE_TAHITI;
74*4882a593Smuzhiyun break;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun case CHIP_BONAIRE:
77*4882a593Smuzhiyun case CHIP_KAVERI:
78*4882a593Smuzhiyun case CHIP_KABINI:
79*4882a593Smuzhiyun case CHIP_HAWAII:
80*4882a593Smuzhiyun case CHIP_MULLINS:
81*4882a593Smuzhiyun fw_name = FIRMWARE_BONAIRE;
82*4882a593Smuzhiyun break;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun default:
85*4882a593Smuzhiyun return -EINVAL;
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun r = request_firmware(&rdev->vce_fw, fw_name, rdev->dev);
89*4882a593Smuzhiyun if (r) {
90*4882a593Smuzhiyun dev_err(rdev->dev, "radeon_vce: Can't load firmware \"%s\"\n",
91*4882a593Smuzhiyun fw_name);
92*4882a593Smuzhiyun return r;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /* search for firmware version */
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun size = rdev->vce_fw->size - strlen(fw_version) - 9;
98*4882a593Smuzhiyun c = rdev->vce_fw->data;
99*4882a593Smuzhiyun for (;size > 0; --size, ++c)
100*4882a593Smuzhiyun if (strncmp(c, fw_version, strlen(fw_version)) == 0)
101*4882a593Smuzhiyun break;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun if (size == 0)
104*4882a593Smuzhiyun return -EINVAL;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun c += strlen(fw_version);
107*4882a593Smuzhiyun if (sscanf(c, "%2hhd.%2hhd.%2hhd]", &start, &mid, &end) != 3)
108*4882a593Smuzhiyun return -EINVAL;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun /* search for feedback version */
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun size = rdev->vce_fw->size - strlen(fb_version) - 3;
113*4882a593Smuzhiyun c = rdev->vce_fw->data;
114*4882a593Smuzhiyun for (;size > 0; --size, ++c)
115*4882a593Smuzhiyun if (strncmp(c, fb_version, strlen(fb_version)) == 0)
116*4882a593Smuzhiyun break;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun if (size == 0)
119*4882a593Smuzhiyun return -EINVAL;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun c += strlen(fb_version);
122*4882a593Smuzhiyun if (sscanf(c, "%2u]", &rdev->vce.fb_version) != 1)
123*4882a593Smuzhiyun return -EINVAL;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun DRM_INFO("Found VCE firmware/feedback version %hhd.%hhd.%hhd / %d!\n",
126*4882a593Smuzhiyun start, mid, end, rdev->vce.fb_version);
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun rdev->vce.fw_version = (start << 24) | (mid << 16) | (end << 8);
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun /* we can only work with this fw version for now */
131*4882a593Smuzhiyun if ((rdev->vce.fw_version != ((40 << 24) | (2 << 16) | (2 << 8))) &&
132*4882a593Smuzhiyun (rdev->vce.fw_version != ((50 << 24) | (0 << 16) | (1 << 8))) &&
133*4882a593Smuzhiyun (rdev->vce.fw_version != ((50 << 24) | (1 << 16) | (2 << 8))))
134*4882a593Smuzhiyun return -EINVAL;
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun /* allocate firmware, stack and heap BO */
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun if (rdev->family < CHIP_BONAIRE)
139*4882a593Smuzhiyun size = vce_v1_0_bo_size(rdev);
140*4882a593Smuzhiyun else
141*4882a593Smuzhiyun size = vce_v2_0_bo_size(rdev);
142*4882a593Smuzhiyun r = radeon_bo_create(rdev, size, PAGE_SIZE, true,
143*4882a593Smuzhiyun RADEON_GEM_DOMAIN_VRAM, 0, NULL, NULL,
144*4882a593Smuzhiyun &rdev->vce.vcpu_bo);
145*4882a593Smuzhiyun if (r) {
146*4882a593Smuzhiyun dev_err(rdev->dev, "(%d) failed to allocate VCE bo\n", r);
147*4882a593Smuzhiyun return r;
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun r = radeon_bo_reserve(rdev->vce.vcpu_bo, false);
151*4882a593Smuzhiyun if (r) {
152*4882a593Smuzhiyun radeon_bo_unref(&rdev->vce.vcpu_bo);
153*4882a593Smuzhiyun dev_err(rdev->dev, "(%d) failed to reserve VCE bo\n", r);
154*4882a593Smuzhiyun return r;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun r = radeon_bo_pin(rdev->vce.vcpu_bo, RADEON_GEM_DOMAIN_VRAM,
158*4882a593Smuzhiyun &rdev->vce.gpu_addr);
159*4882a593Smuzhiyun radeon_bo_unreserve(rdev->vce.vcpu_bo);
160*4882a593Smuzhiyun if (r) {
161*4882a593Smuzhiyun radeon_bo_unref(&rdev->vce.vcpu_bo);
162*4882a593Smuzhiyun dev_err(rdev->dev, "(%d) VCE bo pin failed\n", r);
163*4882a593Smuzhiyun return r;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) {
167*4882a593Smuzhiyun atomic_set(&rdev->vce.handles[i], 0);
168*4882a593Smuzhiyun rdev->vce.filp[i] = NULL;
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun return 0;
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun /**
175*4882a593Smuzhiyun * radeon_vce_fini - free memory
176*4882a593Smuzhiyun *
177*4882a593Smuzhiyun * @rdev: radeon_device pointer
178*4882a593Smuzhiyun *
179*4882a593Smuzhiyun * Last step on VCE teardown, free firmware memory
180*4882a593Smuzhiyun */
radeon_vce_fini(struct radeon_device * rdev)181*4882a593Smuzhiyun void radeon_vce_fini(struct radeon_device *rdev)
182*4882a593Smuzhiyun {
183*4882a593Smuzhiyun if (rdev->vce.vcpu_bo == NULL)
184*4882a593Smuzhiyun return;
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun radeon_bo_unref(&rdev->vce.vcpu_bo);
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun release_firmware(rdev->vce_fw);
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun /**
192*4882a593Smuzhiyun * radeon_vce_suspend - unpin VCE fw memory
193*4882a593Smuzhiyun *
194*4882a593Smuzhiyun * @rdev: radeon_device pointer
195*4882a593Smuzhiyun *
196*4882a593Smuzhiyun */
radeon_vce_suspend(struct radeon_device * rdev)197*4882a593Smuzhiyun int radeon_vce_suspend(struct radeon_device *rdev)
198*4882a593Smuzhiyun {
199*4882a593Smuzhiyun int i;
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun if (rdev->vce.vcpu_bo == NULL)
202*4882a593Smuzhiyun return 0;
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i)
205*4882a593Smuzhiyun if (atomic_read(&rdev->vce.handles[i]))
206*4882a593Smuzhiyun break;
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun if (i == RADEON_MAX_VCE_HANDLES)
209*4882a593Smuzhiyun return 0;
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun /* TODO: suspending running encoding sessions isn't supported */
212*4882a593Smuzhiyun return -EINVAL;
213*4882a593Smuzhiyun }
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun /**
216*4882a593Smuzhiyun * radeon_vce_resume - pin VCE fw memory
217*4882a593Smuzhiyun *
218*4882a593Smuzhiyun * @rdev: radeon_device pointer
219*4882a593Smuzhiyun *
220*4882a593Smuzhiyun */
radeon_vce_resume(struct radeon_device * rdev)221*4882a593Smuzhiyun int radeon_vce_resume(struct radeon_device *rdev)
222*4882a593Smuzhiyun {
223*4882a593Smuzhiyun void *cpu_addr;
224*4882a593Smuzhiyun int r;
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun if (rdev->vce.vcpu_bo == NULL)
227*4882a593Smuzhiyun return -EINVAL;
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun r = radeon_bo_reserve(rdev->vce.vcpu_bo, false);
230*4882a593Smuzhiyun if (r) {
231*4882a593Smuzhiyun dev_err(rdev->dev, "(%d) failed to reserve VCE bo\n", r);
232*4882a593Smuzhiyun return r;
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun r = radeon_bo_kmap(rdev->vce.vcpu_bo, &cpu_addr);
236*4882a593Smuzhiyun if (r) {
237*4882a593Smuzhiyun radeon_bo_unreserve(rdev->vce.vcpu_bo);
238*4882a593Smuzhiyun dev_err(rdev->dev, "(%d) VCE map failed\n", r);
239*4882a593Smuzhiyun return r;
240*4882a593Smuzhiyun }
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun memset(cpu_addr, 0, radeon_bo_size(rdev->vce.vcpu_bo));
243*4882a593Smuzhiyun if (rdev->family < CHIP_BONAIRE)
244*4882a593Smuzhiyun r = vce_v1_0_load_fw(rdev, cpu_addr);
245*4882a593Smuzhiyun else
246*4882a593Smuzhiyun memcpy(cpu_addr, rdev->vce_fw->data, rdev->vce_fw->size);
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun radeon_bo_kunmap(rdev->vce.vcpu_bo);
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun radeon_bo_unreserve(rdev->vce.vcpu_bo);
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun return r;
253*4882a593Smuzhiyun }
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun /**
256*4882a593Smuzhiyun * radeon_vce_idle_work_handler - power off VCE
257*4882a593Smuzhiyun *
258*4882a593Smuzhiyun * @work: pointer to work structure
259*4882a593Smuzhiyun *
260*4882a593Smuzhiyun * power of VCE when it's not used any more
261*4882a593Smuzhiyun */
radeon_vce_idle_work_handler(struct work_struct * work)262*4882a593Smuzhiyun static void radeon_vce_idle_work_handler(struct work_struct *work)
263*4882a593Smuzhiyun {
264*4882a593Smuzhiyun struct radeon_device *rdev =
265*4882a593Smuzhiyun container_of(work, struct radeon_device, vce.idle_work.work);
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun if ((radeon_fence_count_emitted(rdev, TN_RING_TYPE_VCE1_INDEX) == 0) &&
268*4882a593Smuzhiyun (radeon_fence_count_emitted(rdev, TN_RING_TYPE_VCE2_INDEX) == 0)) {
269*4882a593Smuzhiyun if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
270*4882a593Smuzhiyun radeon_dpm_enable_vce(rdev, false);
271*4882a593Smuzhiyun } else {
272*4882a593Smuzhiyun radeon_set_vce_clocks(rdev, 0, 0);
273*4882a593Smuzhiyun }
274*4882a593Smuzhiyun } else {
275*4882a593Smuzhiyun schedule_delayed_work(&rdev->vce.idle_work,
276*4882a593Smuzhiyun msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS));
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun }
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun /**
281*4882a593Smuzhiyun * radeon_vce_note_usage - power up VCE
282*4882a593Smuzhiyun *
283*4882a593Smuzhiyun * @rdev: radeon_device pointer
284*4882a593Smuzhiyun *
285*4882a593Smuzhiyun * Make sure VCE is powerd up when we want to use it
286*4882a593Smuzhiyun */
radeon_vce_note_usage(struct radeon_device * rdev)287*4882a593Smuzhiyun void radeon_vce_note_usage(struct radeon_device *rdev)
288*4882a593Smuzhiyun {
289*4882a593Smuzhiyun bool streams_changed = false;
290*4882a593Smuzhiyun bool set_clocks = !cancel_delayed_work_sync(&rdev->vce.idle_work);
291*4882a593Smuzhiyun set_clocks &= schedule_delayed_work(&rdev->vce.idle_work,
292*4882a593Smuzhiyun msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS));
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
295*4882a593Smuzhiyun /* XXX figure out if the streams changed */
296*4882a593Smuzhiyun streams_changed = false;
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun if (set_clocks || streams_changed) {
300*4882a593Smuzhiyun if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
301*4882a593Smuzhiyun radeon_dpm_enable_vce(rdev, true);
302*4882a593Smuzhiyun } else {
303*4882a593Smuzhiyun radeon_set_vce_clocks(rdev, 53300, 40000);
304*4882a593Smuzhiyun }
305*4882a593Smuzhiyun }
306*4882a593Smuzhiyun }
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun /**
309*4882a593Smuzhiyun * radeon_vce_free_handles - free still open VCE handles
310*4882a593Smuzhiyun *
311*4882a593Smuzhiyun * @rdev: radeon_device pointer
312*4882a593Smuzhiyun * @filp: drm file pointer
313*4882a593Smuzhiyun *
314*4882a593Smuzhiyun * Close all VCE handles still open by this file pointer
315*4882a593Smuzhiyun */
radeon_vce_free_handles(struct radeon_device * rdev,struct drm_file * filp)316*4882a593Smuzhiyun void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp)
317*4882a593Smuzhiyun {
318*4882a593Smuzhiyun int i, r;
319*4882a593Smuzhiyun for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) {
320*4882a593Smuzhiyun uint32_t handle = atomic_read(&rdev->vce.handles[i]);
321*4882a593Smuzhiyun if (!handle || rdev->vce.filp[i] != filp)
322*4882a593Smuzhiyun continue;
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun radeon_vce_note_usage(rdev);
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun r = radeon_vce_get_destroy_msg(rdev, TN_RING_TYPE_VCE1_INDEX,
327*4882a593Smuzhiyun handle, NULL);
328*4882a593Smuzhiyun if (r)
329*4882a593Smuzhiyun DRM_ERROR("Error destroying VCE handle (%d)!\n", r);
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun rdev->vce.filp[i] = NULL;
332*4882a593Smuzhiyun atomic_set(&rdev->vce.handles[i], 0);
333*4882a593Smuzhiyun }
334*4882a593Smuzhiyun }
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun /**
337*4882a593Smuzhiyun * radeon_vce_get_create_msg - generate a VCE create msg
338*4882a593Smuzhiyun *
339*4882a593Smuzhiyun * @rdev: radeon_device pointer
340*4882a593Smuzhiyun * @ring: ring we should submit the msg to
341*4882a593Smuzhiyun * @handle: VCE session handle to use
342*4882a593Smuzhiyun * @fence: optional fence to return
343*4882a593Smuzhiyun *
344*4882a593Smuzhiyun * Open up a stream for HW test
345*4882a593Smuzhiyun */
radeon_vce_get_create_msg(struct radeon_device * rdev,int ring,uint32_t handle,struct radeon_fence ** fence)346*4882a593Smuzhiyun int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
347*4882a593Smuzhiyun uint32_t handle, struct radeon_fence **fence)
348*4882a593Smuzhiyun {
349*4882a593Smuzhiyun const unsigned ib_size_dw = 1024;
350*4882a593Smuzhiyun struct radeon_ib ib;
351*4882a593Smuzhiyun uint64_t dummy;
352*4882a593Smuzhiyun int i, r;
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun r = radeon_ib_get(rdev, ring, &ib, NULL, ib_size_dw * 4);
355*4882a593Smuzhiyun if (r) {
356*4882a593Smuzhiyun DRM_ERROR("radeon: failed to get ib (%d).\n", r);
357*4882a593Smuzhiyun return r;
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun dummy = ib.gpu_addr + 1024;
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun /* stitch together an VCE create msg */
363*4882a593Smuzhiyun ib.length_dw = 0;
364*4882a593Smuzhiyun ib.ptr[ib.length_dw++] = cpu_to_le32(0x0000000c); /* len */
365*4882a593Smuzhiyun ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000001); /* session cmd */
366*4882a593Smuzhiyun ib.ptr[ib.length_dw++] = cpu_to_le32(handle);
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000030); /* len */
369*4882a593Smuzhiyun ib.ptr[ib.length_dw++] = cpu_to_le32(0x01000001); /* create cmd */
370*4882a593Smuzhiyun ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000000);
371*4882a593Smuzhiyun ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000042);
372*4882a593Smuzhiyun ib.ptr[ib.length_dw++] = cpu_to_le32(0x0000000a);
373*4882a593Smuzhiyun ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000001);
374*4882a593Smuzhiyun ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000080);
375*4882a593Smuzhiyun ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000060);
376*4882a593Smuzhiyun ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000100);
377*4882a593Smuzhiyun ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000100);
378*4882a593Smuzhiyun ib.ptr[ib.length_dw++] = cpu_to_le32(0x0000000c);
379*4882a593Smuzhiyun ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000000);
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000014); /* len */
382*4882a593Smuzhiyun ib.ptr[ib.length_dw++] = cpu_to_le32(0x05000005); /* feedback buffer */
383*4882a593Smuzhiyun ib.ptr[ib.length_dw++] = cpu_to_le32(upper_32_bits(dummy));
384*4882a593Smuzhiyun ib.ptr[ib.length_dw++] = cpu_to_le32(dummy);
385*4882a593Smuzhiyun ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000001);
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun for (i = ib.length_dw; i < ib_size_dw; ++i)
388*4882a593Smuzhiyun ib.ptr[i] = cpu_to_le32(0x0);
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun r = radeon_ib_schedule(rdev, &ib, NULL, false);
391*4882a593Smuzhiyun if (r)
392*4882a593Smuzhiyun DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun if (fence)
396*4882a593Smuzhiyun *fence = radeon_fence_ref(ib.fence);
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun radeon_ib_free(rdev, &ib);
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun return r;
401*4882a593Smuzhiyun }
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun /**
404*4882a593Smuzhiyun * radeon_vce_get_destroy_msg - generate a VCE destroy msg
405*4882a593Smuzhiyun *
406*4882a593Smuzhiyun * @rdev: radeon_device pointer
407*4882a593Smuzhiyun * @ring: ring we should submit the msg to
408*4882a593Smuzhiyun * @handle: VCE session handle to use
409*4882a593Smuzhiyun * @fence: optional fence to return
410*4882a593Smuzhiyun *
411*4882a593Smuzhiyun * Close up a stream for HW test or if userspace failed to do so
412*4882a593Smuzhiyun */
radeon_vce_get_destroy_msg(struct radeon_device * rdev,int ring,uint32_t handle,struct radeon_fence ** fence)413*4882a593Smuzhiyun int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
414*4882a593Smuzhiyun uint32_t handle, struct radeon_fence **fence)
415*4882a593Smuzhiyun {
416*4882a593Smuzhiyun const unsigned ib_size_dw = 1024;
417*4882a593Smuzhiyun struct radeon_ib ib;
418*4882a593Smuzhiyun uint64_t dummy;
419*4882a593Smuzhiyun int i, r;
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun r = radeon_ib_get(rdev, ring, &ib, NULL, ib_size_dw * 4);
422*4882a593Smuzhiyun if (r) {
423*4882a593Smuzhiyun DRM_ERROR("radeon: failed to get ib (%d).\n", r);
424*4882a593Smuzhiyun return r;
425*4882a593Smuzhiyun }
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun dummy = ib.gpu_addr + 1024;
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun /* stitch together an VCE destroy msg */
430*4882a593Smuzhiyun ib.length_dw = 0;
431*4882a593Smuzhiyun ib.ptr[ib.length_dw++] = cpu_to_le32(0x0000000c); /* len */
432*4882a593Smuzhiyun ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000001); /* session cmd */
433*4882a593Smuzhiyun ib.ptr[ib.length_dw++] = cpu_to_le32(handle);
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000014); /* len */
436*4882a593Smuzhiyun ib.ptr[ib.length_dw++] = cpu_to_le32(0x05000005); /* feedback buffer */
437*4882a593Smuzhiyun ib.ptr[ib.length_dw++] = cpu_to_le32(upper_32_bits(dummy));
438*4882a593Smuzhiyun ib.ptr[ib.length_dw++] = cpu_to_le32(dummy);
439*4882a593Smuzhiyun ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000001);
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000008); /* len */
442*4882a593Smuzhiyun ib.ptr[ib.length_dw++] = cpu_to_le32(0x02000001); /* destroy cmd */
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun for (i = ib.length_dw; i < ib_size_dw; ++i)
445*4882a593Smuzhiyun ib.ptr[i] = cpu_to_le32(0x0);
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun r = radeon_ib_schedule(rdev, &ib, NULL, false);
448*4882a593Smuzhiyun if (r) {
449*4882a593Smuzhiyun DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
450*4882a593Smuzhiyun }
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun if (fence)
453*4882a593Smuzhiyun *fence = radeon_fence_ref(ib.fence);
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun radeon_ib_free(rdev, &ib);
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun return r;
458*4882a593Smuzhiyun }
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun /**
461*4882a593Smuzhiyun * radeon_vce_cs_reloc - command submission relocation
462*4882a593Smuzhiyun *
463*4882a593Smuzhiyun * @p: parser context
464*4882a593Smuzhiyun * @lo: address of lower dword
465*4882a593Smuzhiyun * @hi: address of higher dword
466*4882a593Smuzhiyun * @size: size of checker for relocation buffer
467*4882a593Smuzhiyun *
468*4882a593Smuzhiyun * Patch relocation inside command stream with real buffer address
469*4882a593Smuzhiyun */
radeon_vce_cs_reloc(struct radeon_cs_parser * p,int lo,int hi,unsigned size)470*4882a593Smuzhiyun int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi,
471*4882a593Smuzhiyun unsigned size)
472*4882a593Smuzhiyun {
473*4882a593Smuzhiyun struct radeon_cs_chunk *relocs_chunk;
474*4882a593Smuzhiyun struct radeon_bo_list *reloc;
475*4882a593Smuzhiyun uint64_t start, end, offset;
476*4882a593Smuzhiyun unsigned idx;
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun relocs_chunk = p->chunk_relocs;
479*4882a593Smuzhiyun offset = radeon_get_ib_value(p, lo);
480*4882a593Smuzhiyun idx = radeon_get_ib_value(p, hi);
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun if (idx >= relocs_chunk->length_dw) {
483*4882a593Smuzhiyun DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
484*4882a593Smuzhiyun idx, relocs_chunk->length_dw);
485*4882a593Smuzhiyun return -EINVAL;
486*4882a593Smuzhiyun }
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun reloc = &p->relocs[(idx / 4)];
489*4882a593Smuzhiyun start = reloc->gpu_offset;
490*4882a593Smuzhiyun end = start + radeon_bo_size(reloc->robj);
491*4882a593Smuzhiyun start += offset;
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun p->ib.ptr[lo] = start & 0xFFFFFFFF;
494*4882a593Smuzhiyun p->ib.ptr[hi] = start >> 32;
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun if (end <= start) {
497*4882a593Smuzhiyun DRM_ERROR("invalid reloc offset %llX!\n", offset);
498*4882a593Smuzhiyun return -EINVAL;
499*4882a593Smuzhiyun }
500*4882a593Smuzhiyun if ((end - start) < size) {
501*4882a593Smuzhiyun DRM_ERROR("buffer to small (%d / %d)!\n",
502*4882a593Smuzhiyun (unsigned)(end - start), size);
503*4882a593Smuzhiyun return -EINVAL;
504*4882a593Smuzhiyun }
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun return 0;
507*4882a593Smuzhiyun }
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun /**
510*4882a593Smuzhiyun * radeon_vce_validate_handle - validate stream handle
511*4882a593Smuzhiyun *
512*4882a593Smuzhiyun * @p: parser context
513*4882a593Smuzhiyun * @handle: handle to validate
514*4882a593Smuzhiyun * @allocated: allocated a new handle?
515*4882a593Smuzhiyun *
516*4882a593Smuzhiyun * Validates the handle and return the found session index or -EINVAL
517*4882a593Smuzhiyun * we we don't have another free session index.
518*4882a593Smuzhiyun */
radeon_vce_validate_handle(struct radeon_cs_parser * p,uint32_t handle,bool * allocated)519*4882a593Smuzhiyun static int radeon_vce_validate_handle(struct radeon_cs_parser *p,
520*4882a593Smuzhiyun uint32_t handle, bool *allocated)
521*4882a593Smuzhiyun {
522*4882a593Smuzhiyun unsigned i;
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun *allocated = false;
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun /* validate the handle */
527*4882a593Smuzhiyun for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) {
528*4882a593Smuzhiyun if (atomic_read(&p->rdev->vce.handles[i]) == handle) {
529*4882a593Smuzhiyun if (p->rdev->vce.filp[i] != p->filp) {
530*4882a593Smuzhiyun DRM_ERROR("VCE handle collision detected!\n");
531*4882a593Smuzhiyun return -EINVAL;
532*4882a593Smuzhiyun }
533*4882a593Smuzhiyun return i;
534*4882a593Smuzhiyun }
535*4882a593Smuzhiyun }
536*4882a593Smuzhiyun
537*4882a593Smuzhiyun /* handle not found try to alloc a new one */
538*4882a593Smuzhiyun for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) {
539*4882a593Smuzhiyun if (!atomic_cmpxchg(&p->rdev->vce.handles[i], 0, handle)) {
540*4882a593Smuzhiyun p->rdev->vce.filp[i] = p->filp;
541*4882a593Smuzhiyun p->rdev->vce.img_size[i] = 0;
542*4882a593Smuzhiyun *allocated = true;
543*4882a593Smuzhiyun return i;
544*4882a593Smuzhiyun }
545*4882a593Smuzhiyun }
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun DRM_ERROR("No more free VCE handles!\n");
548*4882a593Smuzhiyun return -EINVAL;
549*4882a593Smuzhiyun }
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun /**
552*4882a593Smuzhiyun * radeon_vce_cs_parse - parse and validate the command stream
553*4882a593Smuzhiyun *
554*4882a593Smuzhiyun * @p: parser context
555*4882a593Smuzhiyun *
556*4882a593Smuzhiyun */
radeon_vce_cs_parse(struct radeon_cs_parser * p)557*4882a593Smuzhiyun int radeon_vce_cs_parse(struct radeon_cs_parser *p)
558*4882a593Smuzhiyun {
559*4882a593Smuzhiyun int session_idx = -1;
560*4882a593Smuzhiyun bool destroyed = false, created = false, allocated = false;
561*4882a593Smuzhiyun uint32_t tmp, handle = 0;
562*4882a593Smuzhiyun uint32_t *size = &tmp;
563*4882a593Smuzhiyun int i, r = 0;
564*4882a593Smuzhiyun
565*4882a593Smuzhiyun while (p->idx < p->chunk_ib->length_dw) {
566*4882a593Smuzhiyun uint32_t len = radeon_get_ib_value(p, p->idx);
567*4882a593Smuzhiyun uint32_t cmd = radeon_get_ib_value(p, p->idx + 1);
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun if ((len < 8) || (len & 3)) {
570*4882a593Smuzhiyun DRM_ERROR("invalid VCE command length (%d)!\n", len);
571*4882a593Smuzhiyun r = -EINVAL;
572*4882a593Smuzhiyun goto out;
573*4882a593Smuzhiyun }
574*4882a593Smuzhiyun
575*4882a593Smuzhiyun if (destroyed) {
576*4882a593Smuzhiyun DRM_ERROR("No other command allowed after destroy!\n");
577*4882a593Smuzhiyun r = -EINVAL;
578*4882a593Smuzhiyun goto out;
579*4882a593Smuzhiyun }
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun switch (cmd) {
582*4882a593Smuzhiyun case 0x00000001: // session
583*4882a593Smuzhiyun handle = radeon_get_ib_value(p, p->idx + 2);
584*4882a593Smuzhiyun session_idx = radeon_vce_validate_handle(p, handle,
585*4882a593Smuzhiyun &allocated);
586*4882a593Smuzhiyun if (session_idx < 0)
587*4882a593Smuzhiyun return session_idx;
588*4882a593Smuzhiyun size = &p->rdev->vce.img_size[session_idx];
589*4882a593Smuzhiyun break;
590*4882a593Smuzhiyun
591*4882a593Smuzhiyun case 0x00000002: // task info
592*4882a593Smuzhiyun break;
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun case 0x01000001: // create
595*4882a593Smuzhiyun created = true;
596*4882a593Smuzhiyun if (!allocated) {
597*4882a593Smuzhiyun DRM_ERROR("Handle already in use!\n");
598*4882a593Smuzhiyun r = -EINVAL;
599*4882a593Smuzhiyun goto out;
600*4882a593Smuzhiyun }
601*4882a593Smuzhiyun
602*4882a593Smuzhiyun *size = radeon_get_ib_value(p, p->idx + 8) *
603*4882a593Smuzhiyun radeon_get_ib_value(p, p->idx + 10) *
604*4882a593Smuzhiyun 8 * 3 / 2;
605*4882a593Smuzhiyun break;
606*4882a593Smuzhiyun
607*4882a593Smuzhiyun case 0x04000001: // config extension
608*4882a593Smuzhiyun case 0x04000002: // pic control
609*4882a593Smuzhiyun case 0x04000005: // rate control
610*4882a593Smuzhiyun case 0x04000007: // motion estimation
611*4882a593Smuzhiyun case 0x04000008: // rdo
612*4882a593Smuzhiyun case 0x04000009: // vui
613*4882a593Smuzhiyun break;
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun case 0x03000001: // encode
616*4882a593Smuzhiyun r = radeon_vce_cs_reloc(p, p->idx + 10, p->idx + 9,
617*4882a593Smuzhiyun *size);
618*4882a593Smuzhiyun if (r)
619*4882a593Smuzhiyun goto out;
620*4882a593Smuzhiyun
621*4882a593Smuzhiyun r = radeon_vce_cs_reloc(p, p->idx + 12, p->idx + 11,
622*4882a593Smuzhiyun *size / 3);
623*4882a593Smuzhiyun if (r)
624*4882a593Smuzhiyun goto out;
625*4882a593Smuzhiyun break;
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun case 0x02000001: // destroy
628*4882a593Smuzhiyun destroyed = true;
629*4882a593Smuzhiyun break;
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun case 0x05000001: // context buffer
632*4882a593Smuzhiyun r = radeon_vce_cs_reloc(p, p->idx + 3, p->idx + 2,
633*4882a593Smuzhiyun *size * 2);
634*4882a593Smuzhiyun if (r)
635*4882a593Smuzhiyun goto out;
636*4882a593Smuzhiyun break;
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun case 0x05000004: // video bitstream buffer
639*4882a593Smuzhiyun tmp = radeon_get_ib_value(p, p->idx + 4);
640*4882a593Smuzhiyun r = radeon_vce_cs_reloc(p, p->idx + 3, p->idx + 2,
641*4882a593Smuzhiyun tmp);
642*4882a593Smuzhiyun if (r)
643*4882a593Smuzhiyun goto out;
644*4882a593Smuzhiyun break;
645*4882a593Smuzhiyun
646*4882a593Smuzhiyun case 0x05000005: // feedback buffer
647*4882a593Smuzhiyun r = radeon_vce_cs_reloc(p, p->idx + 3, p->idx + 2,
648*4882a593Smuzhiyun 4096);
649*4882a593Smuzhiyun if (r)
650*4882a593Smuzhiyun goto out;
651*4882a593Smuzhiyun break;
652*4882a593Smuzhiyun
653*4882a593Smuzhiyun default:
654*4882a593Smuzhiyun DRM_ERROR("invalid VCE command (0x%x)!\n", cmd);
655*4882a593Smuzhiyun r = -EINVAL;
656*4882a593Smuzhiyun goto out;
657*4882a593Smuzhiyun }
658*4882a593Smuzhiyun
659*4882a593Smuzhiyun if (session_idx == -1) {
660*4882a593Smuzhiyun DRM_ERROR("no session command at start of IB\n");
661*4882a593Smuzhiyun r = -EINVAL;
662*4882a593Smuzhiyun goto out;
663*4882a593Smuzhiyun }
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun p->idx += len / 4;
666*4882a593Smuzhiyun }
667*4882a593Smuzhiyun
668*4882a593Smuzhiyun if (allocated && !created) {
669*4882a593Smuzhiyun DRM_ERROR("New session without create command!\n");
670*4882a593Smuzhiyun r = -ENOENT;
671*4882a593Smuzhiyun }
672*4882a593Smuzhiyun
673*4882a593Smuzhiyun out:
674*4882a593Smuzhiyun if ((!r && destroyed) || (r && allocated)) {
675*4882a593Smuzhiyun /*
676*4882a593Smuzhiyun * IB contains a destroy msg or we have allocated an
677*4882a593Smuzhiyun * handle and got an error, anyway free the handle
678*4882a593Smuzhiyun */
679*4882a593Smuzhiyun for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i)
680*4882a593Smuzhiyun atomic_cmpxchg(&p->rdev->vce.handles[i], handle, 0);
681*4882a593Smuzhiyun }
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun return r;
684*4882a593Smuzhiyun }
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun /**
687*4882a593Smuzhiyun * radeon_vce_semaphore_emit - emit a semaphore command
688*4882a593Smuzhiyun *
689*4882a593Smuzhiyun * @rdev: radeon_device pointer
690*4882a593Smuzhiyun * @ring: engine to use
691*4882a593Smuzhiyun * @semaphore: address of semaphore
692*4882a593Smuzhiyun * @emit_wait: true=emit wait, false=emit signal
693*4882a593Smuzhiyun *
694*4882a593Smuzhiyun */
radeon_vce_semaphore_emit(struct radeon_device * rdev,struct radeon_ring * ring,struct radeon_semaphore * semaphore,bool emit_wait)695*4882a593Smuzhiyun bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
696*4882a593Smuzhiyun struct radeon_ring *ring,
697*4882a593Smuzhiyun struct radeon_semaphore *semaphore,
698*4882a593Smuzhiyun bool emit_wait)
699*4882a593Smuzhiyun {
700*4882a593Smuzhiyun uint64_t addr = semaphore->gpu_addr;
701*4882a593Smuzhiyun
702*4882a593Smuzhiyun radeon_ring_write(ring, cpu_to_le32(VCE_CMD_SEMAPHORE));
703*4882a593Smuzhiyun radeon_ring_write(ring, cpu_to_le32((addr >> 3) & 0x000FFFFF));
704*4882a593Smuzhiyun radeon_ring_write(ring, cpu_to_le32((addr >> 23) & 0x000FFFFF));
705*4882a593Smuzhiyun radeon_ring_write(ring, cpu_to_le32(0x01003000 | (emit_wait ? 1 : 0)));
706*4882a593Smuzhiyun if (!emit_wait)
707*4882a593Smuzhiyun radeon_ring_write(ring, cpu_to_le32(VCE_CMD_END));
708*4882a593Smuzhiyun
709*4882a593Smuzhiyun return true;
710*4882a593Smuzhiyun }
711*4882a593Smuzhiyun
712*4882a593Smuzhiyun /**
713*4882a593Smuzhiyun * radeon_vce_ib_execute - execute indirect buffer
714*4882a593Smuzhiyun *
715*4882a593Smuzhiyun * @rdev: radeon_device pointer
716*4882a593Smuzhiyun * @ib: the IB to execute
717*4882a593Smuzhiyun *
718*4882a593Smuzhiyun */
radeon_vce_ib_execute(struct radeon_device * rdev,struct radeon_ib * ib)719*4882a593Smuzhiyun void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
720*4882a593Smuzhiyun {
721*4882a593Smuzhiyun struct radeon_ring *ring = &rdev->ring[ib->ring];
722*4882a593Smuzhiyun radeon_ring_write(ring, cpu_to_le32(VCE_CMD_IB));
723*4882a593Smuzhiyun radeon_ring_write(ring, cpu_to_le32(ib->gpu_addr));
724*4882a593Smuzhiyun radeon_ring_write(ring, cpu_to_le32(upper_32_bits(ib->gpu_addr)));
725*4882a593Smuzhiyun radeon_ring_write(ring, cpu_to_le32(ib->length_dw));
726*4882a593Smuzhiyun }
727*4882a593Smuzhiyun
728*4882a593Smuzhiyun /**
729*4882a593Smuzhiyun * radeon_vce_fence_emit - add a fence command to the ring
730*4882a593Smuzhiyun *
731*4882a593Smuzhiyun * @rdev: radeon_device pointer
732*4882a593Smuzhiyun * @fence: the fence
733*4882a593Smuzhiyun *
734*4882a593Smuzhiyun */
radeon_vce_fence_emit(struct radeon_device * rdev,struct radeon_fence * fence)735*4882a593Smuzhiyun void radeon_vce_fence_emit(struct radeon_device *rdev,
736*4882a593Smuzhiyun struct radeon_fence *fence)
737*4882a593Smuzhiyun {
738*4882a593Smuzhiyun struct radeon_ring *ring = &rdev->ring[fence->ring];
739*4882a593Smuzhiyun uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr;
740*4882a593Smuzhiyun
741*4882a593Smuzhiyun radeon_ring_write(ring, cpu_to_le32(VCE_CMD_FENCE));
742*4882a593Smuzhiyun radeon_ring_write(ring, cpu_to_le32(addr));
743*4882a593Smuzhiyun radeon_ring_write(ring, cpu_to_le32(upper_32_bits(addr)));
744*4882a593Smuzhiyun radeon_ring_write(ring, cpu_to_le32(fence->seq));
745*4882a593Smuzhiyun radeon_ring_write(ring, cpu_to_le32(VCE_CMD_TRAP));
746*4882a593Smuzhiyun radeon_ring_write(ring, cpu_to_le32(VCE_CMD_END));
747*4882a593Smuzhiyun }
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun /**
750*4882a593Smuzhiyun * radeon_vce_ring_test - test if VCE ring is working
751*4882a593Smuzhiyun *
752*4882a593Smuzhiyun * @rdev: radeon_device pointer
753*4882a593Smuzhiyun * @ring: the engine to test on
754*4882a593Smuzhiyun *
755*4882a593Smuzhiyun */
radeon_vce_ring_test(struct radeon_device * rdev,struct radeon_ring * ring)756*4882a593Smuzhiyun int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
757*4882a593Smuzhiyun {
758*4882a593Smuzhiyun uint32_t rptr = vce_v1_0_get_rptr(rdev, ring);
759*4882a593Smuzhiyun unsigned i;
760*4882a593Smuzhiyun int r;
761*4882a593Smuzhiyun
762*4882a593Smuzhiyun r = radeon_ring_lock(rdev, ring, 16);
763*4882a593Smuzhiyun if (r) {
764*4882a593Smuzhiyun DRM_ERROR("radeon: vce failed to lock ring %d (%d).\n",
765*4882a593Smuzhiyun ring->idx, r);
766*4882a593Smuzhiyun return r;
767*4882a593Smuzhiyun }
768*4882a593Smuzhiyun radeon_ring_write(ring, cpu_to_le32(VCE_CMD_END));
769*4882a593Smuzhiyun radeon_ring_unlock_commit(rdev, ring, false);
770*4882a593Smuzhiyun
771*4882a593Smuzhiyun for (i = 0; i < rdev->usec_timeout; i++) {
772*4882a593Smuzhiyun if (vce_v1_0_get_rptr(rdev, ring) != rptr)
773*4882a593Smuzhiyun break;
774*4882a593Smuzhiyun udelay(1);
775*4882a593Smuzhiyun }
776*4882a593Smuzhiyun
777*4882a593Smuzhiyun if (i < rdev->usec_timeout) {
778*4882a593Smuzhiyun DRM_INFO("ring test on %d succeeded in %d usecs\n",
779*4882a593Smuzhiyun ring->idx, i);
780*4882a593Smuzhiyun } else {
781*4882a593Smuzhiyun DRM_ERROR("radeon: ring %d test failed\n",
782*4882a593Smuzhiyun ring->idx);
783*4882a593Smuzhiyun r = -ETIMEDOUT;
784*4882a593Smuzhiyun }
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun return r;
787*4882a593Smuzhiyun }
788*4882a593Smuzhiyun
789*4882a593Smuzhiyun /**
790*4882a593Smuzhiyun * radeon_vce_ib_test - test if VCE IBs are working
791*4882a593Smuzhiyun *
792*4882a593Smuzhiyun * @rdev: radeon_device pointer
793*4882a593Smuzhiyun * @ring: the engine to test on
794*4882a593Smuzhiyun *
795*4882a593Smuzhiyun */
radeon_vce_ib_test(struct radeon_device * rdev,struct radeon_ring * ring)796*4882a593Smuzhiyun int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
797*4882a593Smuzhiyun {
798*4882a593Smuzhiyun struct radeon_fence *fence = NULL;
799*4882a593Smuzhiyun int r;
800*4882a593Smuzhiyun
801*4882a593Smuzhiyun r = radeon_vce_get_create_msg(rdev, ring->idx, 1, NULL);
802*4882a593Smuzhiyun if (r) {
803*4882a593Smuzhiyun DRM_ERROR("radeon: failed to get create msg (%d).\n", r);
804*4882a593Smuzhiyun goto error;
805*4882a593Smuzhiyun }
806*4882a593Smuzhiyun
807*4882a593Smuzhiyun r = radeon_vce_get_destroy_msg(rdev, ring->idx, 1, &fence);
808*4882a593Smuzhiyun if (r) {
809*4882a593Smuzhiyun DRM_ERROR("radeon: failed to get destroy ib (%d).\n", r);
810*4882a593Smuzhiyun goto error;
811*4882a593Smuzhiyun }
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun r = radeon_fence_wait_timeout(fence, false, usecs_to_jiffies(
814*4882a593Smuzhiyun RADEON_USEC_IB_TEST_TIMEOUT));
815*4882a593Smuzhiyun if (r < 0) {
816*4882a593Smuzhiyun DRM_ERROR("radeon: fence wait failed (%d).\n", r);
817*4882a593Smuzhiyun } else if (r == 0) {
818*4882a593Smuzhiyun DRM_ERROR("radeon: fence wait timed out.\n");
819*4882a593Smuzhiyun r = -ETIMEDOUT;
820*4882a593Smuzhiyun } else {
821*4882a593Smuzhiyun DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
822*4882a593Smuzhiyun r = 0;
823*4882a593Smuzhiyun }
824*4882a593Smuzhiyun error:
825*4882a593Smuzhiyun radeon_fence_unref(&fence);
826*4882a593Smuzhiyun return r;
827*4882a593Smuzhiyun }
828