1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2009 Jerome Glisse.
3*4882a593Smuzhiyun * All Rights Reserved.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a
6*4882a593Smuzhiyun * copy of this software and associated documentation files (the
7*4882a593Smuzhiyun * "Software"), to deal in the Software without restriction, including
8*4882a593Smuzhiyun * without limitation the rights to use, copy, modify, merge, publish,
9*4882a593Smuzhiyun * distribute, sub license, and/or sell copies of the Software, and to
10*4882a593Smuzhiyun * permit persons to whom the Software is furnished to do so, subject to
11*4882a593Smuzhiyun * the following conditions:
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16*4882a593Smuzhiyun * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17*4882a593Smuzhiyun * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18*4882a593Smuzhiyun * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19*4882a593Smuzhiyun * USE OR OTHER DEALINGS IN THE SOFTWARE.
20*4882a593Smuzhiyun *
21*4882a593Smuzhiyun * The above copyright notice and this permission notice (including the
22*4882a593Smuzhiyun * next paragraph) shall be included in all copies or substantial portions
23*4882a593Smuzhiyun * of the Software.
24*4882a593Smuzhiyun *
25*4882a593Smuzhiyun */
26*4882a593Smuzhiyun /*
27*4882a593Smuzhiyun * Authors:
28*4882a593Smuzhiyun * Jerome Glisse <glisse@freedesktop.org>
29*4882a593Smuzhiyun * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30*4882a593Smuzhiyun * Dave Airlie
31*4882a593Smuzhiyun */
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #include <linux/dma-mapping.h>
34*4882a593Smuzhiyun #include <linux/pagemap.h>
35*4882a593Smuzhiyun #include <linux/pci.h>
36*4882a593Smuzhiyun #include <linux/seq_file.h>
37*4882a593Smuzhiyun #include <linux/slab.h>
38*4882a593Smuzhiyun #include <linux/swap.h>
39*4882a593Smuzhiyun #include <linux/swiotlb.h>
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #include <drm/drm_agpsupport.h>
42*4882a593Smuzhiyun #include <drm/drm_debugfs.h>
43*4882a593Smuzhiyun #include <drm/drm_device.h>
44*4882a593Smuzhiyun #include <drm/drm_file.h>
45*4882a593Smuzhiyun #include <drm/drm_prime.h>
46*4882a593Smuzhiyun #include <drm/radeon_drm.h>
47*4882a593Smuzhiyun #include <drm/ttm/ttm_bo_api.h>
48*4882a593Smuzhiyun #include <drm/ttm/ttm_bo_driver.h>
49*4882a593Smuzhiyun #include <drm/ttm/ttm_module.h>
50*4882a593Smuzhiyun #include <drm/ttm/ttm_page_alloc.h>
51*4882a593Smuzhiyun #include <drm/ttm/ttm_placement.h>
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun #include "radeon_reg.h"
54*4882a593Smuzhiyun #include "radeon.h"
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
57*4882a593Smuzhiyun static void radeon_ttm_debugfs_fini(struct radeon_device *rdev);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun static int radeon_ttm_tt_bind(struct ttm_bo_device *bdev,
60*4882a593Smuzhiyun struct ttm_tt *ttm,
61*4882a593Smuzhiyun struct ttm_resource *bo_mem);
62*4882a593Smuzhiyun
radeon_get_rdev(struct ttm_bo_device * bdev)63*4882a593Smuzhiyun struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun struct radeon_mman *mman;
66*4882a593Smuzhiyun struct radeon_device *rdev;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun mman = container_of(bdev, struct radeon_mman, bdev);
69*4882a593Smuzhiyun rdev = container_of(mman, struct radeon_device, mman);
70*4882a593Smuzhiyun return rdev;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
radeon_ttm_init_vram(struct radeon_device * rdev)73*4882a593Smuzhiyun static int radeon_ttm_init_vram(struct radeon_device *rdev)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun return ttm_range_man_init(&rdev->mman.bdev, TTM_PL_VRAM,
76*4882a593Smuzhiyun false, rdev->mc.real_vram_size >> PAGE_SHIFT);
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
radeon_ttm_init_gtt(struct radeon_device * rdev)79*4882a593Smuzhiyun static int radeon_ttm_init_gtt(struct radeon_device *rdev)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun return ttm_range_man_init(&rdev->mman.bdev, TTM_PL_TT,
82*4882a593Smuzhiyun true, rdev->mc.gtt_size >> PAGE_SHIFT);
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
radeon_evict_flags(struct ttm_buffer_object * bo,struct ttm_placement * placement)85*4882a593Smuzhiyun static void radeon_evict_flags(struct ttm_buffer_object *bo,
86*4882a593Smuzhiyun struct ttm_placement *placement)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun static const struct ttm_place placements = {
89*4882a593Smuzhiyun .fpfn = 0,
90*4882a593Smuzhiyun .lpfn = 0,
91*4882a593Smuzhiyun .mem_type = TTM_PL_SYSTEM,
92*4882a593Smuzhiyun .flags = TTM_PL_MASK_CACHING
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun struct radeon_bo *rbo;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun if (!radeon_ttm_bo_is_radeon_bo(bo)) {
98*4882a593Smuzhiyun placement->placement = &placements;
99*4882a593Smuzhiyun placement->busy_placement = &placements;
100*4882a593Smuzhiyun placement->num_placement = 1;
101*4882a593Smuzhiyun placement->num_busy_placement = 1;
102*4882a593Smuzhiyun return;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun rbo = container_of(bo, struct radeon_bo, tbo);
105*4882a593Smuzhiyun switch (bo->mem.mem_type) {
106*4882a593Smuzhiyun case TTM_PL_VRAM:
107*4882a593Smuzhiyun if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false)
108*4882a593Smuzhiyun radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
109*4882a593Smuzhiyun else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size &&
110*4882a593Smuzhiyun bo->mem.start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) {
111*4882a593Smuzhiyun unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
112*4882a593Smuzhiyun int i;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /* Try evicting to the CPU inaccessible part of VRAM
115*4882a593Smuzhiyun * first, but only set GTT as busy placement, so this
116*4882a593Smuzhiyun * BO will be evicted to GTT rather than causing other
117*4882a593Smuzhiyun * BOs to be evicted from VRAM
118*4882a593Smuzhiyun */
119*4882a593Smuzhiyun radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM |
120*4882a593Smuzhiyun RADEON_GEM_DOMAIN_GTT);
121*4882a593Smuzhiyun rbo->placement.num_busy_placement = 0;
122*4882a593Smuzhiyun for (i = 0; i < rbo->placement.num_placement; i++) {
123*4882a593Smuzhiyun if (rbo->placements[i].mem_type == TTM_PL_VRAM) {
124*4882a593Smuzhiyun if (rbo->placements[i].fpfn < fpfn)
125*4882a593Smuzhiyun rbo->placements[i].fpfn = fpfn;
126*4882a593Smuzhiyun } else {
127*4882a593Smuzhiyun rbo->placement.busy_placement =
128*4882a593Smuzhiyun &rbo->placements[i];
129*4882a593Smuzhiyun rbo->placement.num_busy_placement = 1;
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun } else
133*4882a593Smuzhiyun radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
134*4882a593Smuzhiyun break;
135*4882a593Smuzhiyun case TTM_PL_TT:
136*4882a593Smuzhiyun default:
137*4882a593Smuzhiyun radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun *placement = rbo->placement;
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun
radeon_verify_access(struct ttm_buffer_object * bo,struct file * filp)142*4882a593Smuzhiyun static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
145*4882a593Smuzhiyun struct radeon_device *rdev = radeon_get_rdev(bo->bdev);
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun if (radeon_ttm_tt_has_userptr(rdev, bo->ttm))
148*4882a593Smuzhiyun return -EPERM;
149*4882a593Smuzhiyun return drm_vma_node_verify_access(&rbo->tbo.base.vma_node,
150*4882a593Smuzhiyun filp->private_data);
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
radeon_move_blit(struct ttm_buffer_object * bo,bool evict,bool no_wait_gpu,struct ttm_resource * new_mem,struct ttm_resource * old_mem)153*4882a593Smuzhiyun static int radeon_move_blit(struct ttm_buffer_object *bo,
154*4882a593Smuzhiyun bool evict, bool no_wait_gpu,
155*4882a593Smuzhiyun struct ttm_resource *new_mem,
156*4882a593Smuzhiyun struct ttm_resource *old_mem)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun struct radeon_device *rdev;
159*4882a593Smuzhiyun uint64_t old_start, new_start;
160*4882a593Smuzhiyun struct radeon_fence *fence;
161*4882a593Smuzhiyun unsigned num_pages;
162*4882a593Smuzhiyun int r, ridx;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun rdev = radeon_get_rdev(bo->bdev);
165*4882a593Smuzhiyun ridx = radeon_copy_ring_index(rdev);
166*4882a593Smuzhiyun old_start = (u64)old_mem->start << PAGE_SHIFT;
167*4882a593Smuzhiyun new_start = (u64)new_mem->start << PAGE_SHIFT;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun switch (old_mem->mem_type) {
170*4882a593Smuzhiyun case TTM_PL_VRAM:
171*4882a593Smuzhiyun old_start += rdev->mc.vram_start;
172*4882a593Smuzhiyun break;
173*4882a593Smuzhiyun case TTM_PL_TT:
174*4882a593Smuzhiyun old_start += rdev->mc.gtt_start;
175*4882a593Smuzhiyun break;
176*4882a593Smuzhiyun default:
177*4882a593Smuzhiyun DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
178*4882a593Smuzhiyun return -EINVAL;
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun switch (new_mem->mem_type) {
181*4882a593Smuzhiyun case TTM_PL_VRAM:
182*4882a593Smuzhiyun new_start += rdev->mc.vram_start;
183*4882a593Smuzhiyun break;
184*4882a593Smuzhiyun case TTM_PL_TT:
185*4882a593Smuzhiyun new_start += rdev->mc.gtt_start;
186*4882a593Smuzhiyun break;
187*4882a593Smuzhiyun default:
188*4882a593Smuzhiyun DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
189*4882a593Smuzhiyun return -EINVAL;
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun if (!rdev->ring[ridx].ready) {
192*4882a593Smuzhiyun DRM_ERROR("Trying to move memory with ring turned off.\n");
193*4882a593Smuzhiyun return -EINVAL;
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun num_pages = new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
199*4882a593Smuzhiyun fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->base.resv);
200*4882a593Smuzhiyun if (IS_ERR(fence))
201*4882a593Smuzhiyun return PTR_ERR(fence);
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun r = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, false, new_mem);
204*4882a593Smuzhiyun radeon_fence_unref(&fence);
205*4882a593Smuzhiyun return r;
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun
radeon_move_vram_ram(struct ttm_buffer_object * bo,bool evict,bool interruptible,bool no_wait_gpu,struct ttm_resource * new_mem)208*4882a593Smuzhiyun static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
209*4882a593Smuzhiyun bool evict, bool interruptible,
210*4882a593Smuzhiyun bool no_wait_gpu,
211*4882a593Smuzhiyun struct ttm_resource *new_mem)
212*4882a593Smuzhiyun {
213*4882a593Smuzhiyun struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
214*4882a593Smuzhiyun struct ttm_resource *old_mem = &bo->mem;
215*4882a593Smuzhiyun struct ttm_resource tmp_mem;
216*4882a593Smuzhiyun struct ttm_place placements;
217*4882a593Smuzhiyun struct ttm_placement placement;
218*4882a593Smuzhiyun int r;
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun tmp_mem = *new_mem;
221*4882a593Smuzhiyun tmp_mem.mm_node = NULL;
222*4882a593Smuzhiyun placement.num_placement = 1;
223*4882a593Smuzhiyun placement.placement = &placements;
224*4882a593Smuzhiyun placement.num_busy_placement = 1;
225*4882a593Smuzhiyun placement.busy_placement = &placements;
226*4882a593Smuzhiyun placements.fpfn = 0;
227*4882a593Smuzhiyun placements.lpfn = 0;
228*4882a593Smuzhiyun placements.mem_type = TTM_PL_TT;
229*4882a593Smuzhiyun placements.flags = TTM_PL_MASK_CACHING;
230*4882a593Smuzhiyun r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx);
231*4882a593Smuzhiyun if (unlikely(r)) {
232*4882a593Smuzhiyun return r;
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
236*4882a593Smuzhiyun if (unlikely(r)) {
237*4882a593Smuzhiyun goto out_cleanup;
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun r = ttm_tt_populate(bo->bdev, bo->ttm, &ctx);
241*4882a593Smuzhiyun if (unlikely(r)) {
242*4882a593Smuzhiyun goto out_cleanup;
243*4882a593Smuzhiyun }
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun r = radeon_ttm_tt_bind(bo->bdev, bo->ttm, &tmp_mem);
246*4882a593Smuzhiyun if (unlikely(r)) {
247*4882a593Smuzhiyun goto out_cleanup;
248*4882a593Smuzhiyun }
249*4882a593Smuzhiyun r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
250*4882a593Smuzhiyun if (unlikely(r)) {
251*4882a593Smuzhiyun goto out_cleanup;
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun r = ttm_bo_move_ttm(bo, &ctx, new_mem);
254*4882a593Smuzhiyun out_cleanup:
255*4882a593Smuzhiyun ttm_resource_free(bo, &tmp_mem);
256*4882a593Smuzhiyun return r;
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun
radeon_move_ram_vram(struct ttm_buffer_object * bo,bool evict,bool interruptible,bool no_wait_gpu,struct ttm_resource * new_mem)259*4882a593Smuzhiyun static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
260*4882a593Smuzhiyun bool evict, bool interruptible,
261*4882a593Smuzhiyun bool no_wait_gpu,
262*4882a593Smuzhiyun struct ttm_resource *new_mem)
263*4882a593Smuzhiyun {
264*4882a593Smuzhiyun struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
265*4882a593Smuzhiyun struct ttm_resource *old_mem = &bo->mem;
266*4882a593Smuzhiyun struct ttm_resource tmp_mem;
267*4882a593Smuzhiyun struct ttm_placement placement;
268*4882a593Smuzhiyun struct ttm_place placements;
269*4882a593Smuzhiyun int r;
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun tmp_mem = *new_mem;
272*4882a593Smuzhiyun tmp_mem.mm_node = NULL;
273*4882a593Smuzhiyun placement.num_placement = 1;
274*4882a593Smuzhiyun placement.placement = &placements;
275*4882a593Smuzhiyun placement.num_busy_placement = 1;
276*4882a593Smuzhiyun placement.busy_placement = &placements;
277*4882a593Smuzhiyun placements.fpfn = 0;
278*4882a593Smuzhiyun placements.lpfn = 0;
279*4882a593Smuzhiyun placements.mem_type = TTM_PL_TT;
280*4882a593Smuzhiyun placements.flags = TTM_PL_MASK_CACHING;
281*4882a593Smuzhiyun r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx);
282*4882a593Smuzhiyun if (unlikely(r)) {
283*4882a593Smuzhiyun return r;
284*4882a593Smuzhiyun }
285*4882a593Smuzhiyun r = ttm_bo_move_ttm(bo, &ctx, &tmp_mem);
286*4882a593Smuzhiyun if (unlikely(r)) {
287*4882a593Smuzhiyun goto out_cleanup;
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
290*4882a593Smuzhiyun if (unlikely(r)) {
291*4882a593Smuzhiyun goto out_cleanup;
292*4882a593Smuzhiyun }
293*4882a593Smuzhiyun out_cleanup:
294*4882a593Smuzhiyun ttm_resource_free(bo, &tmp_mem);
295*4882a593Smuzhiyun return r;
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun
radeon_bo_move(struct ttm_buffer_object * bo,bool evict,struct ttm_operation_ctx * ctx,struct ttm_resource * new_mem)298*4882a593Smuzhiyun static int radeon_bo_move(struct ttm_buffer_object *bo, bool evict,
299*4882a593Smuzhiyun struct ttm_operation_ctx *ctx,
300*4882a593Smuzhiyun struct ttm_resource *new_mem)
301*4882a593Smuzhiyun {
302*4882a593Smuzhiyun struct radeon_device *rdev;
303*4882a593Smuzhiyun struct radeon_bo *rbo;
304*4882a593Smuzhiyun struct ttm_resource *old_mem = &bo->mem;
305*4882a593Smuzhiyun int r;
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun r = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
308*4882a593Smuzhiyun if (r)
309*4882a593Smuzhiyun return r;
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun /* Can't move a pinned BO */
312*4882a593Smuzhiyun rbo = container_of(bo, struct radeon_bo, tbo);
313*4882a593Smuzhiyun if (WARN_ON_ONCE(rbo->pin_count > 0))
314*4882a593Smuzhiyun return -EINVAL;
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun rdev = radeon_get_rdev(bo->bdev);
317*4882a593Smuzhiyun if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
318*4882a593Smuzhiyun ttm_bo_move_null(bo, new_mem);
319*4882a593Smuzhiyun return 0;
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun if ((old_mem->mem_type == TTM_PL_TT &&
322*4882a593Smuzhiyun new_mem->mem_type == TTM_PL_SYSTEM) ||
323*4882a593Smuzhiyun (old_mem->mem_type == TTM_PL_SYSTEM &&
324*4882a593Smuzhiyun new_mem->mem_type == TTM_PL_TT)) {
325*4882a593Smuzhiyun /* bind is enough */
326*4882a593Smuzhiyun ttm_bo_move_null(bo, new_mem);
327*4882a593Smuzhiyun return 0;
328*4882a593Smuzhiyun }
329*4882a593Smuzhiyun if (!rdev->ring[radeon_copy_ring_index(rdev)].ready ||
330*4882a593Smuzhiyun rdev->asic->copy.copy == NULL) {
331*4882a593Smuzhiyun /* use memcpy */
332*4882a593Smuzhiyun goto memcpy;
333*4882a593Smuzhiyun }
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun if (old_mem->mem_type == TTM_PL_VRAM &&
336*4882a593Smuzhiyun new_mem->mem_type == TTM_PL_SYSTEM) {
337*4882a593Smuzhiyun r = radeon_move_vram_ram(bo, evict, ctx->interruptible,
338*4882a593Smuzhiyun ctx->no_wait_gpu, new_mem);
339*4882a593Smuzhiyun } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
340*4882a593Smuzhiyun new_mem->mem_type == TTM_PL_VRAM) {
341*4882a593Smuzhiyun r = radeon_move_ram_vram(bo, evict, ctx->interruptible,
342*4882a593Smuzhiyun ctx->no_wait_gpu, new_mem);
343*4882a593Smuzhiyun } else {
344*4882a593Smuzhiyun r = radeon_move_blit(bo, evict, ctx->no_wait_gpu,
345*4882a593Smuzhiyun new_mem, old_mem);
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun if (r) {
349*4882a593Smuzhiyun memcpy:
350*4882a593Smuzhiyun r = ttm_bo_move_memcpy(bo, ctx, new_mem);
351*4882a593Smuzhiyun if (r) {
352*4882a593Smuzhiyun return r;
353*4882a593Smuzhiyun }
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun /* update statistics */
357*4882a593Smuzhiyun atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved);
358*4882a593Smuzhiyun return 0;
359*4882a593Smuzhiyun }
360*4882a593Smuzhiyun
radeon_ttm_io_mem_reserve(struct ttm_bo_device * bdev,struct ttm_resource * mem)361*4882a593Smuzhiyun static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *mem)
362*4882a593Smuzhiyun {
363*4882a593Smuzhiyun struct radeon_device *rdev = radeon_get_rdev(bdev);
364*4882a593Smuzhiyun size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun switch (mem->mem_type) {
367*4882a593Smuzhiyun case TTM_PL_SYSTEM:
368*4882a593Smuzhiyun /* system memory */
369*4882a593Smuzhiyun return 0;
370*4882a593Smuzhiyun case TTM_PL_TT:
371*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_AGP)
372*4882a593Smuzhiyun if (rdev->flags & RADEON_IS_AGP) {
373*4882a593Smuzhiyun /* RADEON_IS_AGP is set only if AGP is active */
374*4882a593Smuzhiyun mem->bus.offset = (mem->start << PAGE_SHIFT) +
375*4882a593Smuzhiyun rdev->mc.agp_base;
376*4882a593Smuzhiyun mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture;
377*4882a593Smuzhiyun }
378*4882a593Smuzhiyun #endif
379*4882a593Smuzhiyun break;
380*4882a593Smuzhiyun case TTM_PL_VRAM:
381*4882a593Smuzhiyun mem->bus.offset = mem->start << PAGE_SHIFT;
382*4882a593Smuzhiyun /* check if it's visible */
383*4882a593Smuzhiyun if ((mem->bus.offset + bus_size) > rdev->mc.visible_vram_size)
384*4882a593Smuzhiyun return -EINVAL;
385*4882a593Smuzhiyun mem->bus.offset += rdev->mc.aper_base;
386*4882a593Smuzhiyun mem->bus.is_iomem = true;
387*4882a593Smuzhiyun #ifdef __alpha__
388*4882a593Smuzhiyun /*
389*4882a593Smuzhiyun * Alpha: use bus.addr to hold the ioremap() return,
390*4882a593Smuzhiyun * so we can modify bus.base below.
391*4882a593Smuzhiyun */
392*4882a593Smuzhiyun if (mem->placement & TTM_PL_FLAG_WC)
393*4882a593Smuzhiyun mem->bus.addr =
394*4882a593Smuzhiyun ioremap_wc(mem->bus.offset, bus_size);
395*4882a593Smuzhiyun else
396*4882a593Smuzhiyun mem->bus.addr =
397*4882a593Smuzhiyun ioremap(mem->bus.offset, bus_size);
398*4882a593Smuzhiyun if (!mem->bus.addr)
399*4882a593Smuzhiyun return -ENOMEM;
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun /*
402*4882a593Smuzhiyun * Alpha: Use just the bus offset plus
403*4882a593Smuzhiyun * the hose/domain memory base for bus.base.
404*4882a593Smuzhiyun * It then can be used to build PTEs for VRAM
405*4882a593Smuzhiyun * access, as done in ttm_bo_vm_fault().
406*4882a593Smuzhiyun */
407*4882a593Smuzhiyun mem->bus.offset = (mem->bus.offset & 0x0ffffffffUL) +
408*4882a593Smuzhiyun rdev->ddev->hose->dense_mem_base;
409*4882a593Smuzhiyun #endif
410*4882a593Smuzhiyun break;
411*4882a593Smuzhiyun default:
412*4882a593Smuzhiyun return -EINVAL;
413*4882a593Smuzhiyun }
414*4882a593Smuzhiyun return 0;
415*4882a593Smuzhiyun }
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun /*
418*4882a593Smuzhiyun * TTM backend functions.
419*4882a593Smuzhiyun */
420*4882a593Smuzhiyun struct radeon_ttm_tt {
421*4882a593Smuzhiyun struct ttm_dma_tt ttm;
422*4882a593Smuzhiyun u64 offset;
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun uint64_t userptr;
425*4882a593Smuzhiyun struct mm_struct *usermm;
426*4882a593Smuzhiyun uint32_t userflags;
427*4882a593Smuzhiyun bool bound;
428*4882a593Smuzhiyun };
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun /* prepare the sg table with the user pages */
radeon_ttm_tt_pin_userptr(struct ttm_bo_device * bdev,struct ttm_tt * ttm)431*4882a593Smuzhiyun static int radeon_ttm_tt_pin_userptr(struct ttm_bo_device *bdev, struct ttm_tt *ttm)
432*4882a593Smuzhiyun {
433*4882a593Smuzhiyun struct radeon_device *rdev = radeon_get_rdev(bdev);
434*4882a593Smuzhiyun struct radeon_ttm_tt *gtt = (void *)ttm;
435*4882a593Smuzhiyun unsigned pinned = 0;
436*4882a593Smuzhiyun int r;
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
439*4882a593Smuzhiyun enum dma_data_direction direction = write ?
440*4882a593Smuzhiyun DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun if (current->mm != gtt->usermm)
443*4882a593Smuzhiyun return -EPERM;
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) {
446*4882a593Smuzhiyun /* check that we only pin down anonymous memory
447*4882a593Smuzhiyun to prevent problems with writeback */
448*4882a593Smuzhiyun unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
449*4882a593Smuzhiyun struct vm_area_struct *vma;
450*4882a593Smuzhiyun vma = find_vma(gtt->usermm, gtt->userptr);
451*4882a593Smuzhiyun if (!vma || vma->vm_file || vma->vm_end < end)
452*4882a593Smuzhiyun return -EPERM;
453*4882a593Smuzhiyun }
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun do {
456*4882a593Smuzhiyun unsigned num_pages = ttm->num_pages - pinned;
457*4882a593Smuzhiyun uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
458*4882a593Smuzhiyun struct page **pages = ttm->pages + pinned;
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun r = get_user_pages(userptr, num_pages, write ? FOLL_WRITE : 0,
461*4882a593Smuzhiyun pages, NULL);
462*4882a593Smuzhiyun if (r < 0)
463*4882a593Smuzhiyun goto release_pages;
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun pinned += r;
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun } while (pinned < ttm->num_pages);
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
470*4882a593Smuzhiyun ttm->num_pages << PAGE_SHIFT,
471*4882a593Smuzhiyun GFP_KERNEL);
472*4882a593Smuzhiyun if (r)
473*4882a593Smuzhiyun goto release_sg;
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun r = dma_map_sgtable(rdev->dev, ttm->sg, direction, 0);
476*4882a593Smuzhiyun if (r)
477*4882a593Smuzhiyun goto release_sg;
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
480*4882a593Smuzhiyun gtt->ttm.dma_address, ttm->num_pages);
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun return 0;
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun release_sg:
485*4882a593Smuzhiyun kfree(ttm->sg);
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun release_pages:
488*4882a593Smuzhiyun release_pages(ttm->pages, pinned);
489*4882a593Smuzhiyun return r;
490*4882a593Smuzhiyun }
491*4882a593Smuzhiyun
radeon_ttm_tt_unpin_userptr(struct ttm_bo_device * bdev,struct ttm_tt * ttm)492*4882a593Smuzhiyun static void radeon_ttm_tt_unpin_userptr(struct ttm_bo_device *bdev, struct ttm_tt *ttm)
493*4882a593Smuzhiyun {
494*4882a593Smuzhiyun struct radeon_device *rdev = radeon_get_rdev(bdev);
495*4882a593Smuzhiyun struct radeon_ttm_tt *gtt = (void *)ttm;
496*4882a593Smuzhiyun struct sg_page_iter sg_iter;
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
499*4882a593Smuzhiyun enum dma_data_direction direction = write ?
500*4882a593Smuzhiyun DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun /* double check that we don't free the table twice */
503*4882a593Smuzhiyun if (!ttm->sg->sgl)
504*4882a593Smuzhiyun return;
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun /* free the sg table and pages again */
507*4882a593Smuzhiyun dma_unmap_sgtable(rdev->dev, ttm->sg, direction, 0);
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun for_each_sgtable_page(ttm->sg, &sg_iter, 0) {
510*4882a593Smuzhiyun struct page *page = sg_page_iter_page(&sg_iter);
511*4882a593Smuzhiyun if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY))
512*4882a593Smuzhiyun set_page_dirty(page);
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun mark_page_accessed(page);
515*4882a593Smuzhiyun put_page(page);
516*4882a593Smuzhiyun }
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun sg_free_table(ttm->sg);
519*4882a593Smuzhiyun }
520*4882a593Smuzhiyun
radeon_ttm_backend_is_bound(struct ttm_tt * ttm)521*4882a593Smuzhiyun static bool radeon_ttm_backend_is_bound(struct ttm_tt *ttm)
522*4882a593Smuzhiyun {
523*4882a593Smuzhiyun struct radeon_ttm_tt *gtt = (void*)ttm;
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun return (gtt->bound);
526*4882a593Smuzhiyun }
527*4882a593Smuzhiyun
radeon_ttm_backend_bind(struct ttm_bo_device * bdev,struct ttm_tt * ttm,struct ttm_resource * bo_mem)528*4882a593Smuzhiyun static int radeon_ttm_backend_bind(struct ttm_bo_device *bdev,
529*4882a593Smuzhiyun struct ttm_tt *ttm,
530*4882a593Smuzhiyun struct ttm_resource *bo_mem)
531*4882a593Smuzhiyun {
532*4882a593Smuzhiyun struct radeon_ttm_tt *gtt = (void*)ttm;
533*4882a593Smuzhiyun struct radeon_device *rdev = radeon_get_rdev(bdev);
534*4882a593Smuzhiyun uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ |
535*4882a593Smuzhiyun RADEON_GART_PAGE_WRITE;
536*4882a593Smuzhiyun int r;
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun if (gtt->bound)
539*4882a593Smuzhiyun return 0;
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun if (gtt->userptr) {
542*4882a593Smuzhiyun radeon_ttm_tt_pin_userptr(bdev, ttm);
543*4882a593Smuzhiyun flags &= ~RADEON_GART_PAGE_WRITE;
544*4882a593Smuzhiyun }
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
547*4882a593Smuzhiyun if (!ttm->num_pages) {
548*4882a593Smuzhiyun WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
549*4882a593Smuzhiyun ttm->num_pages, bo_mem, ttm);
550*4882a593Smuzhiyun }
551*4882a593Smuzhiyun if (ttm->caching_state == tt_cached)
552*4882a593Smuzhiyun flags |= RADEON_GART_PAGE_SNOOP;
553*4882a593Smuzhiyun r = radeon_gart_bind(rdev, gtt->offset, ttm->num_pages,
554*4882a593Smuzhiyun ttm->pages, gtt->ttm.dma_address, flags);
555*4882a593Smuzhiyun if (r) {
556*4882a593Smuzhiyun DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
557*4882a593Smuzhiyun ttm->num_pages, (unsigned)gtt->offset);
558*4882a593Smuzhiyun return r;
559*4882a593Smuzhiyun }
560*4882a593Smuzhiyun gtt->bound = true;
561*4882a593Smuzhiyun return 0;
562*4882a593Smuzhiyun }
563*4882a593Smuzhiyun
radeon_ttm_backend_unbind(struct ttm_bo_device * bdev,struct ttm_tt * ttm)564*4882a593Smuzhiyun static void radeon_ttm_backend_unbind(struct ttm_bo_device *bdev, struct ttm_tt *ttm)
565*4882a593Smuzhiyun {
566*4882a593Smuzhiyun struct radeon_ttm_tt *gtt = (void *)ttm;
567*4882a593Smuzhiyun struct radeon_device *rdev = radeon_get_rdev(bdev);
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun if (gtt->userptr)
570*4882a593Smuzhiyun radeon_ttm_tt_unpin_userptr(bdev, ttm);
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun if (!gtt->bound)
573*4882a593Smuzhiyun return;
574*4882a593Smuzhiyun
575*4882a593Smuzhiyun radeon_gart_unbind(rdev, gtt->offset, ttm->num_pages);
576*4882a593Smuzhiyun
577*4882a593Smuzhiyun gtt->bound = false;
578*4882a593Smuzhiyun }
579*4882a593Smuzhiyun
radeon_ttm_backend_destroy(struct ttm_bo_device * bdev,struct ttm_tt * ttm)580*4882a593Smuzhiyun static void radeon_ttm_backend_destroy(struct ttm_bo_device *bdev, struct ttm_tt *ttm)
581*4882a593Smuzhiyun {
582*4882a593Smuzhiyun struct radeon_ttm_tt *gtt = (void *)ttm;
583*4882a593Smuzhiyun
584*4882a593Smuzhiyun radeon_ttm_backend_unbind(bdev, ttm);
585*4882a593Smuzhiyun ttm_tt_destroy_common(bdev, ttm);
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun ttm_dma_tt_fini(>t->ttm);
588*4882a593Smuzhiyun kfree(gtt);
589*4882a593Smuzhiyun }
590*4882a593Smuzhiyun
radeon_ttm_tt_create(struct ttm_buffer_object * bo,uint32_t page_flags)591*4882a593Smuzhiyun static struct ttm_tt *radeon_ttm_tt_create(struct ttm_buffer_object *bo,
592*4882a593Smuzhiyun uint32_t page_flags)
593*4882a593Smuzhiyun {
594*4882a593Smuzhiyun struct radeon_device *rdev;
595*4882a593Smuzhiyun struct radeon_ttm_tt *gtt;
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun rdev = radeon_get_rdev(bo->bdev);
598*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_AGP)
599*4882a593Smuzhiyun if (rdev->flags & RADEON_IS_AGP) {
600*4882a593Smuzhiyun return ttm_agp_tt_create(bo, rdev->ddev->agp->bridge,
601*4882a593Smuzhiyun page_flags);
602*4882a593Smuzhiyun }
603*4882a593Smuzhiyun #endif
604*4882a593Smuzhiyun
605*4882a593Smuzhiyun gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL);
606*4882a593Smuzhiyun if (gtt == NULL) {
607*4882a593Smuzhiyun return NULL;
608*4882a593Smuzhiyun }
609*4882a593Smuzhiyun if (ttm_dma_tt_init(>t->ttm, bo, page_flags)) {
610*4882a593Smuzhiyun kfree(gtt);
611*4882a593Smuzhiyun return NULL;
612*4882a593Smuzhiyun }
613*4882a593Smuzhiyun return >t->ttm.ttm;
614*4882a593Smuzhiyun }
615*4882a593Smuzhiyun
radeon_ttm_tt_to_gtt(struct radeon_device * rdev,struct ttm_tt * ttm)616*4882a593Smuzhiyun static struct radeon_ttm_tt *radeon_ttm_tt_to_gtt(struct radeon_device *rdev,
617*4882a593Smuzhiyun struct ttm_tt *ttm)
618*4882a593Smuzhiyun {
619*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_AGP)
620*4882a593Smuzhiyun if (rdev->flags & RADEON_IS_AGP)
621*4882a593Smuzhiyun return NULL;
622*4882a593Smuzhiyun #endif
623*4882a593Smuzhiyun
624*4882a593Smuzhiyun if (!ttm)
625*4882a593Smuzhiyun return NULL;
626*4882a593Smuzhiyun return container_of(ttm, struct radeon_ttm_tt, ttm.ttm);
627*4882a593Smuzhiyun }
628*4882a593Smuzhiyun
radeon_ttm_tt_populate(struct ttm_bo_device * bdev,struct ttm_tt * ttm,struct ttm_operation_ctx * ctx)629*4882a593Smuzhiyun static int radeon_ttm_tt_populate(struct ttm_bo_device *bdev,
630*4882a593Smuzhiyun struct ttm_tt *ttm,
631*4882a593Smuzhiyun struct ttm_operation_ctx *ctx)
632*4882a593Smuzhiyun {
633*4882a593Smuzhiyun struct radeon_device *rdev = radeon_get_rdev(bdev);
634*4882a593Smuzhiyun struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm);
635*4882a593Smuzhiyun bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
636*4882a593Smuzhiyun
637*4882a593Smuzhiyun if (gtt && gtt->userptr) {
638*4882a593Smuzhiyun ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
639*4882a593Smuzhiyun if (!ttm->sg)
640*4882a593Smuzhiyun return -ENOMEM;
641*4882a593Smuzhiyun
642*4882a593Smuzhiyun ttm->page_flags |= TTM_PAGE_FLAG_SG;
643*4882a593Smuzhiyun ttm_tt_set_populated(ttm);
644*4882a593Smuzhiyun return 0;
645*4882a593Smuzhiyun }
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun if (slave && ttm->sg) {
648*4882a593Smuzhiyun drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
649*4882a593Smuzhiyun gtt->ttm.dma_address, ttm->num_pages);
650*4882a593Smuzhiyun ttm_tt_set_populated(ttm);
651*4882a593Smuzhiyun return 0;
652*4882a593Smuzhiyun }
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_AGP)
655*4882a593Smuzhiyun if (rdev->flags & RADEON_IS_AGP) {
656*4882a593Smuzhiyun return ttm_pool_populate(ttm, ctx);
657*4882a593Smuzhiyun }
658*4882a593Smuzhiyun #endif
659*4882a593Smuzhiyun
660*4882a593Smuzhiyun #ifdef CONFIG_SWIOTLB
661*4882a593Smuzhiyun if (rdev->need_swiotlb && swiotlb_nr_tbl()) {
662*4882a593Smuzhiyun return ttm_dma_populate(>t->ttm, rdev->dev, ctx);
663*4882a593Smuzhiyun }
664*4882a593Smuzhiyun #endif
665*4882a593Smuzhiyun
666*4882a593Smuzhiyun return ttm_populate_and_map_pages(rdev->dev, >t->ttm, ctx);
667*4882a593Smuzhiyun }
668*4882a593Smuzhiyun
radeon_ttm_tt_unpopulate(struct ttm_bo_device * bdev,struct ttm_tt * ttm)669*4882a593Smuzhiyun static void radeon_ttm_tt_unpopulate(struct ttm_bo_device *bdev, struct ttm_tt *ttm)
670*4882a593Smuzhiyun {
671*4882a593Smuzhiyun struct radeon_device *rdev = radeon_get_rdev(bdev);
672*4882a593Smuzhiyun struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm);
673*4882a593Smuzhiyun bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun if (gtt && gtt->userptr) {
676*4882a593Smuzhiyun kfree(ttm->sg);
677*4882a593Smuzhiyun ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
678*4882a593Smuzhiyun return;
679*4882a593Smuzhiyun }
680*4882a593Smuzhiyun
681*4882a593Smuzhiyun if (slave)
682*4882a593Smuzhiyun return;
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_AGP)
685*4882a593Smuzhiyun if (rdev->flags & RADEON_IS_AGP) {
686*4882a593Smuzhiyun ttm_pool_unpopulate(ttm);
687*4882a593Smuzhiyun return;
688*4882a593Smuzhiyun }
689*4882a593Smuzhiyun #endif
690*4882a593Smuzhiyun
691*4882a593Smuzhiyun #ifdef CONFIG_SWIOTLB
692*4882a593Smuzhiyun if (rdev->need_swiotlb && swiotlb_nr_tbl()) {
693*4882a593Smuzhiyun ttm_dma_unpopulate(>t->ttm, rdev->dev);
694*4882a593Smuzhiyun return;
695*4882a593Smuzhiyun }
696*4882a593Smuzhiyun #endif
697*4882a593Smuzhiyun
698*4882a593Smuzhiyun ttm_unmap_and_unpopulate_pages(rdev->dev, >t->ttm);
699*4882a593Smuzhiyun }
700*4882a593Smuzhiyun
radeon_ttm_tt_set_userptr(struct radeon_device * rdev,struct ttm_tt * ttm,uint64_t addr,uint32_t flags)701*4882a593Smuzhiyun int radeon_ttm_tt_set_userptr(struct radeon_device *rdev,
702*4882a593Smuzhiyun struct ttm_tt *ttm, uint64_t addr,
703*4882a593Smuzhiyun uint32_t flags)
704*4882a593Smuzhiyun {
705*4882a593Smuzhiyun struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm);
706*4882a593Smuzhiyun
707*4882a593Smuzhiyun if (gtt == NULL)
708*4882a593Smuzhiyun return -EINVAL;
709*4882a593Smuzhiyun
710*4882a593Smuzhiyun gtt->userptr = addr;
711*4882a593Smuzhiyun gtt->usermm = current->mm;
712*4882a593Smuzhiyun gtt->userflags = flags;
713*4882a593Smuzhiyun return 0;
714*4882a593Smuzhiyun }
715*4882a593Smuzhiyun
radeon_ttm_tt_is_bound(struct ttm_bo_device * bdev,struct ttm_tt * ttm)716*4882a593Smuzhiyun bool radeon_ttm_tt_is_bound(struct ttm_bo_device *bdev,
717*4882a593Smuzhiyun struct ttm_tt *ttm)
718*4882a593Smuzhiyun {
719*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_AGP)
720*4882a593Smuzhiyun struct radeon_device *rdev = radeon_get_rdev(bdev);
721*4882a593Smuzhiyun if (rdev->flags & RADEON_IS_AGP)
722*4882a593Smuzhiyun return ttm_agp_is_bound(ttm);
723*4882a593Smuzhiyun #endif
724*4882a593Smuzhiyun return radeon_ttm_backend_is_bound(ttm);
725*4882a593Smuzhiyun }
726*4882a593Smuzhiyun
radeon_ttm_tt_bind(struct ttm_bo_device * bdev,struct ttm_tt * ttm,struct ttm_resource * bo_mem)727*4882a593Smuzhiyun static int radeon_ttm_tt_bind(struct ttm_bo_device *bdev,
728*4882a593Smuzhiyun struct ttm_tt *ttm,
729*4882a593Smuzhiyun struct ttm_resource *bo_mem)
730*4882a593Smuzhiyun {
731*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_AGP)
732*4882a593Smuzhiyun struct radeon_device *rdev = radeon_get_rdev(bdev);
733*4882a593Smuzhiyun #endif
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun if (!bo_mem)
736*4882a593Smuzhiyun return -EINVAL;
737*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_AGP)
738*4882a593Smuzhiyun if (rdev->flags & RADEON_IS_AGP)
739*4882a593Smuzhiyun return ttm_agp_bind(ttm, bo_mem);
740*4882a593Smuzhiyun #endif
741*4882a593Smuzhiyun
742*4882a593Smuzhiyun return radeon_ttm_backend_bind(bdev, ttm, bo_mem);
743*4882a593Smuzhiyun }
744*4882a593Smuzhiyun
radeon_ttm_tt_unbind(struct ttm_bo_device * bdev,struct ttm_tt * ttm)745*4882a593Smuzhiyun static void radeon_ttm_tt_unbind(struct ttm_bo_device *bdev,
746*4882a593Smuzhiyun struct ttm_tt *ttm)
747*4882a593Smuzhiyun {
748*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_AGP)
749*4882a593Smuzhiyun struct radeon_device *rdev = radeon_get_rdev(bdev);
750*4882a593Smuzhiyun
751*4882a593Smuzhiyun if (rdev->flags & RADEON_IS_AGP) {
752*4882a593Smuzhiyun ttm_agp_unbind(ttm);
753*4882a593Smuzhiyun return;
754*4882a593Smuzhiyun }
755*4882a593Smuzhiyun #endif
756*4882a593Smuzhiyun radeon_ttm_backend_unbind(bdev, ttm);
757*4882a593Smuzhiyun }
758*4882a593Smuzhiyun
radeon_ttm_tt_destroy(struct ttm_bo_device * bdev,struct ttm_tt * ttm)759*4882a593Smuzhiyun static void radeon_ttm_tt_destroy(struct ttm_bo_device *bdev,
760*4882a593Smuzhiyun struct ttm_tt *ttm)
761*4882a593Smuzhiyun {
762*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_AGP)
763*4882a593Smuzhiyun struct radeon_device *rdev = radeon_get_rdev(bdev);
764*4882a593Smuzhiyun
765*4882a593Smuzhiyun if (rdev->flags & RADEON_IS_AGP) {
766*4882a593Smuzhiyun ttm_agp_unbind(ttm);
767*4882a593Smuzhiyun ttm_tt_destroy_common(bdev, ttm);
768*4882a593Smuzhiyun ttm_agp_destroy(ttm);
769*4882a593Smuzhiyun return;
770*4882a593Smuzhiyun }
771*4882a593Smuzhiyun #endif
772*4882a593Smuzhiyun radeon_ttm_backend_destroy(bdev, ttm);
773*4882a593Smuzhiyun }
774*4882a593Smuzhiyun
radeon_ttm_tt_has_userptr(struct radeon_device * rdev,struct ttm_tt * ttm)775*4882a593Smuzhiyun bool radeon_ttm_tt_has_userptr(struct radeon_device *rdev,
776*4882a593Smuzhiyun struct ttm_tt *ttm)
777*4882a593Smuzhiyun {
778*4882a593Smuzhiyun struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm);
779*4882a593Smuzhiyun
780*4882a593Smuzhiyun if (gtt == NULL)
781*4882a593Smuzhiyun return false;
782*4882a593Smuzhiyun
783*4882a593Smuzhiyun return !!gtt->userptr;
784*4882a593Smuzhiyun }
785*4882a593Smuzhiyun
radeon_ttm_tt_is_readonly(struct radeon_device * rdev,struct ttm_tt * ttm)786*4882a593Smuzhiyun bool radeon_ttm_tt_is_readonly(struct radeon_device *rdev,
787*4882a593Smuzhiyun struct ttm_tt *ttm)
788*4882a593Smuzhiyun {
789*4882a593Smuzhiyun struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm);
790*4882a593Smuzhiyun
791*4882a593Smuzhiyun if (gtt == NULL)
792*4882a593Smuzhiyun return false;
793*4882a593Smuzhiyun
794*4882a593Smuzhiyun return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
795*4882a593Smuzhiyun }
796*4882a593Smuzhiyun
797*4882a593Smuzhiyun static struct ttm_bo_driver radeon_bo_driver = {
798*4882a593Smuzhiyun .ttm_tt_create = &radeon_ttm_tt_create,
799*4882a593Smuzhiyun .ttm_tt_populate = &radeon_ttm_tt_populate,
800*4882a593Smuzhiyun .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate,
801*4882a593Smuzhiyun .ttm_tt_bind = &radeon_ttm_tt_bind,
802*4882a593Smuzhiyun .ttm_tt_unbind = &radeon_ttm_tt_unbind,
803*4882a593Smuzhiyun .ttm_tt_destroy = &radeon_ttm_tt_destroy,
804*4882a593Smuzhiyun .eviction_valuable = ttm_bo_eviction_valuable,
805*4882a593Smuzhiyun .evict_flags = &radeon_evict_flags,
806*4882a593Smuzhiyun .move = &radeon_bo_move,
807*4882a593Smuzhiyun .verify_access = &radeon_verify_access,
808*4882a593Smuzhiyun .move_notify = &radeon_bo_move_notify,
809*4882a593Smuzhiyun .fault_reserve_notify = &radeon_bo_fault_reserve_notify,
810*4882a593Smuzhiyun .io_mem_reserve = &radeon_ttm_io_mem_reserve,
811*4882a593Smuzhiyun };
812*4882a593Smuzhiyun
radeon_ttm_init(struct radeon_device * rdev)813*4882a593Smuzhiyun int radeon_ttm_init(struct radeon_device *rdev)
814*4882a593Smuzhiyun {
815*4882a593Smuzhiyun int r;
816*4882a593Smuzhiyun
817*4882a593Smuzhiyun /* No others user of address space so set it to 0 */
818*4882a593Smuzhiyun r = ttm_bo_device_init(&rdev->mman.bdev,
819*4882a593Smuzhiyun &radeon_bo_driver,
820*4882a593Smuzhiyun rdev->ddev->anon_inode->i_mapping,
821*4882a593Smuzhiyun rdev->ddev->vma_offset_manager,
822*4882a593Smuzhiyun dma_addressing_limited(&rdev->pdev->dev));
823*4882a593Smuzhiyun if (r) {
824*4882a593Smuzhiyun DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
825*4882a593Smuzhiyun return r;
826*4882a593Smuzhiyun }
827*4882a593Smuzhiyun rdev->mman.initialized = true;
828*4882a593Smuzhiyun
829*4882a593Smuzhiyun r = radeon_ttm_init_vram(rdev);
830*4882a593Smuzhiyun if (r) {
831*4882a593Smuzhiyun DRM_ERROR("Failed initializing VRAM heap.\n");
832*4882a593Smuzhiyun return r;
833*4882a593Smuzhiyun }
834*4882a593Smuzhiyun /* Change the size here instead of the init above so only lpfn is affected */
835*4882a593Smuzhiyun radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
836*4882a593Smuzhiyun
837*4882a593Smuzhiyun r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
838*4882a593Smuzhiyun RADEON_GEM_DOMAIN_VRAM, 0, NULL,
839*4882a593Smuzhiyun NULL, &rdev->stolen_vga_memory);
840*4882a593Smuzhiyun if (r) {
841*4882a593Smuzhiyun return r;
842*4882a593Smuzhiyun }
843*4882a593Smuzhiyun r = radeon_bo_reserve(rdev->stolen_vga_memory, false);
844*4882a593Smuzhiyun if (r)
845*4882a593Smuzhiyun return r;
846*4882a593Smuzhiyun r = radeon_bo_pin(rdev->stolen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
847*4882a593Smuzhiyun radeon_bo_unreserve(rdev->stolen_vga_memory);
848*4882a593Smuzhiyun if (r) {
849*4882a593Smuzhiyun radeon_bo_unref(&rdev->stolen_vga_memory);
850*4882a593Smuzhiyun return r;
851*4882a593Smuzhiyun }
852*4882a593Smuzhiyun DRM_INFO("radeon: %uM of VRAM memory ready\n",
853*4882a593Smuzhiyun (unsigned) (rdev->mc.real_vram_size / (1024 * 1024)));
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun r = radeon_ttm_init_gtt(rdev);
856*4882a593Smuzhiyun if (r) {
857*4882a593Smuzhiyun DRM_ERROR("Failed initializing GTT heap.\n");
858*4882a593Smuzhiyun return r;
859*4882a593Smuzhiyun }
860*4882a593Smuzhiyun DRM_INFO("radeon: %uM of GTT memory ready.\n",
861*4882a593Smuzhiyun (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
862*4882a593Smuzhiyun
863*4882a593Smuzhiyun r = radeon_ttm_debugfs_init(rdev);
864*4882a593Smuzhiyun if (r) {
865*4882a593Smuzhiyun DRM_ERROR("Failed to init debugfs\n");
866*4882a593Smuzhiyun return r;
867*4882a593Smuzhiyun }
868*4882a593Smuzhiyun return 0;
869*4882a593Smuzhiyun }
870*4882a593Smuzhiyun
radeon_ttm_fini(struct radeon_device * rdev)871*4882a593Smuzhiyun void radeon_ttm_fini(struct radeon_device *rdev)
872*4882a593Smuzhiyun {
873*4882a593Smuzhiyun int r;
874*4882a593Smuzhiyun
875*4882a593Smuzhiyun if (!rdev->mman.initialized)
876*4882a593Smuzhiyun return;
877*4882a593Smuzhiyun radeon_ttm_debugfs_fini(rdev);
878*4882a593Smuzhiyun if (rdev->stolen_vga_memory) {
879*4882a593Smuzhiyun r = radeon_bo_reserve(rdev->stolen_vga_memory, false);
880*4882a593Smuzhiyun if (r == 0) {
881*4882a593Smuzhiyun radeon_bo_unpin(rdev->stolen_vga_memory);
882*4882a593Smuzhiyun radeon_bo_unreserve(rdev->stolen_vga_memory);
883*4882a593Smuzhiyun }
884*4882a593Smuzhiyun radeon_bo_unref(&rdev->stolen_vga_memory);
885*4882a593Smuzhiyun }
886*4882a593Smuzhiyun ttm_range_man_fini(&rdev->mman.bdev, TTM_PL_VRAM);
887*4882a593Smuzhiyun ttm_range_man_fini(&rdev->mman.bdev, TTM_PL_TT);
888*4882a593Smuzhiyun ttm_bo_device_release(&rdev->mman.bdev);
889*4882a593Smuzhiyun radeon_gart_fini(rdev);
890*4882a593Smuzhiyun rdev->mman.initialized = false;
891*4882a593Smuzhiyun DRM_INFO("radeon: ttm finalized\n");
892*4882a593Smuzhiyun }
893*4882a593Smuzhiyun
894*4882a593Smuzhiyun /* this should only be called at bootup or when userspace
895*4882a593Smuzhiyun * isn't running */
radeon_ttm_set_active_vram_size(struct radeon_device * rdev,u64 size)896*4882a593Smuzhiyun void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
897*4882a593Smuzhiyun {
898*4882a593Smuzhiyun struct ttm_resource_manager *man;
899*4882a593Smuzhiyun
900*4882a593Smuzhiyun if (!rdev->mman.initialized)
901*4882a593Smuzhiyun return;
902*4882a593Smuzhiyun
903*4882a593Smuzhiyun man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_VRAM);
904*4882a593Smuzhiyun /* this just adjusts TTM size idea, which sets lpfn to the correct value */
905*4882a593Smuzhiyun man->size = size >> PAGE_SHIFT;
906*4882a593Smuzhiyun }
907*4882a593Smuzhiyun
radeon_ttm_fault(struct vm_fault * vmf)908*4882a593Smuzhiyun static vm_fault_t radeon_ttm_fault(struct vm_fault *vmf)
909*4882a593Smuzhiyun {
910*4882a593Smuzhiyun struct ttm_buffer_object *bo;
911*4882a593Smuzhiyun struct radeon_device *rdev;
912*4882a593Smuzhiyun vm_fault_t ret;
913*4882a593Smuzhiyun
914*4882a593Smuzhiyun bo = (struct ttm_buffer_object *)vmf->vma->vm_private_data;
915*4882a593Smuzhiyun if (bo == NULL)
916*4882a593Smuzhiyun return VM_FAULT_NOPAGE;
917*4882a593Smuzhiyun
918*4882a593Smuzhiyun rdev = radeon_get_rdev(bo->bdev);
919*4882a593Smuzhiyun down_read(&rdev->pm.mclk_lock);
920*4882a593Smuzhiyun ret = ttm_bo_vm_fault(vmf);
921*4882a593Smuzhiyun up_read(&rdev->pm.mclk_lock);
922*4882a593Smuzhiyun return ret;
923*4882a593Smuzhiyun }
924*4882a593Smuzhiyun
925*4882a593Smuzhiyun static struct vm_operations_struct radeon_ttm_vm_ops = {
926*4882a593Smuzhiyun .fault = radeon_ttm_fault,
927*4882a593Smuzhiyun .open = ttm_bo_vm_open,
928*4882a593Smuzhiyun .close = ttm_bo_vm_close,
929*4882a593Smuzhiyun .access = ttm_bo_vm_access
930*4882a593Smuzhiyun };
931*4882a593Smuzhiyun
radeon_mmap(struct file * filp,struct vm_area_struct * vma)932*4882a593Smuzhiyun int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
933*4882a593Smuzhiyun {
934*4882a593Smuzhiyun int r;
935*4882a593Smuzhiyun struct drm_file *file_priv = filp->private_data;
936*4882a593Smuzhiyun struct radeon_device *rdev = file_priv->minor->dev->dev_private;
937*4882a593Smuzhiyun
938*4882a593Smuzhiyun if (rdev == NULL)
939*4882a593Smuzhiyun return -EINVAL;
940*4882a593Smuzhiyun
941*4882a593Smuzhiyun r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
942*4882a593Smuzhiyun if (unlikely(r != 0))
943*4882a593Smuzhiyun return r;
944*4882a593Smuzhiyun
945*4882a593Smuzhiyun vma->vm_ops = &radeon_ttm_vm_ops;
946*4882a593Smuzhiyun return 0;
947*4882a593Smuzhiyun }
948*4882a593Smuzhiyun
949*4882a593Smuzhiyun #if defined(CONFIG_DEBUG_FS)
950*4882a593Smuzhiyun
radeon_mm_dump_table(struct seq_file * m,void * data)951*4882a593Smuzhiyun static int radeon_mm_dump_table(struct seq_file *m, void *data)
952*4882a593Smuzhiyun {
953*4882a593Smuzhiyun struct drm_info_node *node = (struct drm_info_node *)m->private;
954*4882a593Smuzhiyun unsigned ttm_pl = *(int*)node->info_ent->data;
955*4882a593Smuzhiyun struct drm_device *dev = node->minor->dev;
956*4882a593Smuzhiyun struct radeon_device *rdev = dev->dev_private;
957*4882a593Smuzhiyun struct ttm_resource_manager *man = ttm_manager_type(&rdev->mman.bdev, ttm_pl);
958*4882a593Smuzhiyun struct drm_printer p = drm_seq_file_printer(m);
959*4882a593Smuzhiyun
960*4882a593Smuzhiyun man->func->debug(man, &p);
961*4882a593Smuzhiyun return 0;
962*4882a593Smuzhiyun }
963*4882a593Smuzhiyun
964*4882a593Smuzhiyun
965*4882a593Smuzhiyun static int ttm_pl_vram = TTM_PL_VRAM;
966*4882a593Smuzhiyun static int ttm_pl_tt = TTM_PL_TT;
967*4882a593Smuzhiyun
968*4882a593Smuzhiyun static struct drm_info_list radeon_ttm_debugfs_list[] = {
969*4882a593Smuzhiyun {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram},
970*4882a593Smuzhiyun {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt},
971*4882a593Smuzhiyun {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
972*4882a593Smuzhiyun #ifdef CONFIG_SWIOTLB
973*4882a593Smuzhiyun {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
974*4882a593Smuzhiyun #endif
975*4882a593Smuzhiyun };
976*4882a593Smuzhiyun
radeon_ttm_vram_open(struct inode * inode,struct file * filep)977*4882a593Smuzhiyun static int radeon_ttm_vram_open(struct inode *inode, struct file *filep)
978*4882a593Smuzhiyun {
979*4882a593Smuzhiyun struct radeon_device *rdev = inode->i_private;
980*4882a593Smuzhiyun i_size_write(inode, rdev->mc.mc_vram_size);
981*4882a593Smuzhiyun filep->private_data = inode->i_private;
982*4882a593Smuzhiyun return 0;
983*4882a593Smuzhiyun }
984*4882a593Smuzhiyun
radeon_ttm_vram_read(struct file * f,char __user * buf,size_t size,loff_t * pos)985*4882a593Smuzhiyun static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf,
986*4882a593Smuzhiyun size_t size, loff_t *pos)
987*4882a593Smuzhiyun {
988*4882a593Smuzhiyun struct radeon_device *rdev = f->private_data;
989*4882a593Smuzhiyun ssize_t result = 0;
990*4882a593Smuzhiyun int r;
991*4882a593Smuzhiyun
992*4882a593Smuzhiyun if (size & 0x3 || *pos & 0x3)
993*4882a593Smuzhiyun return -EINVAL;
994*4882a593Smuzhiyun
995*4882a593Smuzhiyun while (size) {
996*4882a593Smuzhiyun unsigned long flags;
997*4882a593Smuzhiyun uint32_t value;
998*4882a593Smuzhiyun
999*4882a593Smuzhiyun if (*pos >= rdev->mc.mc_vram_size)
1000*4882a593Smuzhiyun return result;
1001*4882a593Smuzhiyun
1002*4882a593Smuzhiyun spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
1003*4882a593Smuzhiyun WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000);
1004*4882a593Smuzhiyun if (rdev->family >= CHIP_CEDAR)
1005*4882a593Smuzhiyun WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31);
1006*4882a593Smuzhiyun value = RREG32(RADEON_MM_DATA);
1007*4882a593Smuzhiyun spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
1008*4882a593Smuzhiyun
1009*4882a593Smuzhiyun r = put_user(value, (uint32_t *)buf);
1010*4882a593Smuzhiyun if (r)
1011*4882a593Smuzhiyun return r;
1012*4882a593Smuzhiyun
1013*4882a593Smuzhiyun result += 4;
1014*4882a593Smuzhiyun buf += 4;
1015*4882a593Smuzhiyun *pos += 4;
1016*4882a593Smuzhiyun size -= 4;
1017*4882a593Smuzhiyun }
1018*4882a593Smuzhiyun
1019*4882a593Smuzhiyun return result;
1020*4882a593Smuzhiyun }
1021*4882a593Smuzhiyun
1022*4882a593Smuzhiyun static const struct file_operations radeon_ttm_vram_fops = {
1023*4882a593Smuzhiyun .owner = THIS_MODULE,
1024*4882a593Smuzhiyun .open = radeon_ttm_vram_open,
1025*4882a593Smuzhiyun .read = radeon_ttm_vram_read,
1026*4882a593Smuzhiyun .llseek = default_llseek
1027*4882a593Smuzhiyun };
1028*4882a593Smuzhiyun
radeon_ttm_gtt_open(struct inode * inode,struct file * filep)1029*4882a593Smuzhiyun static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep)
1030*4882a593Smuzhiyun {
1031*4882a593Smuzhiyun struct radeon_device *rdev = inode->i_private;
1032*4882a593Smuzhiyun i_size_write(inode, rdev->mc.gtt_size);
1033*4882a593Smuzhiyun filep->private_data = inode->i_private;
1034*4882a593Smuzhiyun return 0;
1035*4882a593Smuzhiyun }
1036*4882a593Smuzhiyun
radeon_ttm_gtt_read(struct file * f,char __user * buf,size_t size,loff_t * pos)1037*4882a593Smuzhiyun static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf,
1038*4882a593Smuzhiyun size_t size, loff_t *pos)
1039*4882a593Smuzhiyun {
1040*4882a593Smuzhiyun struct radeon_device *rdev = f->private_data;
1041*4882a593Smuzhiyun ssize_t result = 0;
1042*4882a593Smuzhiyun int r;
1043*4882a593Smuzhiyun
1044*4882a593Smuzhiyun while (size) {
1045*4882a593Smuzhiyun loff_t p = *pos / PAGE_SIZE;
1046*4882a593Smuzhiyun unsigned off = *pos & ~PAGE_MASK;
1047*4882a593Smuzhiyun size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1048*4882a593Smuzhiyun struct page *page;
1049*4882a593Smuzhiyun void *ptr;
1050*4882a593Smuzhiyun
1051*4882a593Smuzhiyun if (p >= rdev->gart.num_cpu_pages)
1052*4882a593Smuzhiyun return result;
1053*4882a593Smuzhiyun
1054*4882a593Smuzhiyun page = rdev->gart.pages[p];
1055*4882a593Smuzhiyun if (page) {
1056*4882a593Smuzhiyun ptr = kmap(page);
1057*4882a593Smuzhiyun ptr += off;
1058*4882a593Smuzhiyun
1059*4882a593Smuzhiyun r = copy_to_user(buf, ptr, cur_size);
1060*4882a593Smuzhiyun kunmap(rdev->gart.pages[p]);
1061*4882a593Smuzhiyun } else
1062*4882a593Smuzhiyun r = clear_user(buf, cur_size);
1063*4882a593Smuzhiyun
1064*4882a593Smuzhiyun if (r)
1065*4882a593Smuzhiyun return -EFAULT;
1066*4882a593Smuzhiyun
1067*4882a593Smuzhiyun result += cur_size;
1068*4882a593Smuzhiyun buf += cur_size;
1069*4882a593Smuzhiyun *pos += cur_size;
1070*4882a593Smuzhiyun size -= cur_size;
1071*4882a593Smuzhiyun }
1072*4882a593Smuzhiyun
1073*4882a593Smuzhiyun return result;
1074*4882a593Smuzhiyun }
1075*4882a593Smuzhiyun
1076*4882a593Smuzhiyun static const struct file_operations radeon_ttm_gtt_fops = {
1077*4882a593Smuzhiyun .owner = THIS_MODULE,
1078*4882a593Smuzhiyun .open = radeon_ttm_gtt_open,
1079*4882a593Smuzhiyun .read = radeon_ttm_gtt_read,
1080*4882a593Smuzhiyun .llseek = default_llseek
1081*4882a593Smuzhiyun };
1082*4882a593Smuzhiyun
1083*4882a593Smuzhiyun #endif
1084*4882a593Smuzhiyun
radeon_ttm_debugfs_init(struct radeon_device * rdev)1085*4882a593Smuzhiyun static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
1086*4882a593Smuzhiyun {
1087*4882a593Smuzhiyun #if defined(CONFIG_DEBUG_FS)
1088*4882a593Smuzhiyun unsigned count;
1089*4882a593Smuzhiyun
1090*4882a593Smuzhiyun struct drm_minor *minor = rdev->ddev->primary;
1091*4882a593Smuzhiyun struct dentry *root = minor->debugfs_root;
1092*4882a593Smuzhiyun
1093*4882a593Smuzhiyun rdev->mman.vram = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO,
1094*4882a593Smuzhiyun root, rdev,
1095*4882a593Smuzhiyun &radeon_ttm_vram_fops);
1096*4882a593Smuzhiyun
1097*4882a593Smuzhiyun rdev->mman.gtt = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO,
1098*4882a593Smuzhiyun root, rdev, &radeon_ttm_gtt_fops);
1099*4882a593Smuzhiyun
1100*4882a593Smuzhiyun count = ARRAY_SIZE(radeon_ttm_debugfs_list);
1101*4882a593Smuzhiyun
1102*4882a593Smuzhiyun #ifdef CONFIG_SWIOTLB
1103*4882a593Smuzhiyun if (!(rdev->need_swiotlb && swiotlb_nr_tbl()))
1104*4882a593Smuzhiyun --count;
1105*4882a593Smuzhiyun #endif
1106*4882a593Smuzhiyun
1107*4882a593Smuzhiyun return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count);
1108*4882a593Smuzhiyun #else
1109*4882a593Smuzhiyun
1110*4882a593Smuzhiyun return 0;
1111*4882a593Smuzhiyun #endif
1112*4882a593Smuzhiyun }
1113*4882a593Smuzhiyun
radeon_ttm_debugfs_fini(struct radeon_device * rdev)1114*4882a593Smuzhiyun static void radeon_ttm_debugfs_fini(struct radeon_device *rdev)
1115*4882a593Smuzhiyun {
1116*4882a593Smuzhiyun #if defined(CONFIG_DEBUG_FS)
1117*4882a593Smuzhiyun
1118*4882a593Smuzhiyun debugfs_remove(rdev->mman.vram);
1119*4882a593Smuzhiyun rdev->mman.vram = NULL;
1120*4882a593Smuzhiyun
1121*4882a593Smuzhiyun debugfs_remove(rdev->mman.gtt);
1122*4882a593Smuzhiyun rdev->mman.gtt = NULL;
1123*4882a593Smuzhiyun #endif
1124*4882a593Smuzhiyun }
1125