xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/radeon_test.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0 OR MIT
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright 2009 VMware, Inc.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Permission is hereby granted, free of charge, to any person obtaining a
6*4882a593Smuzhiyun  * copy of this software and associated documentation files (the "Software"),
7*4882a593Smuzhiyun  * to deal in the Software without restriction, including without limitation
8*4882a593Smuzhiyun  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9*4882a593Smuzhiyun  * and/or sell copies of the Software, and to permit persons to whom the
10*4882a593Smuzhiyun  * Software is furnished to do so, subject to the following conditions:
11*4882a593Smuzhiyun  *
12*4882a593Smuzhiyun  * The above copyright notice and this permission notice shall be included in
13*4882a593Smuzhiyun  * all copies or substantial portions of the Software.
14*4882a593Smuzhiyun  *
15*4882a593Smuzhiyun  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16*4882a593Smuzhiyun  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18*4882a593Smuzhiyun  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19*4882a593Smuzhiyun  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20*4882a593Smuzhiyun  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21*4882a593Smuzhiyun  * OTHER DEALINGS IN THE SOFTWARE.
22*4882a593Smuzhiyun  *
23*4882a593Smuzhiyun  * Authors: Michel Dänzer
24*4882a593Smuzhiyun  */
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #include <drm/radeon_drm.h>
27*4882a593Smuzhiyun #include "radeon_reg.h"
28*4882a593Smuzhiyun #include "radeon.h"
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #define RADEON_TEST_COPY_BLIT 1
31*4882a593Smuzhiyun #define RADEON_TEST_COPY_DMA  0
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun /* Test BO GTT->VRAM and VRAM->GTT GPU copies across the whole GTT aperture */
radeon_do_test_moves(struct radeon_device * rdev,int flag)35*4882a593Smuzhiyun static void radeon_do_test_moves(struct radeon_device *rdev, int flag)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun 	struct radeon_bo *vram_obj = NULL;
38*4882a593Smuzhiyun 	struct radeon_bo **gtt_obj = NULL;
39*4882a593Smuzhiyun 	uint64_t gtt_addr, vram_addr;
40*4882a593Smuzhiyun 	unsigned n, size;
41*4882a593Smuzhiyun 	int i, r, ring;
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun 	switch (flag) {
44*4882a593Smuzhiyun 	case RADEON_TEST_COPY_DMA:
45*4882a593Smuzhiyun 		ring = radeon_copy_dma_ring_index(rdev);
46*4882a593Smuzhiyun 		break;
47*4882a593Smuzhiyun 	case RADEON_TEST_COPY_BLIT:
48*4882a593Smuzhiyun 		ring = radeon_copy_blit_ring_index(rdev);
49*4882a593Smuzhiyun 		break;
50*4882a593Smuzhiyun 	default:
51*4882a593Smuzhiyun 		DRM_ERROR("Unknown copy method\n");
52*4882a593Smuzhiyun 		return;
53*4882a593Smuzhiyun 	}
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	size = 1024 * 1024;
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	/* Number of tests =
58*4882a593Smuzhiyun 	 * (Total GTT - IB pool - writeback page - ring buffers) / test size
59*4882a593Smuzhiyun 	 */
60*4882a593Smuzhiyun 	n = rdev->mc.gtt_size - rdev->gart_pin_size;
61*4882a593Smuzhiyun 	n /= size;
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun 	gtt_obj = kcalloc(n, sizeof(*gtt_obj), GFP_KERNEL);
64*4882a593Smuzhiyun 	if (!gtt_obj) {
65*4882a593Smuzhiyun 		DRM_ERROR("Failed to allocate %d pointers\n", n);
66*4882a593Smuzhiyun 		r = 1;
67*4882a593Smuzhiyun 		goto out_cleanup;
68*4882a593Smuzhiyun 	}
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun 	r = radeon_bo_create(rdev, size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
71*4882a593Smuzhiyun 			     0, NULL, NULL, &vram_obj);
72*4882a593Smuzhiyun 	if (r) {
73*4882a593Smuzhiyun 		DRM_ERROR("Failed to create VRAM object\n");
74*4882a593Smuzhiyun 		goto out_cleanup;
75*4882a593Smuzhiyun 	}
76*4882a593Smuzhiyun 	r = radeon_bo_reserve(vram_obj, false);
77*4882a593Smuzhiyun 	if (unlikely(r != 0))
78*4882a593Smuzhiyun 		goto out_unref;
79*4882a593Smuzhiyun 	r = radeon_bo_pin(vram_obj, RADEON_GEM_DOMAIN_VRAM, &vram_addr);
80*4882a593Smuzhiyun 	if (r) {
81*4882a593Smuzhiyun 		DRM_ERROR("Failed to pin VRAM object\n");
82*4882a593Smuzhiyun 		goto out_unres;
83*4882a593Smuzhiyun 	}
84*4882a593Smuzhiyun 	for (i = 0; i < n; i++) {
85*4882a593Smuzhiyun 		void *gtt_map, *vram_map;
86*4882a593Smuzhiyun 		void **gtt_start, **gtt_end;
87*4882a593Smuzhiyun 		void **vram_start, **vram_end;
88*4882a593Smuzhiyun 		struct radeon_fence *fence = NULL;
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 		r = radeon_bo_create(rdev, size, PAGE_SIZE, true,
91*4882a593Smuzhiyun 				     RADEON_GEM_DOMAIN_GTT, 0, NULL, NULL,
92*4882a593Smuzhiyun 				     gtt_obj + i);
93*4882a593Smuzhiyun 		if (r) {
94*4882a593Smuzhiyun 			DRM_ERROR("Failed to create GTT object %d\n", i);
95*4882a593Smuzhiyun 			goto out_lclean;
96*4882a593Smuzhiyun 		}
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 		r = radeon_bo_reserve(gtt_obj[i], false);
99*4882a593Smuzhiyun 		if (unlikely(r != 0))
100*4882a593Smuzhiyun 			goto out_lclean_unref;
101*4882a593Smuzhiyun 		r = radeon_bo_pin(gtt_obj[i], RADEON_GEM_DOMAIN_GTT, &gtt_addr);
102*4882a593Smuzhiyun 		if (r) {
103*4882a593Smuzhiyun 			DRM_ERROR("Failed to pin GTT object %d\n", i);
104*4882a593Smuzhiyun 			goto out_lclean_unres;
105*4882a593Smuzhiyun 		}
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 		r = radeon_bo_kmap(gtt_obj[i], &gtt_map);
108*4882a593Smuzhiyun 		if (r) {
109*4882a593Smuzhiyun 			DRM_ERROR("Failed to map GTT object %d\n", i);
110*4882a593Smuzhiyun 			goto out_lclean_unpin;
111*4882a593Smuzhiyun 		}
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 		for (gtt_start = gtt_map, gtt_end = gtt_map + size;
114*4882a593Smuzhiyun 		     gtt_start < gtt_end;
115*4882a593Smuzhiyun 		     gtt_start++)
116*4882a593Smuzhiyun 			*gtt_start = gtt_start;
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 		radeon_bo_kunmap(gtt_obj[i]);
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 		if (ring == R600_RING_TYPE_DMA_INDEX)
121*4882a593Smuzhiyun 			fence = radeon_copy_dma(rdev, gtt_addr, vram_addr,
122*4882a593Smuzhiyun 						size / RADEON_GPU_PAGE_SIZE,
123*4882a593Smuzhiyun 						vram_obj->tbo.base.resv);
124*4882a593Smuzhiyun 		else
125*4882a593Smuzhiyun 			fence = radeon_copy_blit(rdev, gtt_addr, vram_addr,
126*4882a593Smuzhiyun 						 size / RADEON_GPU_PAGE_SIZE,
127*4882a593Smuzhiyun 						 vram_obj->tbo.base.resv);
128*4882a593Smuzhiyun 		if (IS_ERR(fence)) {
129*4882a593Smuzhiyun 			DRM_ERROR("Failed GTT->VRAM copy %d\n", i);
130*4882a593Smuzhiyun 			r = PTR_ERR(fence);
131*4882a593Smuzhiyun 			goto out_lclean_unpin;
132*4882a593Smuzhiyun 		}
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 		r = radeon_fence_wait(fence, false);
135*4882a593Smuzhiyun 		if (r) {
136*4882a593Smuzhiyun 			DRM_ERROR("Failed to wait for GTT->VRAM fence %d\n", i);
137*4882a593Smuzhiyun 			goto out_lclean_unpin;
138*4882a593Smuzhiyun 		}
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 		radeon_fence_unref(&fence);
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 		r = radeon_bo_kmap(vram_obj, &vram_map);
143*4882a593Smuzhiyun 		if (r) {
144*4882a593Smuzhiyun 			DRM_ERROR("Failed to map VRAM object after copy %d\n", i);
145*4882a593Smuzhiyun 			goto out_lclean_unpin;
146*4882a593Smuzhiyun 		}
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 		for (gtt_start = gtt_map, gtt_end = gtt_map + size,
149*4882a593Smuzhiyun 		     vram_start = vram_map, vram_end = vram_map + size;
150*4882a593Smuzhiyun 		     vram_start < vram_end;
151*4882a593Smuzhiyun 		     gtt_start++, vram_start++) {
152*4882a593Smuzhiyun 			if (*vram_start != gtt_start) {
153*4882a593Smuzhiyun 				DRM_ERROR("Incorrect GTT->VRAM copy %d: Got 0x%p, "
154*4882a593Smuzhiyun 					  "expected 0x%p (GTT/VRAM offset "
155*4882a593Smuzhiyun 					  "0x%16llx/0x%16llx)\n",
156*4882a593Smuzhiyun 					  i, *vram_start, gtt_start,
157*4882a593Smuzhiyun 					  (unsigned long long)
158*4882a593Smuzhiyun 					  (gtt_addr - rdev->mc.gtt_start +
159*4882a593Smuzhiyun 					   (void*)gtt_start - gtt_map),
160*4882a593Smuzhiyun 					  (unsigned long long)
161*4882a593Smuzhiyun 					  (vram_addr - rdev->mc.vram_start +
162*4882a593Smuzhiyun 					   (void*)gtt_start - gtt_map));
163*4882a593Smuzhiyun 				radeon_bo_kunmap(vram_obj);
164*4882a593Smuzhiyun 				goto out_lclean_unpin;
165*4882a593Smuzhiyun 			}
166*4882a593Smuzhiyun 			*vram_start = vram_start;
167*4882a593Smuzhiyun 		}
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 		radeon_bo_kunmap(vram_obj);
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 		if (ring == R600_RING_TYPE_DMA_INDEX)
172*4882a593Smuzhiyun 			fence = radeon_copy_dma(rdev, vram_addr, gtt_addr,
173*4882a593Smuzhiyun 						size / RADEON_GPU_PAGE_SIZE,
174*4882a593Smuzhiyun 						vram_obj->tbo.base.resv);
175*4882a593Smuzhiyun 		else
176*4882a593Smuzhiyun 			fence = radeon_copy_blit(rdev, vram_addr, gtt_addr,
177*4882a593Smuzhiyun 						 size / RADEON_GPU_PAGE_SIZE,
178*4882a593Smuzhiyun 						 vram_obj->tbo.base.resv);
179*4882a593Smuzhiyun 		if (IS_ERR(fence)) {
180*4882a593Smuzhiyun 			DRM_ERROR("Failed VRAM->GTT copy %d\n", i);
181*4882a593Smuzhiyun 			r = PTR_ERR(fence);
182*4882a593Smuzhiyun 			goto out_lclean_unpin;
183*4882a593Smuzhiyun 		}
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 		r = radeon_fence_wait(fence, false);
186*4882a593Smuzhiyun 		if (r) {
187*4882a593Smuzhiyun 			DRM_ERROR("Failed to wait for VRAM->GTT fence %d\n", i);
188*4882a593Smuzhiyun 			goto out_lclean_unpin;
189*4882a593Smuzhiyun 		}
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 		radeon_fence_unref(&fence);
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 		r = radeon_bo_kmap(gtt_obj[i], &gtt_map);
194*4882a593Smuzhiyun 		if (r) {
195*4882a593Smuzhiyun 			DRM_ERROR("Failed to map GTT object after copy %d\n", i);
196*4882a593Smuzhiyun 			goto out_lclean_unpin;
197*4882a593Smuzhiyun 		}
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 		for (gtt_start = gtt_map, gtt_end = gtt_map + size,
200*4882a593Smuzhiyun 		     vram_start = vram_map, vram_end = vram_map + size;
201*4882a593Smuzhiyun 		     gtt_start < gtt_end;
202*4882a593Smuzhiyun 		     gtt_start++, vram_start++) {
203*4882a593Smuzhiyun 			if (*gtt_start != vram_start) {
204*4882a593Smuzhiyun 				DRM_ERROR("Incorrect VRAM->GTT copy %d: Got 0x%p, "
205*4882a593Smuzhiyun 					  "expected 0x%p (VRAM/GTT offset "
206*4882a593Smuzhiyun 					  "0x%16llx/0x%16llx)\n",
207*4882a593Smuzhiyun 					  i, *gtt_start, vram_start,
208*4882a593Smuzhiyun 					  (unsigned long long)
209*4882a593Smuzhiyun 					  (vram_addr - rdev->mc.vram_start +
210*4882a593Smuzhiyun 					   (void*)vram_start - vram_map),
211*4882a593Smuzhiyun 					  (unsigned long long)
212*4882a593Smuzhiyun 					  (gtt_addr - rdev->mc.gtt_start +
213*4882a593Smuzhiyun 					   (void*)vram_start - vram_map));
214*4882a593Smuzhiyun 				radeon_bo_kunmap(gtt_obj[i]);
215*4882a593Smuzhiyun 				goto out_lclean_unpin;
216*4882a593Smuzhiyun 			}
217*4882a593Smuzhiyun 		}
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun 		radeon_bo_kunmap(gtt_obj[i]);
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 		DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n",
222*4882a593Smuzhiyun 			 gtt_addr - rdev->mc.gtt_start);
223*4882a593Smuzhiyun 		continue;
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun out_lclean_unpin:
226*4882a593Smuzhiyun 		radeon_bo_unpin(gtt_obj[i]);
227*4882a593Smuzhiyun out_lclean_unres:
228*4882a593Smuzhiyun 		radeon_bo_unreserve(gtt_obj[i]);
229*4882a593Smuzhiyun out_lclean_unref:
230*4882a593Smuzhiyun 		radeon_bo_unref(&gtt_obj[i]);
231*4882a593Smuzhiyun out_lclean:
232*4882a593Smuzhiyun 		for (--i; i >= 0; --i) {
233*4882a593Smuzhiyun 			radeon_bo_unpin(gtt_obj[i]);
234*4882a593Smuzhiyun 			radeon_bo_unreserve(gtt_obj[i]);
235*4882a593Smuzhiyun 			radeon_bo_unref(&gtt_obj[i]);
236*4882a593Smuzhiyun 		}
237*4882a593Smuzhiyun 		if (fence && !IS_ERR(fence))
238*4882a593Smuzhiyun 			radeon_fence_unref(&fence);
239*4882a593Smuzhiyun 		break;
240*4882a593Smuzhiyun 	}
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 	radeon_bo_unpin(vram_obj);
243*4882a593Smuzhiyun out_unres:
244*4882a593Smuzhiyun 	radeon_bo_unreserve(vram_obj);
245*4882a593Smuzhiyun out_unref:
246*4882a593Smuzhiyun 	radeon_bo_unref(&vram_obj);
247*4882a593Smuzhiyun out_cleanup:
248*4882a593Smuzhiyun 	kfree(gtt_obj);
249*4882a593Smuzhiyun 	if (r) {
250*4882a593Smuzhiyun 		pr_warn("Error while testing BO move\n");
251*4882a593Smuzhiyun 	}
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun 
radeon_test_moves(struct radeon_device * rdev)254*4882a593Smuzhiyun void radeon_test_moves(struct radeon_device *rdev)
255*4882a593Smuzhiyun {
256*4882a593Smuzhiyun 	if (rdev->asic->copy.dma)
257*4882a593Smuzhiyun 		radeon_do_test_moves(rdev, RADEON_TEST_COPY_DMA);
258*4882a593Smuzhiyun 	if (rdev->asic->copy.blit)
259*4882a593Smuzhiyun 		radeon_do_test_moves(rdev, RADEON_TEST_COPY_BLIT);
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun 
radeon_test_create_and_emit_fence(struct radeon_device * rdev,struct radeon_ring * ring,struct radeon_fence ** fence)262*4882a593Smuzhiyun static int radeon_test_create_and_emit_fence(struct radeon_device *rdev,
263*4882a593Smuzhiyun 					     struct radeon_ring *ring,
264*4882a593Smuzhiyun 					     struct radeon_fence **fence)
265*4882a593Smuzhiyun {
266*4882a593Smuzhiyun 	uint32_t handle = ring->idx ^ 0xdeafbeef;
267*4882a593Smuzhiyun 	int r;
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 	if (ring->idx == R600_RING_TYPE_UVD_INDEX) {
270*4882a593Smuzhiyun 		r = radeon_uvd_get_create_msg(rdev, ring->idx, handle, NULL);
271*4882a593Smuzhiyun 		if (r) {
272*4882a593Smuzhiyun 			DRM_ERROR("Failed to get dummy create msg\n");
273*4882a593Smuzhiyun 			return r;
274*4882a593Smuzhiyun 		}
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun 		r = radeon_uvd_get_destroy_msg(rdev, ring->idx, handle, fence);
277*4882a593Smuzhiyun 		if (r) {
278*4882a593Smuzhiyun 			DRM_ERROR("Failed to get dummy destroy msg\n");
279*4882a593Smuzhiyun 			return r;
280*4882a593Smuzhiyun 		}
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun 	} else if (ring->idx == TN_RING_TYPE_VCE1_INDEX ||
283*4882a593Smuzhiyun 		   ring->idx == TN_RING_TYPE_VCE2_INDEX) {
284*4882a593Smuzhiyun 		r = radeon_vce_get_create_msg(rdev, ring->idx, handle, NULL);
285*4882a593Smuzhiyun 		if (r) {
286*4882a593Smuzhiyun 			DRM_ERROR("Failed to get dummy create msg\n");
287*4882a593Smuzhiyun 			return r;
288*4882a593Smuzhiyun 		}
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun 		r = radeon_vce_get_destroy_msg(rdev, ring->idx, handle, fence);
291*4882a593Smuzhiyun 		if (r) {
292*4882a593Smuzhiyun 			DRM_ERROR("Failed to get dummy destroy msg\n");
293*4882a593Smuzhiyun 			return r;
294*4882a593Smuzhiyun 		}
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun 	} else {
297*4882a593Smuzhiyun 		r = radeon_ring_lock(rdev, ring, 64);
298*4882a593Smuzhiyun 		if (r) {
299*4882a593Smuzhiyun 			DRM_ERROR("Failed to lock ring A %d\n", ring->idx);
300*4882a593Smuzhiyun 			return r;
301*4882a593Smuzhiyun 		}
302*4882a593Smuzhiyun 		r = radeon_fence_emit(rdev, fence, ring->idx);
303*4882a593Smuzhiyun 		if (r) {
304*4882a593Smuzhiyun 			DRM_ERROR("Failed to emit fence\n");
305*4882a593Smuzhiyun 			radeon_ring_unlock_undo(rdev, ring);
306*4882a593Smuzhiyun 			return r;
307*4882a593Smuzhiyun 		}
308*4882a593Smuzhiyun 		radeon_ring_unlock_commit(rdev, ring, false);
309*4882a593Smuzhiyun 	}
310*4882a593Smuzhiyun 	return 0;
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun 
radeon_test_ring_sync(struct radeon_device * rdev,struct radeon_ring * ringA,struct radeon_ring * ringB)313*4882a593Smuzhiyun void radeon_test_ring_sync(struct radeon_device *rdev,
314*4882a593Smuzhiyun 			   struct radeon_ring *ringA,
315*4882a593Smuzhiyun 			   struct radeon_ring *ringB)
316*4882a593Smuzhiyun {
317*4882a593Smuzhiyun 	struct radeon_fence *fence1 = NULL, *fence2 = NULL;
318*4882a593Smuzhiyun 	struct radeon_semaphore *semaphore = NULL;
319*4882a593Smuzhiyun 	int r;
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun 	r = radeon_semaphore_create(rdev, &semaphore);
322*4882a593Smuzhiyun 	if (r) {
323*4882a593Smuzhiyun 		DRM_ERROR("Failed to create semaphore\n");
324*4882a593Smuzhiyun 		goto out_cleanup;
325*4882a593Smuzhiyun 	}
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun 	r = radeon_ring_lock(rdev, ringA, 64);
328*4882a593Smuzhiyun 	if (r) {
329*4882a593Smuzhiyun 		DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
330*4882a593Smuzhiyun 		goto out_cleanup;
331*4882a593Smuzhiyun 	}
332*4882a593Smuzhiyun 	radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore);
333*4882a593Smuzhiyun 	radeon_ring_unlock_commit(rdev, ringA, false);
334*4882a593Smuzhiyun 
335*4882a593Smuzhiyun 	r = radeon_test_create_and_emit_fence(rdev, ringA, &fence1);
336*4882a593Smuzhiyun 	if (r)
337*4882a593Smuzhiyun 		goto out_cleanup;
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun 	r = radeon_ring_lock(rdev, ringA, 64);
340*4882a593Smuzhiyun 	if (r) {
341*4882a593Smuzhiyun 		DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
342*4882a593Smuzhiyun 		goto out_cleanup;
343*4882a593Smuzhiyun 	}
344*4882a593Smuzhiyun 	radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore);
345*4882a593Smuzhiyun 	radeon_ring_unlock_commit(rdev, ringA, false);
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun 	r = radeon_test_create_and_emit_fence(rdev, ringA, &fence2);
348*4882a593Smuzhiyun 	if (r)
349*4882a593Smuzhiyun 		goto out_cleanup;
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun 	msleep(1000);
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun 	if (radeon_fence_signaled(fence1)) {
354*4882a593Smuzhiyun 		DRM_ERROR("Fence 1 signaled without waiting for semaphore.\n");
355*4882a593Smuzhiyun 		goto out_cleanup;
356*4882a593Smuzhiyun 	}
357*4882a593Smuzhiyun 
358*4882a593Smuzhiyun 	r = radeon_ring_lock(rdev, ringB, 64);
359*4882a593Smuzhiyun 	if (r) {
360*4882a593Smuzhiyun 		DRM_ERROR("Failed to lock ring B %p\n", ringB);
361*4882a593Smuzhiyun 		goto out_cleanup;
362*4882a593Smuzhiyun 	}
363*4882a593Smuzhiyun 	radeon_semaphore_emit_signal(rdev, ringB->idx, semaphore);
364*4882a593Smuzhiyun 	radeon_ring_unlock_commit(rdev, ringB, false);
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun 	r = radeon_fence_wait(fence1, false);
367*4882a593Smuzhiyun 	if (r) {
368*4882a593Smuzhiyun 		DRM_ERROR("Failed to wait for sync fence 1\n");
369*4882a593Smuzhiyun 		goto out_cleanup;
370*4882a593Smuzhiyun 	}
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun 	msleep(1000);
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun 	if (radeon_fence_signaled(fence2)) {
375*4882a593Smuzhiyun 		DRM_ERROR("Fence 2 signaled without waiting for semaphore.\n");
376*4882a593Smuzhiyun 		goto out_cleanup;
377*4882a593Smuzhiyun 	}
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun 	r = radeon_ring_lock(rdev, ringB, 64);
380*4882a593Smuzhiyun 	if (r) {
381*4882a593Smuzhiyun 		DRM_ERROR("Failed to lock ring B %p\n", ringB);
382*4882a593Smuzhiyun 		goto out_cleanup;
383*4882a593Smuzhiyun 	}
384*4882a593Smuzhiyun 	radeon_semaphore_emit_signal(rdev, ringB->idx, semaphore);
385*4882a593Smuzhiyun 	radeon_ring_unlock_commit(rdev, ringB, false);
386*4882a593Smuzhiyun 
387*4882a593Smuzhiyun 	r = radeon_fence_wait(fence2, false);
388*4882a593Smuzhiyun 	if (r) {
389*4882a593Smuzhiyun 		DRM_ERROR("Failed to wait for sync fence 1\n");
390*4882a593Smuzhiyun 		goto out_cleanup;
391*4882a593Smuzhiyun 	}
392*4882a593Smuzhiyun 
393*4882a593Smuzhiyun out_cleanup:
394*4882a593Smuzhiyun 	radeon_semaphore_free(rdev, &semaphore, NULL);
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun 	if (fence1)
397*4882a593Smuzhiyun 		radeon_fence_unref(&fence1);
398*4882a593Smuzhiyun 
399*4882a593Smuzhiyun 	if (fence2)
400*4882a593Smuzhiyun 		radeon_fence_unref(&fence2);
401*4882a593Smuzhiyun 
402*4882a593Smuzhiyun 	if (r)
403*4882a593Smuzhiyun 		pr_warn("Error while testing ring sync (%d)\n", r);
404*4882a593Smuzhiyun }
405*4882a593Smuzhiyun 
radeon_test_ring_sync2(struct radeon_device * rdev,struct radeon_ring * ringA,struct radeon_ring * ringB,struct radeon_ring * ringC)406*4882a593Smuzhiyun static void radeon_test_ring_sync2(struct radeon_device *rdev,
407*4882a593Smuzhiyun 			    struct radeon_ring *ringA,
408*4882a593Smuzhiyun 			    struct radeon_ring *ringB,
409*4882a593Smuzhiyun 			    struct radeon_ring *ringC)
410*4882a593Smuzhiyun {
411*4882a593Smuzhiyun 	struct radeon_fence *fenceA = NULL, *fenceB = NULL;
412*4882a593Smuzhiyun 	struct radeon_semaphore *semaphore = NULL;
413*4882a593Smuzhiyun 	bool sigA, sigB;
414*4882a593Smuzhiyun 	int i, r;
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun 	r = radeon_semaphore_create(rdev, &semaphore);
417*4882a593Smuzhiyun 	if (r) {
418*4882a593Smuzhiyun 		DRM_ERROR("Failed to create semaphore\n");
419*4882a593Smuzhiyun 		goto out_cleanup;
420*4882a593Smuzhiyun 	}
421*4882a593Smuzhiyun 
422*4882a593Smuzhiyun 	r = radeon_ring_lock(rdev, ringA, 64);
423*4882a593Smuzhiyun 	if (r) {
424*4882a593Smuzhiyun 		DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
425*4882a593Smuzhiyun 		goto out_cleanup;
426*4882a593Smuzhiyun 	}
427*4882a593Smuzhiyun 	radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore);
428*4882a593Smuzhiyun 	radeon_ring_unlock_commit(rdev, ringA, false);
429*4882a593Smuzhiyun 
430*4882a593Smuzhiyun 	r = radeon_test_create_and_emit_fence(rdev, ringA, &fenceA);
431*4882a593Smuzhiyun 	if (r)
432*4882a593Smuzhiyun 		goto out_cleanup;
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun 	r = radeon_ring_lock(rdev, ringB, 64);
435*4882a593Smuzhiyun 	if (r) {
436*4882a593Smuzhiyun 		DRM_ERROR("Failed to lock ring B %d\n", ringB->idx);
437*4882a593Smuzhiyun 		goto out_cleanup;
438*4882a593Smuzhiyun 	}
439*4882a593Smuzhiyun 	radeon_semaphore_emit_wait(rdev, ringB->idx, semaphore);
440*4882a593Smuzhiyun 	radeon_ring_unlock_commit(rdev, ringB, false);
441*4882a593Smuzhiyun 	r = radeon_test_create_and_emit_fence(rdev, ringB, &fenceB);
442*4882a593Smuzhiyun 	if (r)
443*4882a593Smuzhiyun 		goto out_cleanup;
444*4882a593Smuzhiyun 
445*4882a593Smuzhiyun 	msleep(1000);
446*4882a593Smuzhiyun 
447*4882a593Smuzhiyun 	if (radeon_fence_signaled(fenceA)) {
448*4882a593Smuzhiyun 		DRM_ERROR("Fence A signaled without waiting for semaphore.\n");
449*4882a593Smuzhiyun 		goto out_cleanup;
450*4882a593Smuzhiyun 	}
451*4882a593Smuzhiyun 	if (radeon_fence_signaled(fenceB)) {
452*4882a593Smuzhiyun 		DRM_ERROR("Fence B signaled without waiting for semaphore.\n");
453*4882a593Smuzhiyun 		goto out_cleanup;
454*4882a593Smuzhiyun 	}
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun 	r = radeon_ring_lock(rdev, ringC, 64);
457*4882a593Smuzhiyun 	if (r) {
458*4882a593Smuzhiyun 		DRM_ERROR("Failed to lock ring B %p\n", ringC);
459*4882a593Smuzhiyun 		goto out_cleanup;
460*4882a593Smuzhiyun 	}
461*4882a593Smuzhiyun 	radeon_semaphore_emit_signal(rdev, ringC->idx, semaphore);
462*4882a593Smuzhiyun 	radeon_ring_unlock_commit(rdev, ringC, false);
463*4882a593Smuzhiyun 
464*4882a593Smuzhiyun 	for (i = 0; i < 30; ++i) {
465*4882a593Smuzhiyun 		msleep(100);
466*4882a593Smuzhiyun 		sigA = radeon_fence_signaled(fenceA);
467*4882a593Smuzhiyun 		sigB = radeon_fence_signaled(fenceB);
468*4882a593Smuzhiyun 		if (sigA || sigB)
469*4882a593Smuzhiyun 			break;
470*4882a593Smuzhiyun 	}
471*4882a593Smuzhiyun 
472*4882a593Smuzhiyun 	if (!sigA && !sigB) {
473*4882a593Smuzhiyun 		DRM_ERROR("Neither fence A nor B has been signaled\n");
474*4882a593Smuzhiyun 		goto out_cleanup;
475*4882a593Smuzhiyun 	} else if (sigA && sigB) {
476*4882a593Smuzhiyun 		DRM_ERROR("Both fence A and B has been signaled\n");
477*4882a593Smuzhiyun 		goto out_cleanup;
478*4882a593Smuzhiyun 	}
479*4882a593Smuzhiyun 
480*4882a593Smuzhiyun 	DRM_INFO("Fence %c was first signaled\n", sigA ? 'A' : 'B');
481*4882a593Smuzhiyun 
482*4882a593Smuzhiyun 	r = radeon_ring_lock(rdev, ringC, 64);
483*4882a593Smuzhiyun 	if (r) {
484*4882a593Smuzhiyun 		DRM_ERROR("Failed to lock ring B %p\n", ringC);
485*4882a593Smuzhiyun 		goto out_cleanup;
486*4882a593Smuzhiyun 	}
487*4882a593Smuzhiyun 	radeon_semaphore_emit_signal(rdev, ringC->idx, semaphore);
488*4882a593Smuzhiyun 	radeon_ring_unlock_commit(rdev, ringC, false);
489*4882a593Smuzhiyun 
490*4882a593Smuzhiyun 	msleep(1000);
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun 	r = radeon_fence_wait(fenceA, false);
493*4882a593Smuzhiyun 	if (r) {
494*4882a593Smuzhiyun 		DRM_ERROR("Failed to wait for sync fence A\n");
495*4882a593Smuzhiyun 		goto out_cleanup;
496*4882a593Smuzhiyun 	}
497*4882a593Smuzhiyun 	r = radeon_fence_wait(fenceB, false);
498*4882a593Smuzhiyun 	if (r) {
499*4882a593Smuzhiyun 		DRM_ERROR("Failed to wait for sync fence B\n");
500*4882a593Smuzhiyun 		goto out_cleanup;
501*4882a593Smuzhiyun 	}
502*4882a593Smuzhiyun 
503*4882a593Smuzhiyun out_cleanup:
504*4882a593Smuzhiyun 	radeon_semaphore_free(rdev, &semaphore, NULL);
505*4882a593Smuzhiyun 
506*4882a593Smuzhiyun 	if (fenceA)
507*4882a593Smuzhiyun 		radeon_fence_unref(&fenceA);
508*4882a593Smuzhiyun 
509*4882a593Smuzhiyun 	if (fenceB)
510*4882a593Smuzhiyun 		radeon_fence_unref(&fenceB);
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun 	if (r)
513*4882a593Smuzhiyun 		pr_warn("Error while testing ring sync (%d)\n", r);
514*4882a593Smuzhiyun }
515*4882a593Smuzhiyun 
radeon_test_sync_possible(struct radeon_ring * ringA,struct radeon_ring * ringB)516*4882a593Smuzhiyun static bool radeon_test_sync_possible(struct radeon_ring *ringA,
517*4882a593Smuzhiyun 				      struct radeon_ring *ringB)
518*4882a593Smuzhiyun {
519*4882a593Smuzhiyun 	if (ringA->idx == TN_RING_TYPE_VCE2_INDEX &&
520*4882a593Smuzhiyun 	    ringB->idx == TN_RING_TYPE_VCE1_INDEX)
521*4882a593Smuzhiyun 		return false;
522*4882a593Smuzhiyun 
523*4882a593Smuzhiyun 	return true;
524*4882a593Smuzhiyun }
525*4882a593Smuzhiyun 
radeon_test_syncing(struct radeon_device * rdev)526*4882a593Smuzhiyun void radeon_test_syncing(struct radeon_device *rdev)
527*4882a593Smuzhiyun {
528*4882a593Smuzhiyun 	int i, j, k;
529*4882a593Smuzhiyun 
530*4882a593Smuzhiyun 	for (i = 1; i < RADEON_NUM_RINGS; ++i) {
531*4882a593Smuzhiyun 		struct radeon_ring *ringA = &rdev->ring[i];
532*4882a593Smuzhiyun 		if (!ringA->ready)
533*4882a593Smuzhiyun 			continue;
534*4882a593Smuzhiyun 
535*4882a593Smuzhiyun 		for (j = 0; j < i; ++j) {
536*4882a593Smuzhiyun 			struct radeon_ring *ringB = &rdev->ring[j];
537*4882a593Smuzhiyun 			if (!ringB->ready)
538*4882a593Smuzhiyun 				continue;
539*4882a593Smuzhiyun 
540*4882a593Smuzhiyun 			if (!radeon_test_sync_possible(ringA, ringB))
541*4882a593Smuzhiyun 				continue;
542*4882a593Smuzhiyun 
543*4882a593Smuzhiyun 			DRM_INFO("Testing syncing between rings %d and %d...\n", i, j);
544*4882a593Smuzhiyun 			radeon_test_ring_sync(rdev, ringA, ringB);
545*4882a593Smuzhiyun 
546*4882a593Smuzhiyun 			DRM_INFO("Testing syncing between rings %d and %d...\n", j, i);
547*4882a593Smuzhiyun 			radeon_test_ring_sync(rdev, ringB, ringA);
548*4882a593Smuzhiyun 
549*4882a593Smuzhiyun 			for (k = 0; k < j; ++k) {
550*4882a593Smuzhiyun 				struct radeon_ring *ringC = &rdev->ring[k];
551*4882a593Smuzhiyun 				if (!ringC->ready)
552*4882a593Smuzhiyun 					continue;
553*4882a593Smuzhiyun 
554*4882a593Smuzhiyun 				if (!radeon_test_sync_possible(ringA, ringC))
555*4882a593Smuzhiyun 					continue;
556*4882a593Smuzhiyun 
557*4882a593Smuzhiyun 				if (!radeon_test_sync_possible(ringB, ringC))
558*4882a593Smuzhiyun 					continue;
559*4882a593Smuzhiyun 
560*4882a593Smuzhiyun 				DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, j, k);
561*4882a593Smuzhiyun 				radeon_test_ring_sync2(rdev, ringA, ringB, ringC);
562*4882a593Smuzhiyun 
563*4882a593Smuzhiyun 				DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, k, j);
564*4882a593Smuzhiyun 				radeon_test_ring_sync2(rdev, ringA, ringC, ringB);
565*4882a593Smuzhiyun 
566*4882a593Smuzhiyun 				DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, i, k);
567*4882a593Smuzhiyun 				radeon_test_ring_sync2(rdev, ringB, ringA, ringC);
568*4882a593Smuzhiyun 
569*4882a593Smuzhiyun 				DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, k, i);
570*4882a593Smuzhiyun 				radeon_test_ring_sync2(rdev, ringB, ringC, ringA);
571*4882a593Smuzhiyun 
572*4882a593Smuzhiyun 				DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, i, j);
573*4882a593Smuzhiyun 				radeon_test_ring_sync2(rdev, ringC, ringA, ringB);
574*4882a593Smuzhiyun 
575*4882a593Smuzhiyun 				DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, j, i);
576*4882a593Smuzhiyun 				radeon_test_ring_sync2(rdev, ringC, ringB, ringA);
577*4882a593Smuzhiyun 			}
578*4882a593Smuzhiyun 		}
579*4882a593Smuzhiyun 	}
580*4882a593Smuzhiyun }
581