1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2012 Advanced Micro Devices, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a
5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"),
6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation
7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the
9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions:
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in
12*4882a593Smuzhiyun * all copies or substantial portions of the Software.
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE.
21*4882a593Smuzhiyun *
22*4882a593Smuzhiyun * based on nouveau_prime.c
23*4882a593Smuzhiyun *
24*4882a593Smuzhiyun * Authors: Alex Deucher
25*4882a593Smuzhiyun */
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #include <linux/dma-buf.h>
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #include <drm/drm_prime.h>
30*4882a593Smuzhiyun #include <drm/radeon_drm.h>
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #include "radeon.h"
33*4882a593Smuzhiyun
radeon_gem_prime_get_sg_table(struct drm_gem_object * obj)34*4882a593Smuzhiyun struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun struct radeon_bo *bo = gem_to_radeon_bo(obj);
37*4882a593Smuzhiyun int npages = bo->tbo.num_pages;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun return drm_prime_pages_to_sg(obj->dev, bo->tbo.ttm->pages, npages);
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
radeon_gem_prime_vmap(struct drm_gem_object * obj)42*4882a593Smuzhiyun void *radeon_gem_prime_vmap(struct drm_gem_object *obj)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun struct radeon_bo *bo = gem_to_radeon_bo(obj);
45*4882a593Smuzhiyun int ret;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun ret = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages,
48*4882a593Smuzhiyun &bo->dma_buf_vmap);
49*4882a593Smuzhiyun if (ret)
50*4882a593Smuzhiyun return ERR_PTR(ret);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun return bo->dma_buf_vmap.virtual;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
radeon_gem_prime_vunmap(struct drm_gem_object * obj,void * vaddr)55*4882a593Smuzhiyun void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun struct radeon_bo *bo = gem_to_radeon_bo(obj);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun ttm_bo_kunmap(&bo->dma_buf_vmap);
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
radeon_gem_prime_import_sg_table(struct drm_device * dev,struct dma_buf_attachment * attach,struct sg_table * sg)62*4882a593Smuzhiyun struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
63*4882a593Smuzhiyun struct dma_buf_attachment *attach,
64*4882a593Smuzhiyun struct sg_table *sg)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun struct dma_resv *resv = attach->dmabuf->resv;
67*4882a593Smuzhiyun struct radeon_device *rdev = dev->dev_private;
68*4882a593Smuzhiyun struct radeon_bo *bo;
69*4882a593Smuzhiyun int ret;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun dma_resv_lock(resv, NULL);
72*4882a593Smuzhiyun ret = radeon_bo_create(rdev, attach->dmabuf->size, PAGE_SIZE, false,
73*4882a593Smuzhiyun RADEON_GEM_DOMAIN_GTT, 0, sg, resv, &bo);
74*4882a593Smuzhiyun dma_resv_unlock(resv);
75*4882a593Smuzhiyun if (ret)
76*4882a593Smuzhiyun return ERR_PTR(ret);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun mutex_lock(&rdev->gem.mutex);
79*4882a593Smuzhiyun list_add_tail(&bo->list, &rdev->gem.objects);
80*4882a593Smuzhiyun mutex_unlock(&rdev->gem.mutex);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun bo->prime_shared_count = 1;
83*4882a593Smuzhiyun return &bo->tbo.base;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
radeon_gem_prime_pin(struct drm_gem_object * obj)86*4882a593Smuzhiyun int radeon_gem_prime_pin(struct drm_gem_object *obj)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun struct radeon_bo *bo = gem_to_radeon_bo(obj);
89*4882a593Smuzhiyun int ret = 0;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun ret = radeon_bo_reserve(bo, false);
92*4882a593Smuzhiyun if (unlikely(ret != 0))
93*4882a593Smuzhiyun return ret;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /* pin buffer into GTT */
96*4882a593Smuzhiyun ret = radeon_bo_pin(bo, RADEON_GEM_DOMAIN_GTT, NULL);
97*4882a593Smuzhiyun if (unlikely(ret))
98*4882a593Smuzhiyun goto error;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun if (bo->tbo.moving) {
101*4882a593Smuzhiyun ret = dma_fence_wait(bo->tbo.moving, false);
102*4882a593Smuzhiyun if (unlikely(ret)) {
103*4882a593Smuzhiyun radeon_bo_unpin(bo);
104*4882a593Smuzhiyun goto error;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun bo->prime_shared_count++;
109*4882a593Smuzhiyun error:
110*4882a593Smuzhiyun radeon_bo_unreserve(bo);
111*4882a593Smuzhiyun return ret;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
radeon_gem_prime_unpin(struct drm_gem_object * obj)114*4882a593Smuzhiyun void radeon_gem_prime_unpin(struct drm_gem_object *obj)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun struct radeon_bo *bo = gem_to_radeon_bo(obj);
117*4882a593Smuzhiyun int ret = 0;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun ret = radeon_bo_reserve(bo, false);
120*4882a593Smuzhiyun if (unlikely(ret != 0))
121*4882a593Smuzhiyun return;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun radeon_bo_unpin(bo);
124*4882a593Smuzhiyun if (bo->prime_shared_count)
125*4882a593Smuzhiyun bo->prime_shared_count--;
126*4882a593Smuzhiyun radeon_bo_unreserve(bo);
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun
radeon_gem_prime_export(struct drm_gem_object * gobj,int flags)130*4882a593Smuzhiyun struct dma_buf *radeon_gem_prime_export(struct drm_gem_object *gobj,
131*4882a593Smuzhiyun int flags)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun struct radeon_bo *bo = gem_to_radeon_bo(gobj);
134*4882a593Smuzhiyun if (radeon_ttm_tt_has_userptr(bo->rdev, bo->tbo.ttm))
135*4882a593Smuzhiyun return ERR_PTR(-EPERM);
136*4882a593Smuzhiyun return drm_gem_prime_export(gobj, flags);
137*4882a593Smuzhiyun }
138