1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2008 Advanced Micro Devices, Inc.
3*4882a593Smuzhiyun * Copyright 2008 Red Hat Inc.
4*4882a593Smuzhiyun * Copyright 2009 Jerome Glisse.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a
7*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"),
8*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation
9*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the
11*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions:
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in
14*4882a593Smuzhiyun * all copies or substantial portions of the Software.
15*4882a593Smuzhiyun *
16*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE.
23*4882a593Smuzhiyun *
24*4882a593Smuzhiyun * Authors: Dave Airlie
25*4882a593Smuzhiyun * Alex Deucher
26*4882a593Smuzhiyun * Jerome Glisse
27*4882a593Smuzhiyun */
28*4882a593Smuzhiyun #ifndef __RADEON_OBJECT_H__
29*4882a593Smuzhiyun #define __RADEON_OBJECT_H__
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #include <drm/radeon_drm.h>
32*4882a593Smuzhiyun #include "radeon.h"
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /**
35*4882a593Smuzhiyun * radeon_mem_type_to_domain - return domain corresponding to mem_type
36*4882a593Smuzhiyun * @mem_type: ttm memory type
37*4882a593Smuzhiyun *
38*4882a593Smuzhiyun * Returns corresponding domain of the ttm mem_type
39*4882a593Smuzhiyun */
radeon_mem_type_to_domain(u32 mem_type)40*4882a593Smuzhiyun static inline unsigned radeon_mem_type_to_domain(u32 mem_type)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun switch (mem_type) {
43*4882a593Smuzhiyun case TTM_PL_VRAM:
44*4882a593Smuzhiyun return RADEON_GEM_DOMAIN_VRAM;
45*4882a593Smuzhiyun case TTM_PL_TT:
46*4882a593Smuzhiyun return RADEON_GEM_DOMAIN_GTT;
47*4882a593Smuzhiyun case TTM_PL_SYSTEM:
48*4882a593Smuzhiyun return RADEON_GEM_DOMAIN_CPU;
49*4882a593Smuzhiyun default:
50*4882a593Smuzhiyun break;
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun return 0;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /**
56*4882a593Smuzhiyun * radeon_bo_reserve - reserve bo
57*4882a593Smuzhiyun * @bo: bo structure
58*4882a593Smuzhiyun * @no_intr: don't return -ERESTARTSYS on pending signal
59*4882a593Smuzhiyun *
60*4882a593Smuzhiyun * Returns:
61*4882a593Smuzhiyun * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
62*4882a593Smuzhiyun * a signal. Release all buffer reservations and return to user-space.
63*4882a593Smuzhiyun */
radeon_bo_reserve(struct radeon_bo * bo,bool no_intr)64*4882a593Smuzhiyun static inline int radeon_bo_reserve(struct radeon_bo *bo, bool no_intr)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun int r;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL);
69*4882a593Smuzhiyun if (unlikely(r != 0)) {
70*4882a593Smuzhiyun if (r != -ERESTARTSYS)
71*4882a593Smuzhiyun dev_err(bo->rdev->dev, "%p reserve failed\n", bo);
72*4882a593Smuzhiyun return r;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun return 0;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
radeon_bo_unreserve(struct radeon_bo * bo)77*4882a593Smuzhiyun static inline void radeon_bo_unreserve(struct radeon_bo *bo)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun ttm_bo_unreserve(&bo->tbo);
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /**
83*4882a593Smuzhiyun * radeon_bo_gpu_offset - return GPU offset of bo
84*4882a593Smuzhiyun * @bo: radeon object for which we query the offset
85*4882a593Smuzhiyun *
86*4882a593Smuzhiyun * Returns current GPU offset of the object.
87*4882a593Smuzhiyun *
88*4882a593Smuzhiyun * Note: object should either be pinned or reserved when calling this
89*4882a593Smuzhiyun * function, it might be useful to add check for this for debugging.
90*4882a593Smuzhiyun */
radeon_bo_gpu_offset(struct radeon_bo * bo)91*4882a593Smuzhiyun static inline u64 radeon_bo_gpu_offset(struct radeon_bo *bo)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun struct radeon_device *rdev;
94*4882a593Smuzhiyun u64 start = 0;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun rdev = radeon_get_rdev(bo->tbo.bdev);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun switch (bo->tbo.mem.mem_type) {
99*4882a593Smuzhiyun case TTM_PL_TT:
100*4882a593Smuzhiyun start = rdev->mc.gtt_start;
101*4882a593Smuzhiyun break;
102*4882a593Smuzhiyun case TTM_PL_VRAM:
103*4882a593Smuzhiyun start = rdev->mc.vram_start;
104*4882a593Smuzhiyun break;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun return (bo->tbo.mem.start << PAGE_SHIFT) + start;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
radeon_bo_size(struct radeon_bo * bo)110*4882a593Smuzhiyun static inline unsigned long radeon_bo_size(struct radeon_bo *bo)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun return bo->tbo.num_pages << PAGE_SHIFT;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
radeon_bo_ngpu_pages(struct radeon_bo * bo)115*4882a593Smuzhiyun static inline unsigned radeon_bo_ngpu_pages(struct radeon_bo *bo)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun return (bo->tbo.num_pages << PAGE_SHIFT) / RADEON_GPU_PAGE_SIZE;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
radeon_bo_gpu_page_alignment(struct radeon_bo * bo)120*4882a593Smuzhiyun static inline unsigned radeon_bo_gpu_page_alignment(struct radeon_bo *bo)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / RADEON_GPU_PAGE_SIZE;
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun /**
126*4882a593Smuzhiyun * radeon_bo_mmap_offset - return mmap offset of bo
127*4882a593Smuzhiyun * @bo: radeon object for which we query the offset
128*4882a593Smuzhiyun *
129*4882a593Smuzhiyun * Returns mmap offset of the object.
130*4882a593Smuzhiyun */
radeon_bo_mmap_offset(struct radeon_bo * bo)131*4882a593Smuzhiyun static inline u64 radeon_bo_mmap_offset(struct radeon_bo *bo)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun return drm_vma_node_offset_addr(&bo->tbo.base.vma_node);
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun extern int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type,
137*4882a593Smuzhiyun bool no_wait);
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun extern int radeon_bo_create(struct radeon_device *rdev,
140*4882a593Smuzhiyun unsigned long size, int byte_align,
141*4882a593Smuzhiyun bool kernel, u32 domain, u32 flags,
142*4882a593Smuzhiyun struct sg_table *sg,
143*4882a593Smuzhiyun struct dma_resv *resv,
144*4882a593Smuzhiyun struct radeon_bo **bo_ptr);
145*4882a593Smuzhiyun extern int radeon_bo_kmap(struct radeon_bo *bo, void **ptr);
146*4882a593Smuzhiyun extern void radeon_bo_kunmap(struct radeon_bo *bo);
147*4882a593Smuzhiyun extern struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo);
148*4882a593Smuzhiyun extern void radeon_bo_unref(struct radeon_bo **bo);
149*4882a593Smuzhiyun extern int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr);
150*4882a593Smuzhiyun extern int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain,
151*4882a593Smuzhiyun u64 max_offset, u64 *gpu_addr);
152*4882a593Smuzhiyun extern int radeon_bo_unpin(struct radeon_bo *bo);
153*4882a593Smuzhiyun extern int radeon_bo_evict_vram(struct radeon_device *rdev);
154*4882a593Smuzhiyun extern void radeon_bo_force_delete(struct radeon_device *rdev);
155*4882a593Smuzhiyun extern int radeon_bo_init(struct radeon_device *rdev);
156*4882a593Smuzhiyun extern void radeon_bo_fini(struct radeon_device *rdev);
157*4882a593Smuzhiyun extern int radeon_bo_list_validate(struct radeon_device *rdev,
158*4882a593Smuzhiyun struct ww_acquire_ctx *ticket,
159*4882a593Smuzhiyun struct list_head *head, int ring);
160*4882a593Smuzhiyun extern int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
161*4882a593Smuzhiyun u32 tiling_flags, u32 pitch);
162*4882a593Smuzhiyun extern void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
163*4882a593Smuzhiyun u32 *tiling_flags, u32 *pitch);
164*4882a593Smuzhiyun extern int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
165*4882a593Smuzhiyun bool force_drop);
166*4882a593Smuzhiyun extern void radeon_bo_move_notify(struct ttm_buffer_object *bo,
167*4882a593Smuzhiyun bool evict,
168*4882a593Smuzhiyun struct ttm_resource *new_mem);
169*4882a593Smuzhiyun extern int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
170*4882a593Smuzhiyun extern int radeon_bo_get_surface_reg(struct radeon_bo *bo);
171*4882a593Smuzhiyun extern void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence,
172*4882a593Smuzhiyun bool shared);
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun /*
175*4882a593Smuzhiyun * sub allocation
176*4882a593Smuzhiyun */
177*4882a593Smuzhiyun
radeon_sa_bo_gpu_addr(struct radeon_sa_bo * sa_bo)178*4882a593Smuzhiyun static inline uint64_t radeon_sa_bo_gpu_addr(struct radeon_sa_bo *sa_bo)
179*4882a593Smuzhiyun {
180*4882a593Smuzhiyun return sa_bo->manager->gpu_addr + sa_bo->soffset;
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun
radeon_sa_bo_cpu_addr(struct radeon_sa_bo * sa_bo)183*4882a593Smuzhiyun static inline void * radeon_sa_bo_cpu_addr(struct radeon_sa_bo *sa_bo)
184*4882a593Smuzhiyun {
185*4882a593Smuzhiyun return sa_bo->manager->cpu_ptr + sa_bo->soffset;
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun extern int radeon_sa_bo_manager_init(struct radeon_device *rdev,
189*4882a593Smuzhiyun struct radeon_sa_manager *sa_manager,
190*4882a593Smuzhiyun unsigned size, u32 align, u32 domain,
191*4882a593Smuzhiyun u32 flags);
192*4882a593Smuzhiyun extern void radeon_sa_bo_manager_fini(struct radeon_device *rdev,
193*4882a593Smuzhiyun struct radeon_sa_manager *sa_manager);
194*4882a593Smuzhiyun extern int radeon_sa_bo_manager_start(struct radeon_device *rdev,
195*4882a593Smuzhiyun struct radeon_sa_manager *sa_manager);
196*4882a593Smuzhiyun extern int radeon_sa_bo_manager_suspend(struct radeon_device *rdev,
197*4882a593Smuzhiyun struct radeon_sa_manager *sa_manager);
198*4882a593Smuzhiyun extern int radeon_sa_bo_new(struct radeon_device *rdev,
199*4882a593Smuzhiyun struct radeon_sa_manager *sa_manager,
200*4882a593Smuzhiyun struct radeon_sa_bo **sa_bo,
201*4882a593Smuzhiyun unsigned size, unsigned align);
202*4882a593Smuzhiyun extern void radeon_sa_bo_free(struct radeon_device *rdev,
203*4882a593Smuzhiyun struct radeon_sa_bo **sa_bo,
204*4882a593Smuzhiyun struct radeon_fence *fence);
205*4882a593Smuzhiyun #if defined(CONFIG_DEBUG_FS)
206*4882a593Smuzhiyun extern void radeon_sa_bo_dump_debug_info(struct radeon_sa_manager *sa_manager,
207*4882a593Smuzhiyun struct seq_file *m);
208*4882a593Smuzhiyun #endif
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun #endif
212