1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright © 2007 David Airlie
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a
5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"),
6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation
7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the
9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions:
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * The above copyright notice and this permission notice (including the next
12*4882a593Smuzhiyun * paragraph) shall be included in all copies or substantial portions of the
13*4882a593Smuzhiyun * Software.
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18*4882a593Smuzhiyun * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19*4882a593Smuzhiyun * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20*4882a593Smuzhiyun * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21*4882a593Smuzhiyun * DEALINGS IN THE SOFTWARE.
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * Authors:
24*4882a593Smuzhiyun * David Airlie
25*4882a593Smuzhiyun */
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #include <linux/module.h>
28*4882a593Smuzhiyun #include <linux/pci.h>
29*4882a593Smuzhiyun #include <linux/pm_runtime.h>
30*4882a593Smuzhiyun #include <linux/slab.h>
31*4882a593Smuzhiyun #include <linux/vga_switcheroo.h>
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #include <drm/drm_crtc.h>
34*4882a593Smuzhiyun #include <drm/drm_crtc_helper.h>
35*4882a593Smuzhiyun #include <drm/drm_fb_helper.h>
36*4882a593Smuzhiyun #include <drm/drm_fourcc.h>
37*4882a593Smuzhiyun #include <drm/radeon_drm.h>
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #include "radeon.h"
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* object hierarchy -
42*4882a593Smuzhiyun * this contains a helper + a radeon fb
43*4882a593Smuzhiyun * the helper contains a pointer to radeon framebuffer baseclass.
44*4882a593Smuzhiyun */
45*4882a593Smuzhiyun struct radeon_fbdev {
46*4882a593Smuzhiyun struct drm_fb_helper helper; /* must be first */
47*4882a593Smuzhiyun struct drm_framebuffer fb;
48*4882a593Smuzhiyun struct radeon_device *rdev;
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun static int
radeonfb_open(struct fb_info * info,int user)52*4882a593Smuzhiyun radeonfb_open(struct fb_info *info, int user)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun struct radeon_fbdev *rfbdev = info->par;
55*4882a593Smuzhiyun struct radeon_device *rdev = rfbdev->rdev;
56*4882a593Smuzhiyun int ret = pm_runtime_get_sync(rdev->ddev->dev);
57*4882a593Smuzhiyun if (ret < 0 && ret != -EACCES) {
58*4882a593Smuzhiyun pm_runtime_mark_last_busy(rdev->ddev->dev);
59*4882a593Smuzhiyun pm_runtime_put_autosuspend(rdev->ddev->dev);
60*4882a593Smuzhiyun return ret;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun return 0;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun static int
radeonfb_release(struct fb_info * info,int user)66*4882a593Smuzhiyun radeonfb_release(struct fb_info *info, int user)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun struct radeon_fbdev *rfbdev = info->par;
69*4882a593Smuzhiyun struct radeon_device *rdev = rfbdev->rdev;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun pm_runtime_mark_last_busy(rdev->ddev->dev);
72*4882a593Smuzhiyun pm_runtime_put_autosuspend(rdev->ddev->dev);
73*4882a593Smuzhiyun return 0;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun static const struct fb_ops radeonfb_ops = {
77*4882a593Smuzhiyun .owner = THIS_MODULE,
78*4882a593Smuzhiyun DRM_FB_HELPER_DEFAULT_OPS,
79*4882a593Smuzhiyun .fb_open = radeonfb_open,
80*4882a593Smuzhiyun .fb_release = radeonfb_release,
81*4882a593Smuzhiyun .fb_fillrect = drm_fb_helper_cfb_fillrect,
82*4882a593Smuzhiyun .fb_copyarea = drm_fb_helper_cfb_copyarea,
83*4882a593Smuzhiyun .fb_imageblit = drm_fb_helper_cfb_imageblit,
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun
radeon_align_pitch(struct radeon_device * rdev,int width,int cpp,bool tiled)87*4882a593Smuzhiyun int radeon_align_pitch(struct radeon_device *rdev, int width, int cpp, bool tiled)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun int aligned = width;
90*4882a593Smuzhiyun int align_large = (ASIC_IS_AVIVO(rdev)) || tiled;
91*4882a593Smuzhiyun int pitch_mask = 0;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun switch (cpp) {
94*4882a593Smuzhiyun case 1:
95*4882a593Smuzhiyun pitch_mask = align_large ? 255 : 127;
96*4882a593Smuzhiyun break;
97*4882a593Smuzhiyun case 2:
98*4882a593Smuzhiyun pitch_mask = align_large ? 127 : 31;
99*4882a593Smuzhiyun break;
100*4882a593Smuzhiyun case 3:
101*4882a593Smuzhiyun case 4:
102*4882a593Smuzhiyun pitch_mask = align_large ? 63 : 15;
103*4882a593Smuzhiyun break;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun aligned += pitch_mask;
107*4882a593Smuzhiyun aligned &= ~pitch_mask;
108*4882a593Smuzhiyun return aligned * cpp;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
radeonfb_destroy_pinned_object(struct drm_gem_object * gobj)111*4882a593Smuzhiyun static void radeonfb_destroy_pinned_object(struct drm_gem_object *gobj)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun struct radeon_bo *rbo = gem_to_radeon_bo(gobj);
114*4882a593Smuzhiyun int ret;
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun ret = radeon_bo_reserve(rbo, false);
117*4882a593Smuzhiyun if (likely(ret == 0)) {
118*4882a593Smuzhiyun radeon_bo_kunmap(rbo);
119*4882a593Smuzhiyun radeon_bo_unpin(rbo);
120*4882a593Smuzhiyun radeon_bo_unreserve(rbo);
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun drm_gem_object_put(gobj);
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun
radeonfb_create_pinned_object(struct radeon_fbdev * rfbdev,struct drm_mode_fb_cmd2 * mode_cmd,struct drm_gem_object ** gobj_p)125*4882a593Smuzhiyun static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
126*4882a593Smuzhiyun struct drm_mode_fb_cmd2 *mode_cmd,
127*4882a593Smuzhiyun struct drm_gem_object **gobj_p)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun const struct drm_format_info *info;
130*4882a593Smuzhiyun struct radeon_device *rdev = rfbdev->rdev;
131*4882a593Smuzhiyun struct drm_gem_object *gobj = NULL;
132*4882a593Smuzhiyun struct radeon_bo *rbo = NULL;
133*4882a593Smuzhiyun bool fb_tiled = false; /* useful for testing */
134*4882a593Smuzhiyun u32 tiling_flags = 0;
135*4882a593Smuzhiyun int ret;
136*4882a593Smuzhiyun int aligned_size, size;
137*4882a593Smuzhiyun int height = mode_cmd->height;
138*4882a593Smuzhiyun u32 cpp;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun info = drm_get_format_info(rdev->ddev, mode_cmd);
141*4882a593Smuzhiyun cpp = info->cpp[0];
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun /* need to align pitch with crtc limits */
144*4882a593Smuzhiyun mode_cmd->pitches[0] = radeon_align_pitch(rdev, mode_cmd->width, cpp,
145*4882a593Smuzhiyun fb_tiled);
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun if (rdev->family >= CHIP_R600)
148*4882a593Smuzhiyun height = ALIGN(mode_cmd->height, 8);
149*4882a593Smuzhiyun size = mode_cmd->pitches[0] * height;
150*4882a593Smuzhiyun aligned_size = ALIGN(size, PAGE_SIZE);
151*4882a593Smuzhiyun ret = radeon_gem_object_create(rdev, aligned_size, 0,
152*4882a593Smuzhiyun RADEON_GEM_DOMAIN_VRAM,
153*4882a593Smuzhiyun 0, true, &gobj);
154*4882a593Smuzhiyun if (ret) {
155*4882a593Smuzhiyun pr_err("failed to allocate framebuffer (%d)\n", aligned_size);
156*4882a593Smuzhiyun return -ENOMEM;
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun rbo = gem_to_radeon_bo(gobj);
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun if (fb_tiled)
161*4882a593Smuzhiyun tiling_flags = RADEON_TILING_MACRO;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun #ifdef __BIG_ENDIAN
164*4882a593Smuzhiyun switch (cpp) {
165*4882a593Smuzhiyun case 4:
166*4882a593Smuzhiyun tiling_flags |= RADEON_TILING_SWAP_32BIT;
167*4882a593Smuzhiyun break;
168*4882a593Smuzhiyun case 2:
169*4882a593Smuzhiyun tiling_flags |= RADEON_TILING_SWAP_16BIT;
170*4882a593Smuzhiyun default:
171*4882a593Smuzhiyun break;
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun #endif
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun if (tiling_flags) {
176*4882a593Smuzhiyun ret = radeon_bo_set_tiling_flags(rbo,
177*4882a593Smuzhiyun tiling_flags | RADEON_TILING_SURFACE,
178*4882a593Smuzhiyun mode_cmd->pitches[0]);
179*4882a593Smuzhiyun if (ret)
180*4882a593Smuzhiyun dev_err(rdev->dev, "FB failed to set tiling flags\n");
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun ret = radeon_bo_reserve(rbo, false);
185*4882a593Smuzhiyun if (unlikely(ret != 0))
186*4882a593Smuzhiyun goto out_unref;
187*4882a593Smuzhiyun /* Only 27 bit offset for legacy CRTC */
188*4882a593Smuzhiyun ret = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
189*4882a593Smuzhiyun ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27,
190*4882a593Smuzhiyun NULL);
191*4882a593Smuzhiyun if (ret) {
192*4882a593Smuzhiyun radeon_bo_unreserve(rbo);
193*4882a593Smuzhiyun goto out_unref;
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun if (fb_tiled)
196*4882a593Smuzhiyun radeon_bo_check_tiling(rbo, 0, 0);
197*4882a593Smuzhiyun ret = radeon_bo_kmap(rbo, NULL);
198*4882a593Smuzhiyun radeon_bo_unreserve(rbo);
199*4882a593Smuzhiyun if (ret) {
200*4882a593Smuzhiyun goto out_unref;
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun *gobj_p = gobj;
204*4882a593Smuzhiyun return 0;
205*4882a593Smuzhiyun out_unref:
206*4882a593Smuzhiyun radeonfb_destroy_pinned_object(gobj);
207*4882a593Smuzhiyun *gobj_p = NULL;
208*4882a593Smuzhiyun return ret;
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun
radeonfb_create(struct drm_fb_helper * helper,struct drm_fb_helper_surface_size * sizes)211*4882a593Smuzhiyun static int radeonfb_create(struct drm_fb_helper *helper,
212*4882a593Smuzhiyun struct drm_fb_helper_surface_size *sizes)
213*4882a593Smuzhiyun {
214*4882a593Smuzhiyun struct radeon_fbdev *rfbdev =
215*4882a593Smuzhiyun container_of(helper, struct radeon_fbdev, helper);
216*4882a593Smuzhiyun struct radeon_device *rdev = rfbdev->rdev;
217*4882a593Smuzhiyun struct fb_info *info;
218*4882a593Smuzhiyun struct drm_framebuffer *fb = NULL;
219*4882a593Smuzhiyun struct drm_mode_fb_cmd2 mode_cmd;
220*4882a593Smuzhiyun struct drm_gem_object *gobj = NULL;
221*4882a593Smuzhiyun struct radeon_bo *rbo = NULL;
222*4882a593Smuzhiyun int ret;
223*4882a593Smuzhiyun unsigned long tmp;
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun mode_cmd.width = sizes->surface_width;
226*4882a593Smuzhiyun mode_cmd.height = sizes->surface_height;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun /* avivo can't scanout real 24bpp */
229*4882a593Smuzhiyun if ((sizes->surface_bpp == 24) && ASIC_IS_AVIVO(rdev))
230*4882a593Smuzhiyun sizes->surface_bpp = 32;
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
233*4882a593Smuzhiyun sizes->surface_depth);
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun ret = radeonfb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
236*4882a593Smuzhiyun if (ret) {
237*4882a593Smuzhiyun DRM_ERROR("failed to create fbcon object %d\n", ret);
238*4882a593Smuzhiyun return ret;
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun rbo = gem_to_radeon_bo(gobj);
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun /* okay we have an object now allocate the framebuffer */
244*4882a593Smuzhiyun info = drm_fb_helper_alloc_fbi(helper);
245*4882a593Smuzhiyun if (IS_ERR(info)) {
246*4882a593Smuzhiyun ret = PTR_ERR(info);
247*4882a593Smuzhiyun goto out;
248*4882a593Smuzhiyun }
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun /* radeon resume is fragile and needs a vt switch to help it along */
251*4882a593Smuzhiyun info->skip_vt_switch = false;
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun ret = radeon_framebuffer_init(rdev->ddev, &rfbdev->fb, &mode_cmd, gobj);
254*4882a593Smuzhiyun if (ret) {
255*4882a593Smuzhiyun DRM_ERROR("failed to initialize framebuffer %d\n", ret);
256*4882a593Smuzhiyun goto out;
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun fb = &rfbdev->fb;
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun /* setup helper */
262*4882a593Smuzhiyun rfbdev->helper.fb = fb;
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun memset_io(rbo->kptr, 0x0, radeon_bo_size(rbo));
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun info->fbops = &radeonfb_ops;
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start;
269*4882a593Smuzhiyun info->fix.smem_start = rdev->mc.aper_base + tmp;
270*4882a593Smuzhiyun info->fix.smem_len = radeon_bo_size(rbo);
271*4882a593Smuzhiyun info->screen_base = rbo->kptr;
272*4882a593Smuzhiyun info->screen_size = radeon_bo_size(rbo);
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun drm_fb_helper_fill_info(info, &rfbdev->helper, sizes);
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun /* setup aperture base/size for vesafb takeover */
277*4882a593Smuzhiyun info->apertures->ranges[0].base = rdev->ddev->mode_config.fb_base;
278*4882a593Smuzhiyun info->apertures->ranges[0].size = rdev->mc.aper_size;
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun if (info->screen_base == NULL) {
283*4882a593Smuzhiyun ret = -ENOSPC;
284*4882a593Smuzhiyun goto out;
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
288*4882a593Smuzhiyun DRM_INFO("vram apper at 0x%lX\n", (unsigned long)rdev->mc.aper_base);
289*4882a593Smuzhiyun DRM_INFO("size %lu\n", (unsigned long)radeon_bo_size(rbo));
290*4882a593Smuzhiyun DRM_INFO("fb depth is %d\n", fb->format->depth);
291*4882a593Smuzhiyun DRM_INFO(" pitch is %d\n", fb->pitches[0]);
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun vga_switcheroo_client_fb_set(rdev->ddev->pdev, info);
294*4882a593Smuzhiyun return 0;
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun out:
297*4882a593Smuzhiyun if (rbo) {
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun }
300*4882a593Smuzhiyun if (fb && ret) {
301*4882a593Smuzhiyun drm_gem_object_put(gobj);
302*4882a593Smuzhiyun drm_framebuffer_unregister_private(fb);
303*4882a593Smuzhiyun drm_framebuffer_cleanup(fb);
304*4882a593Smuzhiyun kfree(fb);
305*4882a593Smuzhiyun }
306*4882a593Smuzhiyun return ret;
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun
radeon_fbdev_destroy(struct drm_device * dev,struct radeon_fbdev * rfbdev)309*4882a593Smuzhiyun static int radeon_fbdev_destroy(struct drm_device *dev, struct radeon_fbdev *rfbdev)
310*4882a593Smuzhiyun {
311*4882a593Smuzhiyun struct drm_framebuffer *fb = &rfbdev->fb;
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun drm_fb_helper_unregister_fbi(&rfbdev->helper);
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun if (fb->obj[0]) {
316*4882a593Smuzhiyun radeonfb_destroy_pinned_object(fb->obj[0]);
317*4882a593Smuzhiyun fb->obj[0] = NULL;
318*4882a593Smuzhiyun drm_framebuffer_unregister_private(fb);
319*4882a593Smuzhiyun drm_framebuffer_cleanup(fb);
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun drm_fb_helper_fini(&rfbdev->helper);
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun return 0;
324*4882a593Smuzhiyun }
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun static const struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
327*4882a593Smuzhiyun .fb_probe = radeonfb_create,
328*4882a593Smuzhiyun };
329*4882a593Smuzhiyun
radeon_fbdev_init(struct radeon_device * rdev)330*4882a593Smuzhiyun int radeon_fbdev_init(struct radeon_device *rdev)
331*4882a593Smuzhiyun {
332*4882a593Smuzhiyun struct radeon_fbdev *rfbdev;
333*4882a593Smuzhiyun int bpp_sel = 32;
334*4882a593Smuzhiyun int ret;
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun /* don't enable fbdev if no connectors */
337*4882a593Smuzhiyun if (list_empty(&rdev->ddev->mode_config.connector_list))
338*4882a593Smuzhiyun return 0;
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun /* select 8 bpp console on 8MB cards, or 16 bpp on RN50 or 32MB */
341*4882a593Smuzhiyun if (rdev->mc.real_vram_size <= (8*1024*1024))
342*4882a593Smuzhiyun bpp_sel = 8;
343*4882a593Smuzhiyun else if (ASIC_IS_RN50(rdev) ||
344*4882a593Smuzhiyun rdev->mc.real_vram_size <= (32*1024*1024))
345*4882a593Smuzhiyun bpp_sel = 16;
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun rfbdev = kzalloc(sizeof(struct radeon_fbdev), GFP_KERNEL);
348*4882a593Smuzhiyun if (!rfbdev)
349*4882a593Smuzhiyun return -ENOMEM;
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun rfbdev->rdev = rdev;
352*4882a593Smuzhiyun rdev->mode_info.rfbdev = rfbdev;
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun drm_fb_helper_prepare(rdev->ddev, &rfbdev->helper,
355*4882a593Smuzhiyun &radeon_fb_helper_funcs);
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun ret = drm_fb_helper_init(rdev->ddev, &rfbdev->helper);
358*4882a593Smuzhiyun if (ret)
359*4882a593Smuzhiyun goto free;
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun /* disable all the possible outputs/crtcs before entering KMS mode */
362*4882a593Smuzhiyun drm_helper_disable_unused_functions(rdev->ddev);
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun ret = drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
365*4882a593Smuzhiyun if (ret)
366*4882a593Smuzhiyun goto fini;
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun return 0;
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun fini:
371*4882a593Smuzhiyun drm_fb_helper_fini(&rfbdev->helper);
372*4882a593Smuzhiyun free:
373*4882a593Smuzhiyun kfree(rfbdev);
374*4882a593Smuzhiyun return ret;
375*4882a593Smuzhiyun }
376*4882a593Smuzhiyun
radeon_fbdev_fini(struct radeon_device * rdev)377*4882a593Smuzhiyun void radeon_fbdev_fini(struct radeon_device *rdev)
378*4882a593Smuzhiyun {
379*4882a593Smuzhiyun if (!rdev->mode_info.rfbdev)
380*4882a593Smuzhiyun return;
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun radeon_fbdev_destroy(rdev->ddev, rdev->mode_info.rfbdev);
383*4882a593Smuzhiyun kfree(rdev->mode_info.rfbdev);
384*4882a593Smuzhiyun rdev->mode_info.rfbdev = NULL;
385*4882a593Smuzhiyun }
386*4882a593Smuzhiyun
radeon_fbdev_set_suspend(struct radeon_device * rdev,int state)387*4882a593Smuzhiyun void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state)
388*4882a593Smuzhiyun {
389*4882a593Smuzhiyun if (rdev->mode_info.rfbdev)
390*4882a593Smuzhiyun drm_fb_helper_set_suspend(&rdev->mode_info.rfbdev->helper, state);
391*4882a593Smuzhiyun }
392*4882a593Smuzhiyun
radeon_fbdev_robj_is_fb(struct radeon_device * rdev,struct radeon_bo * robj)393*4882a593Smuzhiyun bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj)
394*4882a593Smuzhiyun {
395*4882a593Smuzhiyun if (!rdev->mode_info.rfbdev)
396*4882a593Smuzhiyun return false;
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun if (robj == gem_to_radeon_bo(rdev->mode_info.rfbdev->fb.obj[0]))
399*4882a593Smuzhiyun return true;
400*4882a593Smuzhiyun return false;
401*4882a593Smuzhiyun }
402