1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2007-8 Advanced Micro Devices, Inc.
3*4882a593Smuzhiyun * Copyright 2008 Red Hat Inc.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a
6*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"),
7*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation
8*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the
10*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions:
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in
13*4882a593Smuzhiyun * all copies or substantial portions of the Software.
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE.
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * Authors: Dave Airlie
24*4882a593Smuzhiyun * Alex Deucher
25*4882a593Smuzhiyun */
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #include <linux/pci.h>
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #include <drm/drm_crtc_helper.h>
30*4882a593Smuzhiyun #include <drm/drm_device.h>
31*4882a593Smuzhiyun #include <drm/radeon_drm.h>
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #include "radeon.h"
34*4882a593Smuzhiyun #include "atom.h"
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun extern void
37*4882a593Smuzhiyun radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder,
38*4882a593Smuzhiyun struct drm_connector *drm_connector);
39*4882a593Smuzhiyun extern void
40*4882a593Smuzhiyun radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
41*4882a593Smuzhiyun struct drm_connector *drm_connector);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun
radeon_encoder_clones(struct drm_encoder * encoder)44*4882a593Smuzhiyun static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun struct drm_device *dev = encoder->dev;
47*4882a593Smuzhiyun struct radeon_device *rdev = dev->dev_private;
48*4882a593Smuzhiyun struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
49*4882a593Smuzhiyun struct drm_encoder *clone_encoder;
50*4882a593Smuzhiyun uint32_t index_mask = 0;
51*4882a593Smuzhiyun int count;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* DIG routing gets problematic */
54*4882a593Smuzhiyun if (rdev->family >= CHIP_R600)
55*4882a593Smuzhiyun return index_mask;
56*4882a593Smuzhiyun /* LVDS/TV are too wacky */
57*4882a593Smuzhiyun if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
58*4882a593Smuzhiyun return index_mask;
59*4882a593Smuzhiyun /* DVO requires 2x ppll clocks depending on tmds chip */
60*4882a593Smuzhiyun if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
61*4882a593Smuzhiyun return index_mask;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun count = -1;
64*4882a593Smuzhiyun list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
65*4882a593Smuzhiyun struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
66*4882a593Smuzhiyun count++;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun if (clone_encoder == encoder)
69*4882a593Smuzhiyun continue;
70*4882a593Smuzhiyun if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
71*4882a593Smuzhiyun continue;
72*4882a593Smuzhiyun if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
73*4882a593Smuzhiyun continue;
74*4882a593Smuzhiyun else
75*4882a593Smuzhiyun index_mask |= (1 << count);
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun return index_mask;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
radeon_setup_encoder_clones(struct drm_device * dev)80*4882a593Smuzhiyun void radeon_setup_encoder_clones(struct drm_device *dev)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun struct drm_encoder *encoder;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
85*4882a593Smuzhiyun encoder->possible_clones = radeon_encoder_clones(encoder);
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun uint32_t
radeon_get_encoder_enum(struct drm_device * dev,uint32_t supported_device,uint8_t dac)90*4882a593Smuzhiyun radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun struct radeon_device *rdev = dev->dev_private;
93*4882a593Smuzhiyun uint32_t ret = 0;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun switch (supported_device) {
96*4882a593Smuzhiyun case ATOM_DEVICE_CRT1_SUPPORT:
97*4882a593Smuzhiyun case ATOM_DEVICE_TV1_SUPPORT:
98*4882a593Smuzhiyun case ATOM_DEVICE_TV2_SUPPORT:
99*4882a593Smuzhiyun case ATOM_DEVICE_CRT2_SUPPORT:
100*4882a593Smuzhiyun case ATOM_DEVICE_CV_SUPPORT:
101*4882a593Smuzhiyun switch (dac) {
102*4882a593Smuzhiyun case 1: /* dac a */
103*4882a593Smuzhiyun if ((rdev->family == CHIP_RS300) ||
104*4882a593Smuzhiyun (rdev->family == CHIP_RS400) ||
105*4882a593Smuzhiyun (rdev->family == CHIP_RS480))
106*4882a593Smuzhiyun ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
107*4882a593Smuzhiyun else if (ASIC_IS_AVIVO(rdev))
108*4882a593Smuzhiyun ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1;
109*4882a593Smuzhiyun else
110*4882a593Smuzhiyun ret = ENCODER_INTERNAL_DAC1_ENUM_ID1;
111*4882a593Smuzhiyun break;
112*4882a593Smuzhiyun case 2: /* dac b */
113*4882a593Smuzhiyun if (ASIC_IS_AVIVO(rdev))
114*4882a593Smuzhiyun ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1;
115*4882a593Smuzhiyun else {
116*4882a593Smuzhiyun /*if (rdev->family == CHIP_R200)
117*4882a593Smuzhiyun ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
118*4882a593Smuzhiyun else*/
119*4882a593Smuzhiyun ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun break;
122*4882a593Smuzhiyun case 3: /* external dac */
123*4882a593Smuzhiyun if (ASIC_IS_AVIVO(rdev))
124*4882a593Smuzhiyun ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
125*4882a593Smuzhiyun else
126*4882a593Smuzhiyun ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
127*4882a593Smuzhiyun break;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun break;
130*4882a593Smuzhiyun case ATOM_DEVICE_LCD1_SUPPORT:
131*4882a593Smuzhiyun if (ASIC_IS_AVIVO(rdev))
132*4882a593Smuzhiyun ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
133*4882a593Smuzhiyun else
134*4882a593Smuzhiyun ret = ENCODER_INTERNAL_LVDS_ENUM_ID1;
135*4882a593Smuzhiyun break;
136*4882a593Smuzhiyun case ATOM_DEVICE_DFP1_SUPPORT:
137*4882a593Smuzhiyun if ((rdev->family == CHIP_RS300) ||
138*4882a593Smuzhiyun (rdev->family == CHIP_RS400) ||
139*4882a593Smuzhiyun (rdev->family == CHIP_RS480))
140*4882a593Smuzhiyun ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
141*4882a593Smuzhiyun else if (ASIC_IS_AVIVO(rdev))
142*4882a593Smuzhiyun ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1;
143*4882a593Smuzhiyun else
144*4882a593Smuzhiyun ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1;
145*4882a593Smuzhiyun break;
146*4882a593Smuzhiyun case ATOM_DEVICE_LCD2_SUPPORT:
147*4882a593Smuzhiyun case ATOM_DEVICE_DFP2_SUPPORT:
148*4882a593Smuzhiyun if ((rdev->family == CHIP_RS600) ||
149*4882a593Smuzhiyun (rdev->family == CHIP_RS690) ||
150*4882a593Smuzhiyun (rdev->family == CHIP_RS740))
151*4882a593Smuzhiyun ret = ENCODER_INTERNAL_DDI_ENUM_ID1;
152*4882a593Smuzhiyun else if (ASIC_IS_AVIVO(rdev))
153*4882a593Smuzhiyun ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
154*4882a593Smuzhiyun else
155*4882a593Smuzhiyun ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
156*4882a593Smuzhiyun break;
157*4882a593Smuzhiyun case ATOM_DEVICE_DFP3_SUPPORT:
158*4882a593Smuzhiyun ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
159*4882a593Smuzhiyun break;
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun return ret;
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun
radeon_encoder_add_backlight(struct radeon_encoder * radeon_encoder,struct drm_connector * connector)165*4882a593Smuzhiyun static void radeon_encoder_add_backlight(struct radeon_encoder *radeon_encoder,
166*4882a593Smuzhiyun struct drm_connector *connector)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun struct drm_device *dev = radeon_encoder->base.dev;
169*4882a593Smuzhiyun struct radeon_device *rdev = dev->dev_private;
170*4882a593Smuzhiyun bool use_bl = false;
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun if (!(radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)))
173*4882a593Smuzhiyun return;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun if (radeon_backlight == 0) {
176*4882a593Smuzhiyun return;
177*4882a593Smuzhiyun } else if (radeon_backlight == 1) {
178*4882a593Smuzhiyun use_bl = true;
179*4882a593Smuzhiyun } else if (radeon_backlight == -1) {
180*4882a593Smuzhiyun /* Quirks */
181*4882a593Smuzhiyun /* Amilo Xi 2550 only works with acpi bl */
182*4882a593Smuzhiyun if ((rdev->pdev->device == 0x9583) &&
183*4882a593Smuzhiyun (rdev->pdev->subsystem_vendor == 0x1734) &&
184*4882a593Smuzhiyun (rdev->pdev->subsystem_device == 0x1107))
185*4882a593Smuzhiyun use_bl = false;
186*4882a593Smuzhiyun /* Older PPC macs use on-GPU backlight controller */
187*4882a593Smuzhiyun #ifndef CONFIG_PPC_PMAC
188*4882a593Smuzhiyun /* disable native backlight control on older asics */
189*4882a593Smuzhiyun else if (rdev->family < CHIP_R600)
190*4882a593Smuzhiyun use_bl = false;
191*4882a593Smuzhiyun #endif
192*4882a593Smuzhiyun else
193*4882a593Smuzhiyun use_bl = true;
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun if (use_bl) {
197*4882a593Smuzhiyun if (rdev->is_atom_bios)
198*4882a593Smuzhiyun radeon_atom_backlight_init(radeon_encoder, connector);
199*4882a593Smuzhiyun else
200*4882a593Smuzhiyun radeon_legacy_backlight_init(radeon_encoder, connector);
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun void
radeon_link_encoder_connector(struct drm_device * dev)205*4882a593Smuzhiyun radeon_link_encoder_connector(struct drm_device *dev)
206*4882a593Smuzhiyun {
207*4882a593Smuzhiyun struct drm_connector *connector;
208*4882a593Smuzhiyun struct radeon_connector *radeon_connector;
209*4882a593Smuzhiyun struct drm_encoder *encoder;
210*4882a593Smuzhiyun struct radeon_encoder *radeon_encoder;
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun /* walk the list and link encoders to connectors */
213*4882a593Smuzhiyun list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
214*4882a593Smuzhiyun radeon_connector = to_radeon_connector(connector);
215*4882a593Smuzhiyun list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
216*4882a593Smuzhiyun radeon_encoder = to_radeon_encoder(encoder);
217*4882a593Smuzhiyun if (radeon_encoder->devices & radeon_connector->devices) {
218*4882a593Smuzhiyun drm_connector_attach_encoder(connector, encoder);
219*4882a593Smuzhiyun if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
220*4882a593Smuzhiyun radeon_encoder_add_backlight(radeon_encoder, connector);
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun }
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun
radeon_encoder_set_active_device(struct drm_encoder * encoder)226*4882a593Smuzhiyun void radeon_encoder_set_active_device(struct drm_encoder *encoder)
227*4882a593Smuzhiyun {
228*4882a593Smuzhiyun struct drm_device *dev = encoder->dev;
229*4882a593Smuzhiyun struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
230*4882a593Smuzhiyun struct drm_connector *connector;
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
233*4882a593Smuzhiyun if (connector->encoder == encoder) {
234*4882a593Smuzhiyun struct radeon_connector *radeon_connector = to_radeon_connector(connector);
235*4882a593Smuzhiyun radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
236*4882a593Smuzhiyun DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
237*4882a593Smuzhiyun radeon_encoder->active_device, radeon_encoder->devices,
238*4882a593Smuzhiyun radeon_connector->devices, encoder->encoder_type);
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun }
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun struct drm_connector *
radeon_get_connector_for_encoder(struct drm_encoder * encoder)244*4882a593Smuzhiyun radeon_get_connector_for_encoder(struct drm_encoder *encoder)
245*4882a593Smuzhiyun {
246*4882a593Smuzhiyun struct drm_device *dev = encoder->dev;
247*4882a593Smuzhiyun struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
248*4882a593Smuzhiyun struct drm_connector *connector;
249*4882a593Smuzhiyun struct radeon_connector *radeon_connector;
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
252*4882a593Smuzhiyun radeon_connector = to_radeon_connector(connector);
253*4882a593Smuzhiyun if (radeon_encoder->is_mst_encoder) {
254*4882a593Smuzhiyun struct radeon_encoder_mst *mst_enc;
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun if (!radeon_connector->is_mst_connector)
257*4882a593Smuzhiyun continue;
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun mst_enc = radeon_encoder->enc_priv;
260*4882a593Smuzhiyun if (mst_enc->connector == radeon_connector->mst_port)
261*4882a593Smuzhiyun return connector;
262*4882a593Smuzhiyun } else if (radeon_encoder->active_device & radeon_connector->devices)
263*4882a593Smuzhiyun return connector;
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun return NULL;
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun struct drm_connector *
radeon_get_connector_for_encoder_init(struct drm_encoder * encoder)269*4882a593Smuzhiyun radeon_get_connector_for_encoder_init(struct drm_encoder *encoder)
270*4882a593Smuzhiyun {
271*4882a593Smuzhiyun struct drm_device *dev = encoder->dev;
272*4882a593Smuzhiyun struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
273*4882a593Smuzhiyun struct drm_connector *connector;
274*4882a593Smuzhiyun struct radeon_connector *radeon_connector;
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
277*4882a593Smuzhiyun radeon_connector = to_radeon_connector(connector);
278*4882a593Smuzhiyun if (radeon_encoder->devices & radeon_connector->devices)
279*4882a593Smuzhiyun return connector;
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun return NULL;
282*4882a593Smuzhiyun }
283*4882a593Smuzhiyun
radeon_get_external_encoder(struct drm_encoder * encoder)284*4882a593Smuzhiyun struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder)
285*4882a593Smuzhiyun {
286*4882a593Smuzhiyun struct drm_device *dev = encoder->dev;
287*4882a593Smuzhiyun struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
288*4882a593Smuzhiyun struct drm_encoder *other_encoder;
289*4882a593Smuzhiyun struct radeon_encoder *other_radeon_encoder;
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun if (radeon_encoder->is_ext_encoder)
292*4882a593Smuzhiyun return NULL;
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
295*4882a593Smuzhiyun if (other_encoder == encoder)
296*4882a593Smuzhiyun continue;
297*4882a593Smuzhiyun other_radeon_encoder = to_radeon_encoder(other_encoder);
298*4882a593Smuzhiyun if (other_radeon_encoder->is_ext_encoder &&
299*4882a593Smuzhiyun (radeon_encoder->devices & other_radeon_encoder->devices))
300*4882a593Smuzhiyun return other_encoder;
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun return NULL;
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun
radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder * encoder)305*4882a593Smuzhiyun u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder)
306*4882a593Smuzhiyun {
307*4882a593Smuzhiyun struct drm_encoder *other_encoder = radeon_get_external_encoder(encoder);
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun if (other_encoder) {
310*4882a593Smuzhiyun struct radeon_encoder *radeon_encoder = to_radeon_encoder(other_encoder);
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun switch (radeon_encoder->encoder_id) {
313*4882a593Smuzhiyun case ENCODER_OBJECT_ID_TRAVIS:
314*4882a593Smuzhiyun case ENCODER_OBJECT_ID_NUTMEG:
315*4882a593Smuzhiyun return radeon_encoder->encoder_id;
316*4882a593Smuzhiyun default:
317*4882a593Smuzhiyun return ENCODER_OBJECT_ID_NONE;
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun }
320*4882a593Smuzhiyun return ENCODER_OBJECT_ID_NONE;
321*4882a593Smuzhiyun }
322*4882a593Smuzhiyun
radeon_panel_mode_fixup(struct drm_encoder * encoder,struct drm_display_mode * adjusted_mode)323*4882a593Smuzhiyun void radeon_panel_mode_fixup(struct drm_encoder *encoder,
324*4882a593Smuzhiyun struct drm_display_mode *adjusted_mode)
325*4882a593Smuzhiyun {
326*4882a593Smuzhiyun struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
327*4882a593Smuzhiyun struct drm_device *dev = encoder->dev;
328*4882a593Smuzhiyun struct radeon_device *rdev = dev->dev_private;
329*4882a593Smuzhiyun struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
330*4882a593Smuzhiyun unsigned hblank = native_mode->htotal - native_mode->hdisplay;
331*4882a593Smuzhiyun unsigned vblank = native_mode->vtotal - native_mode->vdisplay;
332*4882a593Smuzhiyun unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
333*4882a593Smuzhiyun unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
334*4882a593Smuzhiyun unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
335*4882a593Smuzhiyun unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun adjusted_mode->clock = native_mode->clock;
338*4882a593Smuzhiyun adjusted_mode->flags = native_mode->flags;
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun if (ASIC_IS_AVIVO(rdev)) {
341*4882a593Smuzhiyun adjusted_mode->hdisplay = native_mode->hdisplay;
342*4882a593Smuzhiyun adjusted_mode->vdisplay = native_mode->vdisplay;
343*4882a593Smuzhiyun }
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun adjusted_mode->htotal = native_mode->hdisplay + hblank;
346*4882a593Smuzhiyun adjusted_mode->hsync_start = native_mode->hdisplay + hover;
347*4882a593Smuzhiyun adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun adjusted_mode->vtotal = native_mode->vdisplay + vblank;
350*4882a593Smuzhiyun adjusted_mode->vsync_start = native_mode->vdisplay + vover;
351*4882a593Smuzhiyun adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun if (ASIC_IS_AVIVO(rdev)) {
356*4882a593Smuzhiyun adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
357*4882a593Smuzhiyun adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
361*4882a593Smuzhiyun adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
362*4882a593Smuzhiyun adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
365*4882a593Smuzhiyun adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
366*4882a593Smuzhiyun adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun
radeon_dig_monitor_is_duallink(struct drm_encoder * encoder,u32 pixel_clock)370*4882a593Smuzhiyun bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
371*4882a593Smuzhiyun u32 pixel_clock)
372*4882a593Smuzhiyun {
373*4882a593Smuzhiyun struct drm_device *dev = encoder->dev;
374*4882a593Smuzhiyun struct radeon_device *rdev = dev->dev_private;
375*4882a593Smuzhiyun struct drm_connector *connector;
376*4882a593Smuzhiyun struct radeon_connector *radeon_connector;
377*4882a593Smuzhiyun struct radeon_connector_atom_dig *dig_connector;
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun connector = radeon_get_connector_for_encoder(encoder);
380*4882a593Smuzhiyun /* if we don't have an active device yet, just use one of
381*4882a593Smuzhiyun * the connectors tied to the encoder.
382*4882a593Smuzhiyun */
383*4882a593Smuzhiyun if (!connector)
384*4882a593Smuzhiyun connector = radeon_get_connector_for_encoder_init(encoder);
385*4882a593Smuzhiyun radeon_connector = to_radeon_connector(connector);
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun switch (connector->connector_type) {
388*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_DVII:
389*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_HDMIB:
390*4882a593Smuzhiyun if (radeon_connector->use_digital) {
391*4882a593Smuzhiyun /* HDMI 1.3 supports up to 340 Mhz over single link */
392*4882a593Smuzhiyun if (ASIC_IS_DCE6(rdev) && drm_detect_hdmi_monitor(radeon_connector_edid(connector))) {
393*4882a593Smuzhiyun if (pixel_clock > 340000)
394*4882a593Smuzhiyun return true;
395*4882a593Smuzhiyun else
396*4882a593Smuzhiyun return false;
397*4882a593Smuzhiyun } else {
398*4882a593Smuzhiyun if (pixel_clock > 165000)
399*4882a593Smuzhiyun return true;
400*4882a593Smuzhiyun else
401*4882a593Smuzhiyun return false;
402*4882a593Smuzhiyun }
403*4882a593Smuzhiyun } else
404*4882a593Smuzhiyun return false;
405*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_DVID:
406*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_HDMIA:
407*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_DisplayPort:
408*4882a593Smuzhiyun if (radeon_connector->is_mst_connector)
409*4882a593Smuzhiyun return false;
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun dig_connector = radeon_connector->con_priv;
412*4882a593Smuzhiyun if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
413*4882a593Smuzhiyun (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
414*4882a593Smuzhiyun return false;
415*4882a593Smuzhiyun else {
416*4882a593Smuzhiyun /* HDMI 1.3 supports up to 340 Mhz over single link */
417*4882a593Smuzhiyun if (ASIC_IS_DCE6(rdev) && drm_detect_hdmi_monitor(radeon_connector_edid(connector))) {
418*4882a593Smuzhiyun if (pixel_clock > 340000)
419*4882a593Smuzhiyun return true;
420*4882a593Smuzhiyun else
421*4882a593Smuzhiyun return false;
422*4882a593Smuzhiyun } else {
423*4882a593Smuzhiyun if (pixel_clock > 165000)
424*4882a593Smuzhiyun return true;
425*4882a593Smuzhiyun else
426*4882a593Smuzhiyun return false;
427*4882a593Smuzhiyun }
428*4882a593Smuzhiyun }
429*4882a593Smuzhiyun default:
430*4882a593Smuzhiyun return false;
431*4882a593Smuzhiyun }
432*4882a593Smuzhiyun }
433*4882a593Smuzhiyun
radeon_encoder_is_digital(struct drm_encoder * encoder)434*4882a593Smuzhiyun bool radeon_encoder_is_digital(struct drm_encoder *encoder)
435*4882a593Smuzhiyun {
436*4882a593Smuzhiyun struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
437*4882a593Smuzhiyun switch (radeon_encoder->encoder_id) {
438*4882a593Smuzhiyun case ENCODER_OBJECT_ID_INTERNAL_LVDS:
439*4882a593Smuzhiyun case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
440*4882a593Smuzhiyun case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
441*4882a593Smuzhiyun case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
442*4882a593Smuzhiyun case ENCODER_OBJECT_ID_INTERNAL_DVO1:
443*4882a593Smuzhiyun case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
444*4882a593Smuzhiyun case ENCODER_OBJECT_ID_INTERNAL_DDI:
445*4882a593Smuzhiyun case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
446*4882a593Smuzhiyun case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
447*4882a593Smuzhiyun case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
448*4882a593Smuzhiyun case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
449*4882a593Smuzhiyun case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
450*4882a593Smuzhiyun return true;
451*4882a593Smuzhiyun default:
452*4882a593Smuzhiyun return false;
453*4882a593Smuzhiyun }
454*4882a593Smuzhiyun }
455