1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2007-8 Advanced Micro Devices, Inc.
3*4882a593Smuzhiyun * Copyright 2008 Red Hat Inc.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a
6*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"),
7*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation
8*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the
10*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions:
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in
13*4882a593Smuzhiyun * all copies or substantial portions of the Software.
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE.
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * Authors: Dave Airlie
24*4882a593Smuzhiyun * Alex Deucher
25*4882a593Smuzhiyun */
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #include <drm/drm_edid.h>
28*4882a593Smuzhiyun #include <drm/drm_crtc_helper.h>
29*4882a593Smuzhiyun #include <drm/drm_fb_helper.h>
30*4882a593Smuzhiyun #include <drm/drm_dp_mst_helper.h>
31*4882a593Smuzhiyun #include <drm/drm_probe_helper.h>
32*4882a593Smuzhiyun #include <drm/radeon_drm.h>
33*4882a593Smuzhiyun #include "radeon.h"
34*4882a593Smuzhiyun #include "radeon_audio.h"
35*4882a593Smuzhiyun #include "atom.h"
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #include <linux/pm_runtime.h>
38*4882a593Smuzhiyun #include <linux/vga_switcheroo.h>
39*4882a593Smuzhiyun
radeon_dp_handle_hpd(struct drm_connector * connector)40*4882a593Smuzhiyun static int radeon_dp_handle_hpd(struct drm_connector *connector)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun struct radeon_connector *radeon_connector = to_radeon_connector(connector);
43*4882a593Smuzhiyun int ret;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun ret = radeon_dp_mst_check_status(radeon_connector);
46*4882a593Smuzhiyun if (ret == -EINVAL)
47*4882a593Smuzhiyun return 1;
48*4882a593Smuzhiyun return 0;
49*4882a593Smuzhiyun }
radeon_connector_hotplug(struct drm_connector * connector)50*4882a593Smuzhiyun void radeon_connector_hotplug(struct drm_connector *connector)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun struct drm_device *dev = connector->dev;
53*4882a593Smuzhiyun struct radeon_device *rdev = dev->dev_private;
54*4882a593Smuzhiyun struct radeon_connector *radeon_connector = to_radeon_connector(connector);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
57*4882a593Smuzhiyun struct radeon_connector_atom_dig *dig_connector =
58*4882a593Smuzhiyun radeon_connector->con_priv;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun if (radeon_connector->is_mst_connector)
61*4882a593Smuzhiyun return;
62*4882a593Smuzhiyun if (dig_connector->is_mst) {
63*4882a593Smuzhiyun radeon_dp_handle_hpd(connector);
64*4882a593Smuzhiyun return;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun /* bail if the connector does not have hpd pin, e.g.,
68*4882a593Smuzhiyun * VGA, TV, etc.
69*4882a593Smuzhiyun */
70*4882a593Smuzhiyun if (radeon_connector->hpd.hpd == RADEON_HPD_NONE)
71*4882a593Smuzhiyun return;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* if the connector is already off, don't turn it back on */
76*4882a593Smuzhiyun /* FIXME: This access isn't protected by any locks. */
77*4882a593Smuzhiyun if (connector->dpms != DRM_MODE_DPMS_ON)
78*4882a593Smuzhiyun return;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun /* just deal with DP (not eDP) here. */
81*4882a593Smuzhiyun if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
82*4882a593Smuzhiyun struct radeon_connector_atom_dig *dig_connector =
83*4882a593Smuzhiyun radeon_connector->con_priv;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /* if existing sink type was not DP no need to retrain */
86*4882a593Smuzhiyun if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT)
87*4882a593Smuzhiyun return;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /* first get sink type as it may be reset after (un)plug */
90*4882a593Smuzhiyun dig_connector->dp_sink_type = radeon_dp_getsinktype(radeon_connector);
91*4882a593Smuzhiyun /* don't do anything if sink is not display port, i.e.,
92*4882a593Smuzhiyun * passive dp->(dvi|hdmi) adaptor
93*4882a593Smuzhiyun */
94*4882a593Smuzhiyun if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
95*4882a593Smuzhiyun radeon_hpd_sense(rdev, radeon_connector->hpd.hpd) &&
96*4882a593Smuzhiyun radeon_dp_needs_link_train(radeon_connector)) {
97*4882a593Smuzhiyun /* Don't start link training before we have the DPCD */
98*4882a593Smuzhiyun if (!radeon_dp_getdpcd(radeon_connector))
99*4882a593Smuzhiyun return;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun /* Turn the connector off and back on immediately, which
102*4882a593Smuzhiyun * will trigger link training
103*4882a593Smuzhiyun */
104*4882a593Smuzhiyun drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
105*4882a593Smuzhiyun drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
radeon_property_change_mode(struct drm_encoder * encoder)110*4882a593Smuzhiyun static void radeon_property_change_mode(struct drm_encoder *encoder)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun struct drm_crtc *crtc = encoder->crtc;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun if (crtc && crtc->enabled) {
115*4882a593Smuzhiyun drm_crtc_helper_set_mode(crtc, &crtc->mode,
116*4882a593Smuzhiyun crtc->x, crtc->y, crtc->primary->fb);
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
radeon_get_monitor_bpc(struct drm_connector * connector)120*4882a593Smuzhiyun int radeon_get_monitor_bpc(struct drm_connector *connector)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun struct drm_device *dev = connector->dev;
123*4882a593Smuzhiyun struct radeon_device *rdev = dev->dev_private;
124*4882a593Smuzhiyun struct radeon_connector *radeon_connector = to_radeon_connector(connector);
125*4882a593Smuzhiyun struct radeon_connector_atom_dig *dig_connector;
126*4882a593Smuzhiyun int bpc = 8;
127*4882a593Smuzhiyun int mode_clock, max_tmds_clock;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun switch (connector->connector_type) {
130*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_DVII:
131*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_HDMIB:
132*4882a593Smuzhiyun if (radeon_connector->use_digital) {
133*4882a593Smuzhiyun if (drm_detect_hdmi_monitor(radeon_connector_edid(connector))) {
134*4882a593Smuzhiyun if (connector->display_info.bpc)
135*4882a593Smuzhiyun bpc = connector->display_info.bpc;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun break;
139*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_DVID:
140*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_HDMIA:
141*4882a593Smuzhiyun if (drm_detect_hdmi_monitor(radeon_connector_edid(connector))) {
142*4882a593Smuzhiyun if (connector->display_info.bpc)
143*4882a593Smuzhiyun bpc = connector->display_info.bpc;
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun break;
146*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_DisplayPort:
147*4882a593Smuzhiyun dig_connector = radeon_connector->con_priv;
148*4882a593Smuzhiyun if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
149*4882a593Smuzhiyun (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
150*4882a593Smuzhiyun drm_detect_hdmi_monitor(radeon_connector_edid(connector))) {
151*4882a593Smuzhiyun if (connector->display_info.bpc)
152*4882a593Smuzhiyun bpc = connector->display_info.bpc;
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun break;
155*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_eDP:
156*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_LVDS:
157*4882a593Smuzhiyun if (connector->display_info.bpc)
158*4882a593Smuzhiyun bpc = connector->display_info.bpc;
159*4882a593Smuzhiyun else if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
160*4882a593Smuzhiyun const struct drm_connector_helper_funcs *connector_funcs =
161*4882a593Smuzhiyun connector->helper_private;
162*4882a593Smuzhiyun struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
163*4882a593Smuzhiyun struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
164*4882a593Smuzhiyun struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR)
167*4882a593Smuzhiyun bpc = 6;
168*4882a593Smuzhiyun else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR)
169*4882a593Smuzhiyun bpc = 8;
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun break;
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun if (drm_detect_hdmi_monitor(radeon_connector_edid(connector))) {
175*4882a593Smuzhiyun /* hdmi deep color only implemented on DCE4+ */
176*4882a593Smuzhiyun if ((bpc > 8) && !ASIC_IS_DCE4(rdev)) {
177*4882a593Smuzhiyun DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 8 bpc.\n",
178*4882a593Smuzhiyun connector->name, bpc);
179*4882a593Smuzhiyun bpc = 8;
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun /*
183*4882a593Smuzhiyun * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make
184*4882a593Smuzhiyun * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at
185*4882a593Smuzhiyun * 12 bpc is always supported on hdmi deep color sinks, as this is
186*4882a593Smuzhiyun * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum.
187*4882a593Smuzhiyun */
188*4882a593Smuzhiyun if (bpc > 12) {
189*4882a593Smuzhiyun DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n",
190*4882a593Smuzhiyun connector->name, bpc);
191*4882a593Smuzhiyun bpc = 12;
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun /* Any defined maximum tmds clock limit we must not exceed? */
195*4882a593Smuzhiyun if (connector->display_info.max_tmds_clock > 0) {
196*4882a593Smuzhiyun /* mode_clock is clock in kHz for mode to be modeset on this connector */
197*4882a593Smuzhiyun mode_clock = radeon_connector->pixelclock_for_modeset;
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun /* Maximum allowable input clock in kHz */
200*4882a593Smuzhiyun max_tmds_clock = connector->display_info.max_tmds_clock;
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n",
203*4882a593Smuzhiyun connector->name, mode_clock, max_tmds_clock);
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */
206*4882a593Smuzhiyun if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
207*4882a593Smuzhiyun if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) &&
208*4882a593Smuzhiyun (mode_clock * 5/4 <= max_tmds_clock))
209*4882a593Smuzhiyun bpc = 10;
210*4882a593Smuzhiyun else
211*4882a593Smuzhiyun bpc = 8;
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n",
214*4882a593Smuzhiyun connector->name, bpc);
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
218*4882a593Smuzhiyun bpc = 8;
219*4882a593Smuzhiyun DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
220*4882a593Smuzhiyun connector->name, bpc);
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun }
223*4882a593Smuzhiyun else if (bpc > 8) {
224*4882a593Smuzhiyun /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
225*4882a593Smuzhiyun DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
226*4882a593Smuzhiyun connector->name);
227*4882a593Smuzhiyun bpc = 8;
228*4882a593Smuzhiyun }
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun if ((radeon_deep_color == 0) && (bpc > 8)) {
232*4882a593Smuzhiyun DRM_DEBUG("%s: Deep color disabled. Set radeon module param deep_color=1 to enable.\n",
233*4882a593Smuzhiyun connector->name);
234*4882a593Smuzhiyun bpc = 8;
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
238*4882a593Smuzhiyun connector->name, connector->display_info.bpc, bpc);
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun return bpc;
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun static void
radeon_connector_update_scratch_regs(struct drm_connector * connector,enum drm_connector_status status)244*4882a593Smuzhiyun radeon_connector_update_scratch_regs(struct drm_connector *connector, enum drm_connector_status status)
245*4882a593Smuzhiyun {
246*4882a593Smuzhiyun struct drm_device *dev = connector->dev;
247*4882a593Smuzhiyun struct radeon_device *rdev = dev->dev_private;
248*4882a593Smuzhiyun struct drm_encoder *best_encoder;
249*4882a593Smuzhiyun struct drm_encoder *encoder;
250*4882a593Smuzhiyun const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
251*4882a593Smuzhiyun bool connected;
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun best_encoder = connector_funcs->best_encoder(connector);
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun drm_connector_for_each_possible_encoder(connector, encoder) {
256*4882a593Smuzhiyun if ((encoder == best_encoder) && (status == connector_status_connected))
257*4882a593Smuzhiyun connected = true;
258*4882a593Smuzhiyun else
259*4882a593Smuzhiyun connected = false;
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun if (rdev->is_atom_bios)
262*4882a593Smuzhiyun radeon_atombios_connected_scratch_regs(connector, encoder, connected);
263*4882a593Smuzhiyun else
264*4882a593Smuzhiyun radeon_combios_connected_scratch_regs(connector, encoder, connected);
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun
radeon_find_encoder(struct drm_connector * connector,int encoder_type)268*4882a593Smuzhiyun static struct drm_encoder *radeon_find_encoder(struct drm_connector *connector, int encoder_type)
269*4882a593Smuzhiyun {
270*4882a593Smuzhiyun struct drm_encoder *encoder;
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun drm_connector_for_each_possible_encoder(connector, encoder) {
273*4882a593Smuzhiyun if (encoder->encoder_type == encoder_type)
274*4882a593Smuzhiyun return encoder;
275*4882a593Smuzhiyun }
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun return NULL;
278*4882a593Smuzhiyun }
279*4882a593Smuzhiyun
radeon_connector_edid(struct drm_connector * connector)280*4882a593Smuzhiyun struct edid *radeon_connector_edid(struct drm_connector *connector)
281*4882a593Smuzhiyun {
282*4882a593Smuzhiyun struct radeon_connector *radeon_connector = to_radeon_connector(connector);
283*4882a593Smuzhiyun struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun if (radeon_connector->edid) {
286*4882a593Smuzhiyun return radeon_connector->edid;
287*4882a593Smuzhiyun } else if (edid_blob) {
288*4882a593Smuzhiyun struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL);
289*4882a593Smuzhiyun if (edid)
290*4882a593Smuzhiyun radeon_connector->edid = edid;
291*4882a593Smuzhiyun }
292*4882a593Smuzhiyun return radeon_connector->edid;
293*4882a593Smuzhiyun }
294*4882a593Smuzhiyun
radeon_connector_get_edid(struct drm_connector * connector)295*4882a593Smuzhiyun static void radeon_connector_get_edid(struct drm_connector *connector)
296*4882a593Smuzhiyun {
297*4882a593Smuzhiyun struct drm_device *dev = connector->dev;
298*4882a593Smuzhiyun struct radeon_device *rdev = dev->dev_private;
299*4882a593Smuzhiyun struct radeon_connector *radeon_connector = to_radeon_connector(connector);
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun if (radeon_connector->edid)
302*4882a593Smuzhiyun return;
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun /* on hw with routers, select right port */
305*4882a593Smuzhiyun if (radeon_connector->router.ddc_valid)
306*4882a593Smuzhiyun radeon_router_select_ddc_port(radeon_connector);
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) !=
309*4882a593Smuzhiyun ENCODER_OBJECT_ID_NONE) &&
310*4882a593Smuzhiyun radeon_connector->ddc_bus->has_aux) {
311*4882a593Smuzhiyun radeon_connector->edid = drm_get_edid(connector,
312*4882a593Smuzhiyun &radeon_connector->ddc_bus->aux.ddc);
313*4882a593Smuzhiyun } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
314*4882a593Smuzhiyun (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
315*4882a593Smuzhiyun struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
318*4882a593Smuzhiyun dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
319*4882a593Smuzhiyun radeon_connector->ddc_bus->has_aux)
320*4882a593Smuzhiyun radeon_connector->edid = drm_get_edid(&radeon_connector->base,
321*4882a593Smuzhiyun &radeon_connector->ddc_bus->aux.ddc);
322*4882a593Smuzhiyun else if (radeon_connector->ddc_bus)
323*4882a593Smuzhiyun radeon_connector->edid = drm_get_edid(&radeon_connector->base,
324*4882a593Smuzhiyun &radeon_connector->ddc_bus->adapter);
325*4882a593Smuzhiyun } else if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC &&
326*4882a593Smuzhiyun connector->connector_type == DRM_MODE_CONNECTOR_LVDS &&
327*4882a593Smuzhiyun radeon_connector->ddc_bus) {
328*4882a593Smuzhiyun radeon_connector->edid = drm_get_edid_switcheroo(&radeon_connector->base,
329*4882a593Smuzhiyun &radeon_connector->ddc_bus->adapter);
330*4882a593Smuzhiyun } else if (radeon_connector->ddc_bus) {
331*4882a593Smuzhiyun radeon_connector->edid = drm_get_edid(&radeon_connector->base,
332*4882a593Smuzhiyun &radeon_connector->ddc_bus->adapter);
333*4882a593Smuzhiyun }
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun if (!radeon_connector->edid) {
336*4882a593Smuzhiyun /* don't fetch the edid from the vbios if ddc fails and runpm is
337*4882a593Smuzhiyun * enabled so we report disconnected.
338*4882a593Smuzhiyun */
339*4882a593Smuzhiyun if ((rdev->flags & RADEON_IS_PX) && (radeon_runtime_pm != 0))
340*4882a593Smuzhiyun return;
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun if (rdev->is_atom_bios) {
343*4882a593Smuzhiyun /* some laptops provide a hardcoded edid in rom for LCDs */
344*4882a593Smuzhiyun if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
345*4882a593Smuzhiyun (connector->connector_type == DRM_MODE_CONNECTOR_eDP)))
346*4882a593Smuzhiyun radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
347*4882a593Smuzhiyun } else {
348*4882a593Smuzhiyun /* some servers provide a hardcoded edid in rom for KVMs */
349*4882a593Smuzhiyun radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
350*4882a593Smuzhiyun }
351*4882a593Smuzhiyun }
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun
radeon_connector_free_edid(struct drm_connector * connector)354*4882a593Smuzhiyun static void radeon_connector_free_edid(struct drm_connector *connector)
355*4882a593Smuzhiyun {
356*4882a593Smuzhiyun struct radeon_connector *radeon_connector = to_radeon_connector(connector);
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun if (radeon_connector->edid) {
359*4882a593Smuzhiyun kfree(radeon_connector->edid);
360*4882a593Smuzhiyun radeon_connector->edid = NULL;
361*4882a593Smuzhiyun }
362*4882a593Smuzhiyun }
363*4882a593Smuzhiyun
radeon_ddc_get_modes(struct drm_connector * connector)364*4882a593Smuzhiyun static int radeon_ddc_get_modes(struct drm_connector *connector)
365*4882a593Smuzhiyun {
366*4882a593Smuzhiyun struct radeon_connector *radeon_connector = to_radeon_connector(connector);
367*4882a593Smuzhiyun int ret;
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun if (radeon_connector->edid) {
370*4882a593Smuzhiyun drm_connector_update_edid_property(connector, radeon_connector->edid);
371*4882a593Smuzhiyun ret = drm_add_edid_modes(connector, radeon_connector->edid);
372*4882a593Smuzhiyun return ret;
373*4882a593Smuzhiyun }
374*4882a593Smuzhiyun drm_connector_update_edid_property(connector, NULL);
375*4882a593Smuzhiyun return 0;
376*4882a593Smuzhiyun }
377*4882a593Smuzhiyun
radeon_best_single_encoder(struct drm_connector * connector)378*4882a593Smuzhiyun static struct drm_encoder *radeon_best_single_encoder(struct drm_connector *connector)
379*4882a593Smuzhiyun {
380*4882a593Smuzhiyun struct drm_encoder *encoder;
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun /* pick the first one */
383*4882a593Smuzhiyun drm_connector_for_each_possible_encoder(connector, encoder)
384*4882a593Smuzhiyun return encoder;
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun return NULL;
387*4882a593Smuzhiyun }
388*4882a593Smuzhiyun
radeon_get_native_mode(struct drm_connector * connector)389*4882a593Smuzhiyun static void radeon_get_native_mode(struct drm_connector *connector)
390*4882a593Smuzhiyun {
391*4882a593Smuzhiyun struct drm_encoder *encoder = radeon_best_single_encoder(connector);
392*4882a593Smuzhiyun struct radeon_encoder *radeon_encoder;
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun if (encoder == NULL)
395*4882a593Smuzhiyun return;
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun radeon_encoder = to_radeon_encoder(encoder);
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun if (!list_empty(&connector->probed_modes)) {
400*4882a593Smuzhiyun struct drm_display_mode *preferred_mode =
401*4882a593Smuzhiyun list_first_entry(&connector->probed_modes,
402*4882a593Smuzhiyun struct drm_display_mode, head);
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun radeon_encoder->native_mode = *preferred_mode;
405*4882a593Smuzhiyun } else {
406*4882a593Smuzhiyun radeon_encoder->native_mode.clock = 0;
407*4882a593Smuzhiyun }
408*4882a593Smuzhiyun }
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun /*
411*4882a593Smuzhiyun * radeon_connector_analog_encoder_conflict_solve
412*4882a593Smuzhiyun * - search for other connectors sharing this encoder
413*4882a593Smuzhiyun * if priority is true, then set them disconnected if this is connected
414*4882a593Smuzhiyun * if priority is false, set us disconnected if they are connected
415*4882a593Smuzhiyun */
416*4882a593Smuzhiyun static enum drm_connector_status
radeon_connector_analog_encoder_conflict_solve(struct drm_connector * connector,struct drm_encoder * encoder,enum drm_connector_status current_status,bool priority)417*4882a593Smuzhiyun radeon_connector_analog_encoder_conflict_solve(struct drm_connector *connector,
418*4882a593Smuzhiyun struct drm_encoder *encoder,
419*4882a593Smuzhiyun enum drm_connector_status current_status,
420*4882a593Smuzhiyun bool priority)
421*4882a593Smuzhiyun {
422*4882a593Smuzhiyun struct drm_device *dev = connector->dev;
423*4882a593Smuzhiyun struct drm_connector *conflict;
424*4882a593Smuzhiyun struct radeon_connector *radeon_conflict;
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun list_for_each_entry(conflict, &dev->mode_config.connector_list, head) {
427*4882a593Smuzhiyun struct drm_encoder *enc;
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun if (conflict == connector)
430*4882a593Smuzhiyun continue;
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun radeon_conflict = to_radeon_connector(conflict);
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun drm_connector_for_each_possible_encoder(conflict, enc) {
435*4882a593Smuzhiyun /* if the IDs match */
436*4882a593Smuzhiyun if (enc == encoder) {
437*4882a593Smuzhiyun if (conflict->status != connector_status_connected)
438*4882a593Smuzhiyun continue;
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun if (radeon_conflict->use_digital)
441*4882a593Smuzhiyun continue;
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun if (priority) {
444*4882a593Smuzhiyun DRM_DEBUG_KMS("1: conflicting encoders switching off %s\n",
445*4882a593Smuzhiyun conflict->name);
446*4882a593Smuzhiyun DRM_DEBUG_KMS("in favor of %s\n",
447*4882a593Smuzhiyun connector->name);
448*4882a593Smuzhiyun conflict->status = connector_status_disconnected;
449*4882a593Smuzhiyun radeon_connector_update_scratch_regs(conflict, connector_status_disconnected);
450*4882a593Smuzhiyun } else {
451*4882a593Smuzhiyun DRM_DEBUG_KMS("2: conflicting encoders switching off %s\n",
452*4882a593Smuzhiyun connector->name);
453*4882a593Smuzhiyun DRM_DEBUG_KMS("in favor of %s\n",
454*4882a593Smuzhiyun conflict->name);
455*4882a593Smuzhiyun current_status = connector_status_disconnected;
456*4882a593Smuzhiyun }
457*4882a593Smuzhiyun break;
458*4882a593Smuzhiyun }
459*4882a593Smuzhiyun }
460*4882a593Smuzhiyun }
461*4882a593Smuzhiyun return current_status;
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun }
464*4882a593Smuzhiyun
radeon_fp_native_mode(struct drm_encoder * encoder)465*4882a593Smuzhiyun static struct drm_display_mode *radeon_fp_native_mode(struct drm_encoder *encoder)
466*4882a593Smuzhiyun {
467*4882a593Smuzhiyun struct drm_device *dev = encoder->dev;
468*4882a593Smuzhiyun struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
469*4882a593Smuzhiyun struct drm_display_mode *mode = NULL;
470*4882a593Smuzhiyun struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun if (native_mode->hdisplay != 0 &&
473*4882a593Smuzhiyun native_mode->vdisplay != 0 &&
474*4882a593Smuzhiyun native_mode->clock != 0) {
475*4882a593Smuzhiyun mode = drm_mode_duplicate(dev, native_mode);
476*4882a593Smuzhiyun if (!mode)
477*4882a593Smuzhiyun return NULL;
478*4882a593Smuzhiyun mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
479*4882a593Smuzhiyun drm_mode_set_name(mode);
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
482*4882a593Smuzhiyun } else if (native_mode->hdisplay != 0 &&
483*4882a593Smuzhiyun native_mode->vdisplay != 0) {
484*4882a593Smuzhiyun /* mac laptops without an edid */
485*4882a593Smuzhiyun /* Note that this is not necessarily the exact panel mode,
486*4882a593Smuzhiyun * but an approximation based on the cvt formula. For these
487*4882a593Smuzhiyun * systems we should ideally read the mode info out of the
488*4882a593Smuzhiyun * registers or add a mode table, but this works and is much
489*4882a593Smuzhiyun * simpler.
490*4882a593Smuzhiyun */
491*4882a593Smuzhiyun mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
492*4882a593Smuzhiyun if (!mode)
493*4882a593Smuzhiyun return NULL;
494*4882a593Smuzhiyun mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
495*4882a593Smuzhiyun DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
496*4882a593Smuzhiyun }
497*4882a593Smuzhiyun return mode;
498*4882a593Smuzhiyun }
499*4882a593Smuzhiyun
radeon_add_common_modes(struct drm_encoder * encoder,struct drm_connector * connector)500*4882a593Smuzhiyun static void radeon_add_common_modes(struct drm_encoder *encoder, struct drm_connector *connector)
501*4882a593Smuzhiyun {
502*4882a593Smuzhiyun struct drm_device *dev = encoder->dev;
503*4882a593Smuzhiyun struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
504*4882a593Smuzhiyun struct drm_display_mode *mode = NULL;
505*4882a593Smuzhiyun struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
506*4882a593Smuzhiyun int i;
507*4882a593Smuzhiyun struct mode_size {
508*4882a593Smuzhiyun int w;
509*4882a593Smuzhiyun int h;
510*4882a593Smuzhiyun } common_modes[17] = {
511*4882a593Smuzhiyun { 640, 480},
512*4882a593Smuzhiyun { 720, 480},
513*4882a593Smuzhiyun { 800, 600},
514*4882a593Smuzhiyun { 848, 480},
515*4882a593Smuzhiyun {1024, 768},
516*4882a593Smuzhiyun {1152, 768},
517*4882a593Smuzhiyun {1280, 720},
518*4882a593Smuzhiyun {1280, 800},
519*4882a593Smuzhiyun {1280, 854},
520*4882a593Smuzhiyun {1280, 960},
521*4882a593Smuzhiyun {1280, 1024},
522*4882a593Smuzhiyun {1440, 900},
523*4882a593Smuzhiyun {1400, 1050},
524*4882a593Smuzhiyun {1680, 1050},
525*4882a593Smuzhiyun {1600, 1200},
526*4882a593Smuzhiyun {1920, 1080},
527*4882a593Smuzhiyun {1920, 1200}
528*4882a593Smuzhiyun };
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun for (i = 0; i < 17; i++) {
531*4882a593Smuzhiyun if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
532*4882a593Smuzhiyun if (common_modes[i].w > 1024 ||
533*4882a593Smuzhiyun common_modes[i].h > 768)
534*4882a593Smuzhiyun continue;
535*4882a593Smuzhiyun }
536*4882a593Smuzhiyun if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
537*4882a593Smuzhiyun if (common_modes[i].w > native_mode->hdisplay ||
538*4882a593Smuzhiyun common_modes[i].h > native_mode->vdisplay ||
539*4882a593Smuzhiyun (common_modes[i].w == native_mode->hdisplay &&
540*4882a593Smuzhiyun common_modes[i].h == native_mode->vdisplay))
541*4882a593Smuzhiyun continue;
542*4882a593Smuzhiyun }
543*4882a593Smuzhiyun if (common_modes[i].w < 320 || common_modes[i].h < 200)
544*4882a593Smuzhiyun continue;
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
547*4882a593Smuzhiyun drm_mode_probed_add(connector, mode);
548*4882a593Smuzhiyun }
549*4882a593Smuzhiyun }
550*4882a593Smuzhiyun
radeon_connector_set_property(struct drm_connector * connector,struct drm_property * property,uint64_t val)551*4882a593Smuzhiyun static int radeon_connector_set_property(struct drm_connector *connector, struct drm_property *property,
552*4882a593Smuzhiyun uint64_t val)
553*4882a593Smuzhiyun {
554*4882a593Smuzhiyun struct drm_device *dev = connector->dev;
555*4882a593Smuzhiyun struct radeon_device *rdev = dev->dev_private;
556*4882a593Smuzhiyun struct drm_encoder *encoder;
557*4882a593Smuzhiyun struct radeon_encoder *radeon_encoder;
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun if (property == rdev->mode_info.coherent_mode_property) {
560*4882a593Smuzhiyun struct radeon_encoder_atom_dig *dig;
561*4882a593Smuzhiyun bool new_coherent_mode;
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun /* need to find digital encoder on connector */
564*4882a593Smuzhiyun encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
565*4882a593Smuzhiyun if (!encoder)
566*4882a593Smuzhiyun return 0;
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun radeon_encoder = to_radeon_encoder(encoder);
569*4882a593Smuzhiyun
570*4882a593Smuzhiyun if (!radeon_encoder->enc_priv)
571*4882a593Smuzhiyun return 0;
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun dig = radeon_encoder->enc_priv;
574*4882a593Smuzhiyun new_coherent_mode = val ? true : false;
575*4882a593Smuzhiyun if (dig->coherent_mode != new_coherent_mode) {
576*4882a593Smuzhiyun dig->coherent_mode = new_coherent_mode;
577*4882a593Smuzhiyun radeon_property_change_mode(&radeon_encoder->base);
578*4882a593Smuzhiyun }
579*4882a593Smuzhiyun }
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun if (property == rdev->mode_info.audio_property) {
582*4882a593Smuzhiyun struct radeon_connector *radeon_connector = to_radeon_connector(connector);
583*4882a593Smuzhiyun /* need to find digital encoder on connector */
584*4882a593Smuzhiyun encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
585*4882a593Smuzhiyun if (!encoder)
586*4882a593Smuzhiyun return 0;
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun radeon_encoder = to_radeon_encoder(encoder);
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun if (radeon_connector->audio != val) {
591*4882a593Smuzhiyun radeon_connector->audio = val;
592*4882a593Smuzhiyun radeon_property_change_mode(&radeon_encoder->base);
593*4882a593Smuzhiyun }
594*4882a593Smuzhiyun }
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun if (property == rdev->mode_info.dither_property) {
597*4882a593Smuzhiyun struct radeon_connector *radeon_connector = to_radeon_connector(connector);
598*4882a593Smuzhiyun /* need to find digital encoder on connector */
599*4882a593Smuzhiyun encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
600*4882a593Smuzhiyun if (!encoder)
601*4882a593Smuzhiyun return 0;
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun radeon_encoder = to_radeon_encoder(encoder);
604*4882a593Smuzhiyun
605*4882a593Smuzhiyun if (radeon_connector->dither != val) {
606*4882a593Smuzhiyun radeon_connector->dither = val;
607*4882a593Smuzhiyun radeon_property_change_mode(&radeon_encoder->base);
608*4882a593Smuzhiyun }
609*4882a593Smuzhiyun }
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun if (property == rdev->mode_info.underscan_property) {
612*4882a593Smuzhiyun /* need to find digital encoder on connector */
613*4882a593Smuzhiyun encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
614*4882a593Smuzhiyun if (!encoder)
615*4882a593Smuzhiyun return 0;
616*4882a593Smuzhiyun
617*4882a593Smuzhiyun radeon_encoder = to_radeon_encoder(encoder);
618*4882a593Smuzhiyun
619*4882a593Smuzhiyun if (radeon_encoder->underscan_type != val) {
620*4882a593Smuzhiyun radeon_encoder->underscan_type = val;
621*4882a593Smuzhiyun radeon_property_change_mode(&radeon_encoder->base);
622*4882a593Smuzhiyun }
623*4882a593Smuzhiyun }
624*4882a593Smuzhiyun
625*4882a593Smuzhiyun if (property == rdev->mode_info.underscan_hborder_property) {
626*4882a593Smuzhiyun /* need to find digital encoder on connector */
627*4882a593Smuzhiyun encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
628*4882a593Smuzhiyun if (!encoder)
629*4882a593Smuzhiyun return 0;
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun radeon_encoder = to_radeon_encoder(encoder);
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun if (radeon_encoder->underscan_hborder != val) {
634*4882a593Smuzhiyun radeon_encoder->underscan_hborder = val;
635*4882a593Smuzhiyun radeon_property_change_mode(&radeon_encoder->base);
636*4882a593Smuzhiyun }
637*4882a593Smuzhiyun }
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun if (property == rdev->mode_info.underscan_vborder_property) {
640*4882a593Smuzhiyun /* need to find digital encoder on connector */
641*4882a593Smuzhiyun encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
642*4882a593Smuzhiyun if (!encoder)
643*4882a593Smuzhiyun return 0;
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun radeon_encoder = to_radeon_encoder(encoder);
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun if (radeon_encoder->underscan_vborder != val) {
648*4882a593Smuzhiyun radeon_encoder->underscan_vborder = val;
649*4882a593Smuzhiyun radeon_property_change_mode(&radeon_encoder->base);
650*4882a593Smuzhiyun }
651*4882a593Smuzhiyun }
652*4882a593Smuzhiyun
653*4882a593Smuzhiyun if (property == rdev->mode_info.tv_std_property) {
654*4882a593Smuzhiyun encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TVDAC);
655*4882a593Smuzhiyun if (!encoder) {
656*4882a593Smuzhiyun encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_DAC);
657*4882a593Smuzhiyun }
658*4882a593Smuzhiyun
659*4882a593Smuzhiyun if (!encoder)
660*4882a593Smuzhiyun return 0;
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun radeon_encoder = to_radeon_encoder(encoder);
663*4882a593Smuzhiyun if (!radeon_encoder->enc_priv)
664*4882a593Smuzhiyun return 0;
665*4882a593Smuzhiyun if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) {
666*4882a593Smuzhiyun struct radeon_encoder_atom_dac *dac_int;
667*4882a593Smuzhiyun dac_int = radeon_encoder->enc_priv;
668*4882a593Smuzhiyun dac_int->tv_std = val;
669*4882a593Smuzhiyun } else {
670*4882a593Smuzhiyun struct radeon_encoder_tv_dac *dac_int;
671*4882a593Smuzhiyun dac_int = radeon_encoder->enc_priv;
672*4882a593Smuzhiyun dac_int->tv_std = val;
673*4882a593Smuzhiyun }
674*4882a593Smuzhiyun radeon_property_change_mode(&radeon_encoder->base);
675*4882a593Smuzhiyun }
676*4882a593Smuzhiyun
677*4882a593Smuzhiyun if (property == rdev->mode_info.load_detect_property) {
678*4882a593Smuzhiyun struct radeon_connector *radeon_connector =
679*4882a593Smuzhiyun to_radeon_connector(connector);
680*4882a593Smuzhiyun
681*4882a593Smuzhiyun if (val == 0)
682*4882a593Smuzhiyun radeon_connector->dac_load_detect = false;
683*4882a593Smuzhiyun else
684*4882a593Smuzhiyun radeon_connector->dac_load_detect = true;
685*4882a593Smuzhiyun }
686*4882a593Smuzhiyun
687*4882a593Smuzhiyun if (property == rdev->mode_info.tmds_pll_property) {
688*4882a593Smuzhiyun struct radeon_encoder_int_tmds *tmds = NULL;
689*4882a593Smuzhiyun bool ret = false;
690*4882a593Smuzhiyun /* need to find digital encoder on connector */
691*4882a593Smuzhiyun encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
692*4882a593Smuzhiyun if (!encoder)
693*4882a593Smuzhiyun return 0;
694*4882a593Smuzhiyun
695*4882a593Smuzhiyun radeon_encoder = to_radeon_encoder(encoder);
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun tmds = radeon_encoder->enc_priv;
698*4882a593Smuzhiyun if (!tmds)
699*4882a593Smuzhiyun return 0;
700*4882a593Smuzhiyun
701*4882a593Smuzhiyun if (val == 0) {
702*4882a593Smuzhiyun if (rdev->is_atom_bios)
703*4882a593Smuzhiyun ret = radeon_atombios_get_tmds_info(radeon_encoder, tmds);
704*4882a593Smuzhiyun else
705*4882a593Smuzhiyun ret = radeon_legacy_get_tmds_info_from_combios(radeon_encoder, tmds);
706*4882a593Smuzhiyun }
707*4882a593Smuzhiyun if (val == 1 || !ret)
708*4882a593Smuzhiyun radeon_legacy_get_tmds_info_from_table(radeon_encoder, tmds);
709*4882a593Smuzhiyun
710*4882a593Smuzhiyun radeon_property_change_mode(&radeon_encoder->base);
711*4882a593Smuzhiyun }
712*4882a593Smuzhiyun
713*4882a593Smuzhiyun if (property == dev->mode_config.scaling_mode_property) {
714*4882a593Smuzhiyun enum radeon_rmx_type rmx_type;
715*4882a593Smuzhiyun
716*4882a593Smuzhiyun if (connector->encoder)
717*4882a593Smuzhiyun radeon_encoder = to_radeon_encoder(connector->encoder);
718*4882a593Smuzhiyun else {
719*4882a593Smuzhiyun const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
720*4882a593Smuzhiyun radeon_encoder = to_radeon_encoder(connector_funcs->best_encoder(connector));
721*4882a593Smuzhiyun }
722*4882a593Smuzhiyun
723*4882a593Smuzhiyun switch (val) {
724*4882a593Smuzhiyun default:
725*4882a593Smuzhiyun case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
726*4882a593Smuzhiyun case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
727*4882a593Smuzhiyun case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
728*4882a593Smuzhiyun case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
729*4882a593Smuzhiyun }
730*4882a593Smuzhiyun if (radeon_encoder->rmx_type == rmx_type)
731*4882a593Smuzhiyun return 0;
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun if ((rmx_type != DRM_MODE_SCALE_NONE) &&
734*4882a593Smuzhiyun (radeon_encoder->native_mode.clock == 0))
735*4882a593Smuzhiyun return 0;
736*4882a593Smuzhiyun
737*4882a593Smuzhiyun radeon_encoder->rmx_type = rmx_type;
738*4882a593Smuzhiyun
739*4882a593Smuzhiyun radeon_property_change_mode(&radeon_encoder->base);
740*4882a593Smuzhiyun }
741*4882a593Smuzhiyun
742*4882a593Smuzhiyun if (property == rdev->mode_info.output_csc_property) {
743*4882a593Smuzhiyun if (connector->encoder)
744*4882a593Smuzhiyun radeon_encoder = to_radeon_encoder(connector->encoder);
745*4882a593Smuzhiyun else {
746*4882a593Smuzhiyun const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
747*4882a593Smuzhiyun radeon_encoder = to_radeon_encoder(connector_funcs->best_encoder(connector));
748*4882a593Smuzhiyun }
749*4882a593Smuzhiyun
750*4882a593Smuzhiyun if (radeon_encoder->output_csc == val)
751*4882a593Smuzhiyun return 0;
752*4882a593Smuzhiyun
753*4882a593Smuzhiyun radeon_encoder->output_csc = val;
754*4882a593Smuzhiyun
755*4882a593Smuzhiyun if (connector->encoder && connector->encoder->crtc) {
756*4882a593Smuzhiyun struct drm_crtc *crtc = connector->encoder->crtc;
757*4882a593Smuzhiyun struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
758*4882a593Smuzhiyun
759*4882a593Smuzhiyun radeon_crtc->output_csc = radeon_encoder->output_csc;
760*4882a593Smuzhiyun
761*4882a593Smuzhiyun /*
762*4882a593Smuzhiyun * Our .gamma_set assumes the .gamma_store has been
763*4882a593Smuzhiyun * prefilled and don't care about its arguments.
764*4882a593Smuzhiyun */
765*4882a593Smuzhiyun crtc->funcs->gamma_set(crtc, NULL, NULL, NULL, 0, NULL);
766*4882a593Smuzhiyun }
767*4882a593Smuzhiyun }
768*4882a593Smuzhiyun
769*4882a593Smuzhiyun return 0;
770*4882a593Smuzhiyun }
771*4882a593Smuzhiyun
radeon_fixup_lvds_native_mode(struct drm_encoder * encoder,struct drm_connector * connector)772*4882a593Smuzhiyun static void radeon_fixup_lvds_native_mode(struct drm_encoder *encoder,
773*4882a593Smuzhiyun struct drm_connector *connector)
774*4882a593Smuzhiyun {
775*4882a593Smuzhiyun struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
776*4882a593Smuzhiyun struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
777*4882a593Smuzhiyun struct drm_display_mode *t, *mode;
778*4882a593Smuzhiyun
779*4882a593Smuzhiyun /* If the EDID preferred mode doesn't match the native mode, use it */
780*4882a593Smuzhiyun list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
781*4882a593Smuzhiyun if (mode->type & DRM_MODE_TYPE_PREFERRED) {
782*4882a593Smuzhiyun if (mode->hdisplay != native_mode->hdisplay ||
783*4882a593Smuzhiyun mode->vdisplay != native_mode->vdisplay)
784*4882a593Smuzhiyun memcpy(native_mode, mode, sizeof(*mode));
785*4882a593Smuzhiyun }
786*4882a593Smuzhiyun }
787*4882a593Smuzhiyun
788*4882a593Smuzhiyun /* Try to get native mode details from EDID if necessary */
789*4882a593Smuzhiyun if (!native_mode->clock) {
790*4882a593Smuzhiyun list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
791*4882a593Smuzhiyun if (mode->hdisplay == native_mode->hdisplay &&
792*4882a593Smuzhiyun mode->vdisplay == native_mode->vdisplay) {
793*4882a593Smuzhiyun *native_mode = *mode;
794*4882a593Smuzhiyun drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
795*4882a593Smuzhiyun DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
796*4882a593Smuzhiyun break;
797*4882a593Smuzhiyun }
798*4882a593Smuzhiyun }
799*4882a593Smuzhiyun }
800*4882a593Smuzhiyun
801*4882a593Smuzhiyun if (!native_mode->clock) {
802*4882a593Smuzhiyun DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
803*4882a593Smuzhiyun radeon_encoder->rmx_type = RMX_OFF;
804*4882a593Smuzhiyun }
805*4882a593Smuzhiyun }
806*4882a593Smuzhiyun
radeon_lvds_get_modes(struct drm_connector * connector)807*4882a593Smuzhiyun static int radeon_lvds_get_modes(struct drm_connector *connector)
808*4882a593Smuzhiyun {
809*4882a593Smuzhiyun struct drm_encoder *encoder;
810*4882a593Smuzhiyun int ret = 0;
811*4882a593Smuzhiyun struct drm_display_mode *mode;
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun radeon_connector_get_edid(connector);
814*4882a593Smuzhiyun ret = radeon_ddc_get_modes(connector);
815*4882a593Smuzhiyun if (ret > 0) {
816*4882a593Smuzhiyun encoder = radeon_best_single_encoder(connector);
817*4882a593Smuzhiyun if (encoder) {
818*4882a593Smuzhiyun radeon_fixup_lvds_native_mode(encoder, connector);
819*4882a593Smuzhiyun /* add scaled modes */
820*4882a593Smuzhiyun radeon_add_common_modes(encoder, connector);
821*4882a593Smuzhiyun }
822*4882a593Smuzhiyun return ret;
823*4882a593Smuzhiyun }
824*4882a593Smuzhiyun
825*4882a593Smuzhiyun encoder = radeon_best_single_encoder(connector);
826*4882a593Smuzhiyun if (!encoder)
827*4882a593Smuzhiyun return 0;
828*4882a593Smuzhiyun
829*4882a593Smuzhiyun /* we have no EDID modes */
830*4882a593Smuzhiyun mode = radeon_fp_native_mode(encoder);
831*4882a593Smuzhiyun if (mode) {
832*4882a593Smuzhiyun ret = 1;
833*4882a593Smuzhiyun drm_mode_probed_add(connector, mode);
834*4882a593Smuzhiyun /* add the width/height from vbios tables if available */
835*4882a593Smuzhiyun connector->display_info.width_mm = mode->width_mm;
836*4882a593Smuzhiyun connector->display_info.height_mm = mode->height_mm;
837*4882a593Smuzhiyun /* add scaled modes */
838*4882a593Smuzhiyun radeon_add_common_modes(encoder, connector);
839*4882a593Smuzhiyun }
840*4882a593Smuzhiyun
841*4882a593Smuzhiyun return ret;
842*4882a593Smuzhiyun }
843*4882a593Smuzhiyun
radeon_lvds_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)844*4882a593Smuzhiyun static enum drm_mode_status radeon_lvds_mode_valid(struct drm_connector *connector,
845*4882a593Smuzhiyun struct drm_display_mode *mode)
846*4882a593Smuzhiyun {
847*4882a593Smuzhiyun struct drm_encoder *encoder = radeon_best_single_encoder(connector);
848*4882a593Smuzhiyun
849*4882a593Smuzhiyun if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
850*4882a593Smuzhiyun return MODE_PANEL;
851*4882a593Smuzhiyun
852*4882a593Smuzhiyun if (encoder) {
853*4882a593Smuzhiyun struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
854*4882a593Smuzhiyun struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
855*4882a593Smuzhiyun
856*4882a593Smuzhiyun /* AVIVO hardware supports downscaling modes larger than the panel
857*4882a593Smuzhiyun * to the panel size, but I'm not sure this is desirable.
858*4882a593Smuzhiyun */
859*4882a593Smuzhiyun if ((mode->hdisplay > native_mode->hdisplay) ||
860*4882a593Smuzhiyun (mode->vdisplay > native_mode->vdisplay))
861*4882a593Smuzhiyun return MODE_PANEL;
862*4882a593Smuzhiyun
863*4882a593Smuzhiyun /* if scaling is disabled, block non-native modes */
864*4882a593Smuzhiyun if (radeon_encoder->rmx_type == RMX_OFF) {
865*4882a593Smuzhiyun if ((mode->hdisplay != native_mode->hdisplay) ||
866*4882a593Smuzhiyun (mode->vdisplay != native_mode->vdisplay))
867*4882a593Smuzhiyun return MODE_PANEL;
868*4882a593Smuzhiyun }
869*4882a593Smuzhiyun }
870*4882a593Smuzhiyun
871*4882a593Smuzhiyun return MODE_OK;
872*4882a593Smuzhiyun }
873*4882a593Smuzhiyun
874*4882a593Smuzhiyun static enum drm_connector_status
radeon_lvds_detect(struct drm_connector * connector,bool force)875*4882a593Smuzhiyun radeon_lvds_detect(struct drm_connector *connector, bool force)
876*4882a593Smuzhiyun {
877*4882a593Smuzhiyun struct drm_device *dev = connector->dev;
878*4882a593Smuzhiyun struct radeon_device *rdev = dev->dev_private;
879*4882a593Smuzhiyun struct radeon_connector *radeon_connector = to_radeon_connector(connector);
880*4882a593Smuzhiyun struct drm_encoder *encoder = radeon_best_single_encoder(connector);
881*4882a593Smuzhiyun enum drm_connector_status ret = connector_status_disconnected;
882*4882a593Smuzhiyun int r;
883*4882a593Smuzhiyun
884*4882a593Smuzhiyun if (!drm_kms_helper_is_poll_worker()) {
885*4882a593Smuzhiyun r = pm_runtime_get_sync(connector->dev->dev);
886*4882a593Smuzhiyun if (r < 0) {
887*4882a593Smuzhiyun pm_runtime_put_autosuspend(connector->dev->dev);
888*4882a593Smuzhiyun return connector_status_disconnected;
889*4882a593Smuzhiyun }
890*4882a593Smuzhiyun }
891*4882a593Smuzhiyun
892*4882a593Smuzhiyun if (encoder) {
893*4882a593Smuzhiyun struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
894*4882a593Smuzhiyun struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
895*4882a593Smuzhiyun
896*4882a593Smuzhiyun /* check if panel is valid */
897*4882a593Smuzhiyun if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
898*4882a593Smuzhiyun ret = connector_status_connected;
899*4882a593Smuzhiyun /* don't fetch the edid from the vbios if ddc fails and runpm is
900*4882a593Smuzhiyun * enabled so we report disconnected.
901*4882a593Smuzhiyun */
902*4882a593Smuzhiyun if ((rdev->flags & RADEON_IS_PX) && (radeon_runtime_pm != 0))
903*4882a593Smuzhiyun ret = connector_status_disconnected;
904*4882a593Smuzhiyun }
905*4882a593Smuzhiyun
906*4882a593Smuzhiyun /* check for edid as well */
907*4882a593Smuzhiyun radeon_connector_get_edid(connector);
908*4882a593Smuzhiyun if (radeon_connector->edid)
909*4882a593Smuzhiyun ret = connector_status_connected;
910*4882a593Smuzhiyun /* check acpi lid status ??? */
911*4882a593Smuzhiyun
912*4882a593Smuzhiyun radeon_connector_update_scratch_regs(connector, ret);
913*4882a593Smuzhiyun
914*4882a593Smuzhiyun if (!drm_kms_helper_is_poll_worker()) {
915*4882a593Smuzhiyun pm_runtime_mark_last_busy(connector->dev->dev);
916*4882a593Smuzhiyun pm_runtime_put_autosuspend(connector->dev->dev);
917*4882a593Smuzhiyun }
918*4882a593Smuzhiyun
919*4882a593Smuzhiyun return ret;
920*4882a593Smuzhiyun }
921*4882a593Smuzhiyun
radeon_connector_unregister(struct drm_connector * connector)922*4882a593Smuzhiyun static void radeon_connector_unregister(struct drm_connector *connector)
923*4882a593Smuzhiyun {
924*4882a593Smuzhiyun struct radeon_connector *radeon_connector = to_radeon_connector(connector);
925*4882a593Smuzhiyun
926*4882a593Smuzhiyun if (radeon_connector->ddc_bus && radeon_connector->ddc_bus->has_aux) {
927*4882a593Smuzhiyun drm_dp_aux_unregister(&radeon_connector->ddc_bus->aux);
928*4882a593Smuzhiyun radeon_connector->ddc_bus->has_aux = false;
929*4882a593Smuzhiyun }
930*4882a593Smuzhiyun }
931*4882a593Smuzhiyun
radeon_connector_destroy(struct drm_connector * connector)932*4882a593Smuzhiyun static void radeon_connector_destroy(struct drm_connector *connector)
933*4882a593Smuzhiyun {
934*4882a593Smuzhiyun struct radeon_connector *radeon_connector = to_radeon_connector(connector);
935*4882a593Smuzhiyun
936*4882a593Smuzhiyun radeon_connector_free_edid(connector);
937*4882a593Smuzhiyun kfree(radeon_connector->con_priv);
938*4882a593Smuzhiyun drm_connector_unregister(connector);
939*4882a593Smuzhiyun drm_connector_cleanup(connector);
940*4882a593Smuzhiyun kfree(connector);
941*4882a593Smuzhiyun }
942*4882a593Smuzhiyun
radeon_lvds_set_property(struct drm_connector * connector,struct drm_property * property,uint64_t value)943*4882a593Smuzhiyun static int radeon_lvds_set_property(struct drm_connector *connector,
944*4882a593Smuzhiyun struct drm_property *property,
945*4882a593Smuzhiyun uint64_t value)
946*4882a593Smuzhiyun {
947*4882a593Smuzhiyun struct drm_device *dev = connector->dev;
948*4882a593Smuzhiyun struct radeon_encoder *radeon_encoder;
949*4882a593Smuzhiyun enum radeon_rmx_type rmx_type;
950*4882a593Smuzhiyun
951*4882a593Smuzhiyun DRM_DEBUG_KMS("\n");
952*4882a593Smuzhiyun if (property != dev->mode_config.scaling_mode_property)
953*4882a593Smuzhiyun return 0;
954*4882a593Smuzhiyun
955*4882a593Smuzhiyun if (connector->encoder)
956*4882a593Smuzhiyun radeon_encoder = to_radeon_encoder(connector->encoder);
957*4882a593Smuzhiyun else {
958*4882a593Smuzhiyun const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
959*4882a593Smuzhiyun radeon_encoder = to_radeon_encoder(connector_funcs->best_encoder(connector));
960*4882a593Smuzhiyun }
961*4882a593Smuzhiyun
962*4882a593Smuzhiyun switch (value) {
963*4882a593Smuzhiyun case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
964*4882a593Smuzhiyun case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
965*4882a593Smuzhiyun case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
966*4882a593Smuzhiyun default:
967*4882a593Smuzhiyun case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
968*4882a593Smuzhiyun }
969*4882a593Smuzhiyun if (radeon_encoder->rmx_type == rmx_type)
970*4882a593Smuzhiyun return 0;
971*4882a593Smuzhiyun
972*4882a593Smuzhiyun radeon_encoder->rmx_type = rmx_type;
973*4882a593Smuzhiyun
974*4882a593Smuzhiyun radeon_property_change_mode(&radeon_encoder->base);
975*4882a593Smuzhiyun return 0;
976*4882a593Smuzhiyun }
977*4882a593Smuzhiyun
978*4882a593Smuzhiyun
979*4882a593Smuzhiyun static const struct drm_connector_helper_funcs radeon_lvds_connector_helper_funcs = {
980*4882a593Smuzhiyun .get_modes = radeon_lvds_get_modes,
981*4882a593Smuzhiyun .mode_valid = radeon_lvds_mode_valid,
982*4882a593Smuzhiyun .best_encoder = radeon_best_single_encoder,
983*4882a593Smuzhiyun };
984*4882a593Smuzhiyun
985*4882a593Smuzhiyun static const struct drm_connector_funcs radeon_lvds_connector_funcs = {
986*4882a593Smuzhiyun .dpms = drm_helper_connector_dpms,
987*4882a593Smuzhiyun .detect = radeon_lvds_detect,
988*4882a593Smuzhiyun .fill_modes = drm_helper_probe_single_connector_modes,
989*4882a593Smuzhiyun .early_unregister = radeon_connector_unregister,
990*4882a593Smuzhiyun .destroy = radeon_connector_destroy,
991*4882a593Smuzhiyun .set_property = radeon_lvds_set_property,
992*4882a593Smuzhiyun };
993*4882a593Smuzhiyun
radeon_vga_get_modes(struct drm_connector * connector)994*4882a593Smuzhiyun static int radeon_vga_get_modes(struct drm_connector *connector)
995*4882a593Smuzhiyun {
996*4882a593Smuzhiyun int ret;
997*4882a593Smuzhiyun
998*4882a593Smuzhiyun radeon_connector_get_edid(connector);
999*4882a593Smuzhiyun ret = radeon_ddc_get_modes(connector);
1000*4882a593Smuzhiyun
1001*4882a593Smuzhiyun radeon_get_native_mode(connector);
1002*4882a593Smuzhiyun
1003*4882a593Smuzhiyun return ret;
1004*4882a593Smuzhiyun }
1005*4882a593Smuzhiyun
radeon_vga_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)1006*4882a593Smuzhiyun static enum drm_mode_status radeon_vga_mode_valid(struct drm_connector *connector,
1007*4882a593Smuzhiyun struct drm_display_mode *mode)
1008*4882a593Smuzhiyun {
1009*4882a593Smuzhiyun struct drm_device *dev = connector->dev;
1010*4882a593Smuzhiyun struct radeon_device *rdev = dev->dev_private;
1011*4882a593Smuzhiyun
1012*4882a593Smuzhiyun /* XXX check mode bandwidth */
1013*4882a593Smuzhiyun
1014*4882a593Smuzhiyun if ((mode->clock / 10) > rdev->clock.max_pixel_clock)
1015*4882a593Smuzhiyun return MODE_CLOCK_HIGH;
1016*4882a593Smuzhiyun
1017*4882a593Smuzhiyun return MODE_OK;
1018*4882a593Smuzhiyun }
1019*4882a593Smuzhiyun
1020*4882a593Smuzhiyun static enum drm_connector_status
radeon_vga_detect(struct drm_connector * connector,bool force)1021*4882a593Smuzhiyun radeon_vga_detect(struct drm_connector *connector, bool force)
1022*4882a593Smuzhiyun {
1023*4882a593Smuzhiyun struct drm_device *dev = connector->dev;
1024*4882a593Smuzhiyun struct radeon_device *rdev = dev->dev_private;
1025*4882a593Smuzhiyun struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1026*4882a593Smuzhiyun struct drm_encoder *encoder;
1027*4882a593Smuzhiyun const struct drm_encoder_helper_funcs *encoder_funcs;
1028*4882a593Smuzhiyun bool dret = false;
1029*4882a593Smuzhiyun enum drm_connector_status ret = connector_status_disconnected;
1030*4882a593Smuzhiyun int r;
1031*4882a593Smuzhiyun
1032*4882a593Smuzhiyun if (!drm_kms_helper_is_poll_worker()) {
1033*4882a593Smuzhiyun r = pm_runtime_get_sync(connector->dev->dev);
1034*4882a593Smuzhiyun if (r < 0) {
1035*4882a593Smuzhiyun pm_runtime_put_autosuspend(connector->dev->dev);
1036*4882a593Smuzhiyun return connector_status_disconnected;
1037*4882a593Smuzhiyun }
1038*4882a593Smuzhiyun }
1039*4882a593Smuzhiyun
1040*4882a593Smuzhiyun encoder = radeon_best_single_encoder(connector);
1041*4882a593Smuzhiyun if (!encoder)
1042*4882a593Smuzhiyun ret = connector_status_disconnected;
1043*4882a593Smuzhiyun
1044*4882a593Smuzhiyun if (radeon_connector->ddc_bus)
1045*4882a593Smuzhiyun dret = radeon_ddc_probe(radeon_connector, false);
1046*4882a593Smuzhiyun if (dret) {
1047*4882a593Smuzhiyun radeon_connector->detected_by_load = false;
1048*4882a593Smuzhiyun radeon_connector_free_edid(connector);
1049*4882a593Smuzhiyun radeon_connector_get_edid(connector);
1050*4882a593Smuzhiyun
1051*4882a593Smuzhiyun if (!radeon_connector->edid) {
1052*4882a593Smuzhiyun DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
1053*4882a593Smuzhiyun connector->name);
1054*4882a593Smuzhiyun ret = connector_status_connected;
1055*4882a593Smuzhiyun } else {
1056*4882a593Smuzhiyun radeon_connector->use_digital =
1057*4882a593Smuzhiyun !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
1058*4882a593Smuzhiyun
1059*4882a593Smuzhiyun /* some oems have boards with separate digital and analog connectors
1060*4882a593Smuzhiyun * with a shared ddc line (often vga + hdmi)
1061*4882a593Smuzhiyun */
1062*4882a593Smuzhiyun if (radeon_connector->use_digital && radeon_connector->shared_ddc) {
1063*4882a593Smuzhiyun radeon_connector_free_edid(connector);
1064*4882a593Smuzhiyun ret = connector_status_disconnected;
1065*4882a593Smuzhiyun } else {
1066*4882a593Smuzhiyun ret = connector_status_connected;
1067*4882a593Smuzhiyun }
1068*4882a593Smuzhiyun }
1069*4882a593Smuzhiyun } else {
1070*4882a593Smuzhiyun
1071*4882a593Smuzhiyun /* if we aren't forcing don't do destructive polling */
1072*4882a593Smuzhiyun if (!force) {
1073*4882a593Smuzhiyun /* only return the previous status if we last
1074*4882a593Smuzhiyun * detected a monitor via load.
1075*4882a593Smuzhiyun */
1076*4882a593Smuzhiyun if (radeon_connector->detected_by_load)
1077*4882a593Smuzhiyun ret = connector->status;
1078*4882a593Smuzhiyun goto out;
1079*4882a593Smuzhiyun }
1080*4882a593Smuzhiyun
1081*4882a593Smuzhiyun if (radeon_connector->dac_load_detect && encoder) {
1082*4882a593Smuzhiyun encoder_funcs = encoder->helper_private;
1083*4882a593Smuzhiyun ret = encoder_funcs->detect(encoder, connector);
1084*4882a593Smuzhiyun if (ret != connector_status_disconnected)
1085*4882a593Smuzhiyun radeon_connector->detected_by_load = true;
1086*4882a593Smuzhiyun }
1087*4882a593Smuzhiyun }
1088*4882a593Smuzhiyun
1089*4882a593Smuzhiyun if (ret == connector_status_connected)
1090*4882a593Smuzhiyun ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, true);
1091*4882a593Smuzhiyun
1092*4882a593Smuzhiyun /* RN50 and some RV100 asics in servers often have a hardcoded EDID in the
1093*4882a593Smuzhiyun * vbios to deal with KVMs. If we have one and are not able to detect a monitor
1094*4882a593Smuzhiyun * by other means, assume the CRT is connected and use that EDID.
1095*4882a593Smuzhiyun */
1096*4882a593Smuzhiyun if ((!rdev->is_atom_bios) &&
1097*4882a593Smuzhiyun (ret == connector_status_disconnected) &&
1098*4882a593Smuzhiyun rdev->mode_info.bios_hardcoded_edid_size) {
1099*4882a593Smuzhiyun ret = connector_status_connected;
1100*4882a593Smuzhiyun }
1101*4882a593Smuzhiyun
1102*4882a593Smuzhiyun radeon_connector_update_scratch_regs(connector, ret);
1103*4882a593Smuzhiyun
1104*4882a593Smuzhiyun out:
1105*4882a593Smuzhiyun if (!drm_kms_helper_is_poll_worker()) {
1106*4882a593Smuzhiyun pm_runtime_mark_last_busy(connector->dev->dev);
1107*4882a593Smuzhiyun pm_runtime_put_autosuspend(connector->dev->dev);
1108*4882a593Smuzhiyun }
1109*4882a593Smuzhiyun
1110*4882a593Smuzhiyun return ret;
1111*4882a593Smuzhiyun }
1112*4882a593Smuzhiyun
1113*4882a593Smuzhiyun static const struct drm_connector_helper_funcs radeon_vga_connector_helper_funcs = {
1114*4882a593Smuzhiyun .get_modes = radeon_vga_get_modes,
1115*4882a593Smuzhiyun .mode_valid = radeon_vga_mode_valid,
1116*4882a593Smuzhiyun .best_encoder = radeon_best_single_encoder,
1117*4882a593Smuzhiyun };
1118*4882a593Smuzhiyun
1119*4882a593Smuzhiyun static const struct drm_connector_funcs radeon_vga_connector_funcs = {
1120*4882a593Smuzhiyun .dpms = drm_helper_connector_dpms,
1121*4882a593Smuzhiyun .detect = radeon_vga_detect,
1122*4882a593Smuzhiyun .fill_modes = drm_helper_probe_single_connector_modes,
1123*4882a593Smuzhiyun .early_unregister = radeon_connector_unregister,
1124*4882a593Smuzhiyun .destroy = radeon_connector_destroy,
1125*4882a593Smuzhiyun .set_property = radeon_connector_set_property,
1126*4882a593Smuzhiyun };
1127*4882a593Smuzhiyun
radeon_tv_get_modes(struct drm_connector * connector)1128*4882a593Smuzhiyun static int radeon_tv_get_modes(struct drm_connector *connector)
1129*4882a593Smuzhiyun {
1130*4882a593Smuzhiyun struct drm_device *dev = connector->dev;
1131*4882a593Smuzhiyun struct radeon_device *rdev = dev->dev_private;
1132*4882a593Smuzhiyun struct drm_display_mode *tv_mode;
1133*4882a593Smuzhiyun struct drm_encoder *encoder;
1134*4882a593Smuzhiyun
1135*4882a593Smuzhiyun encoder = radeon_best_single_encoder(connector);
1136*4882a593Smuzhiyun if (!encoder)
1137*4882a593Smuzhiyun return 0;
1138*4882a593Smuzhiyun
1139*4882a593Smuzhiyun /* avivo chips can scale any mode */
1140*4882a593Smuzhiyun if (rdev->family >= CHIP_RS600)
1141*4882a593Smuzhiyun /* add scaled modes */
1142*4882a593Smuzhiyun radeon_add_common_modes(encoder, connector);
1143*4882a593Smuzhiyun else {
1144*4882a593Smuzhiyun /* only 800x600 is supported right now on pre-avivo chips */
1145*4882a593Smuzhiyun tv_mode = drm_cvt_mode(dev, 800, 600, 60, false, false, false);
1146*4882a593Smuzhiyun tv_mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
1147*4882a593Smuzhiyun drm_mode_probed_add(connector, tv_mode);
1148*4882a593Smuzhiyun }
1149*4882a593Smuzhiyun return 1;
1150*4882a593Smuzhiyun }
1151*4882a593Smuzhiyun
radeon_tv_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)1152*4882a593Smuzhiyun static enum drm_mode_status radeon_tv_mode_valid(struct drm_connector *connector,
1153*4882a593Smuzhiyun struct drm_display_mode *mode)
1154*4882a593Smuzhiyun {
1155*4882a593Smuzhiyun if ((mode->hdisplay > 1024) || (mode->vdisplay > 768))
1156*4882a593Smuzhiyun return MODE_CLOCK_RANGE;
1157*4882a593Smuzhiyun return MODE_OK;
1158*4882a593Smuzhiyun }
1159*4882a593Smuzhiyun
1160*4882a593Smuzhiyun static enum drm_connector_status
radeon_tv_detect(struct drm_connector * connector,bool force)1161*4882a593Smuzhiyun radeon_tv_detect(struct drm_connector *connector, bool force)
1162*4882a593Smuzhiyun {
1163*4882a593Smuzhiyun struct drm_encoder *encoder;
1164*4882a593Smuzhiyun const struct drm_encoder_helper_funcs *encoder_funcs;
1165*4882a593Smuzhiyun struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1166*4882a593Smuzhiyun enum drm_connector_status ret = connector_status_disconnected;
1167*4882a593Smuzhiyun int r;
1168*4882a593Smuzhiyun
1169*4882a593Smuzhiyun if (!radeon_connector->dac_load_detect)
1170*4882a593Smuzhiyun return ret;
1171*4882a593Smuzhiyun
1172*4882a593Smuzhiyun if (!drm_kms_helper_is_poll_worker()) {
1173*4882a593Smuzhiyun r = pm_runtime_get_sync(connector->dev->dev);
1174*4882a593Smuzhiyun if (r < 0) {
1175*4882a593Smuzhiyun pm_runtime_put_autosuspend(connector->dev->dev);
1176*4882a593Smuzhiyun return connector_status_disconnected;
1177*4882a593Smuzhiyun }
1178*4882a593Smuzhiyun }
1179*4882a593Smuzhiyun
1180*4882a593Smuzhiyun encoder = radeon_best_single_encoder(connector);
1181*4882a593Smuzhiyun if (!encoder)
1182*4882a593Smuzhiyun ret = connector_status_disconnected;
1183*4882a593Smuzhiyun else {
1184*4882a593Smuzhiyun encoder_funcs = encoder->helper_private;
1185*4882a593Smuzhiyun ret = encoder_funcs->detect(encoder, connector);
1186*4882a593Smuzhiyun }
1187*4882a593Smuzhiyun if (ret == connector_status_connected)
1188*4882a593Smuzhiyun ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, false);
1189*4882a593Smuzhiyun radeon_connector_update_scratch_regs(connector, ret);
1190*4882a593Smuzhiyun
1191*4882a593Smuzhiyun if (!drm_kms_helper_is_poll_worker()) {
1192*4882a593Smuzhiyun pm_runtime_mark_last_busy(connector->dev->dev);
1193*4882a593Smuzhiyun pm_runtime_put_autosuspend(connector->dev->dev);
1194*4882a593Smuzhiyun }
1195*4882a593Smuzhiyun
1196*4882a593Smuzhiyun return ret;
1197*4882a593Smuzhiyun }
1198*4882a593Smuzhiyun
1199*4882a593Smuzhiyun static const struct drm_connector_helper_funcs radeon_tv_connector_helper_funcs = {
1200*4882a593Smuzhiyun .get_modes = radeon_tv_get_modes,
1201*4882a593Smuzhiyun .mode_valid = radeon_tv_mode_valid,
1202*4882a593Smuzhiyun .best_encoder = radeon_best_single_encoder,
1203*4882a593Smuzhiyun };
1204*4882a593Smuzhiyun
1205*4882a593Smuzhiyun static const struct drm_connector_funcs radeon_tv_connector_funcs = {
1206*4882a593Smuzhiyun .dpms = drm_helper_connector_dpms,
1207*4882a593Smuzhiyun .detect = radeon_tv_detect,
1208*4882a593Smuzhiyun .fill_modes = drm_helper_probe_single_connector_modes,
1209*4882a593Smuzhiyun .early_unregister = radeon_connector_unregister,
1210*4882a593Smuzhiyun .destroy = radeon_connector_destroy,
1211*4882a593Smuzhiyun .set_property = radeon_connector_set_property,
1212*4882a593Smuzhiyun };
1213*4882a593Smuzhiyun
radeon_check_hpd_status_unchanged(struct drm_connector * connector)1214*4882a593Smuzhiyun static bool radeon_check_hpd_status_unchanged(struct drm_connector *connector)
1215*4882a593Smuzhiyun {
1216*4882a593Smuzhiyun struct drm_device *dev = connector->dev;
1217*4882a593Smuzhiyun struct radeon_device *rdev = dev->dev_private;
1218*4882a593Smuzhiyun struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1219*4882a593Smuzhiyun enum drm_connector_status status;
1220*4882a593Smuzhiyun
1221*4882a593Smuzhiyun /* We only trust HPD on R600 and newer ASICS. */
1222*4882a593Smuzhiyun if (rdev->family >= CHIP_R600
1223*4882a593Smuzhiyun && radeon_connector->hpd.hpd != RADEON_HPD_NONE) {
1224*4882a593Smuzhiyun if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1225*4882a593Smuzhiyun status = connector_status_connected;
1226*4882a593Smuzhiyun else
1227*4882a593Smuzhiyun status = connector_status_disconnected;
1228*4882a593Smuzhiyun if (connector->status == status)
1229*4882a593Smuzhiyun return true;
1230*4882a593Smuzhiyun }
1231*4882a593Smuzhiyun
1232*4882a593Smuzhiyun return false;
1233*4882a593Smuzhiyun }
1234*4882a593Smuzhiyun
1235*4882a593Smuzhiyun /*
1236*4882a593Smuzhiyun * DVI is complicated
1237*4882a593Smuzhiyun * Do a DDC probe, if DDC probe passes, get the full EDID so
1238*4882a593Smuzhiyun * we can do analog/digital monitor detection at this point.
1239*4882a593Smuzhiyun * If the monitor is an analog monitor or we got no DDC,
1240*4882a593Smuzhiyun * we need to find the DAC encoder object for this connector.
1241*4882a593Smuzhiyun * If we got no DDC, we do load detection on the DAC encoder object.
1242*4882a593Smuzhiyun * If we got analog DDC or load detection passes on the DAC encoder
1243*4882a593Smuzhiyun * we have to check if this analog encoder is shared with anyone else (TV)
1244*4882a593Smuzhiyun * if its shared we have to set the other connector to disconnected.
1245*4882a593Smuzhiyun */
1246*4882a593Smuzhiyun static enum drm_connector_status
radeon_dvi_detect(struct drm_connector * connector,bool force)1247*4882a593Smuzhiyun radeon_dvi_detect(struct drm_connector *connector, bool force)
1248*4882a593Smuzhiyun {
1249*4882a593Smuzhiyun struct drm_device *dev = connector->dev;
1250*4882a593Smuzhiyun struct radeon_device *rdev = dev->dev_private;
1251*4882a593Smuzhiyun struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1252*4882a593Smuzhiyun struct drm_encoder *encoder = NULL;
1253*4882a593Smuzhiyun const struct drm_encoder_helper_funcs *encoder_funcs;
1254*4882a593Smuzhiyun int r;
1255*4882a593Smuzhiyun enum drm_connector_status ret = connector_status_disconnected;
1256*4882a593Smuzhiyun bool dret = false, broken_edid = false;
1257*4882a593Smuzhiyun
1258*4882a593Smuzhiyun if (!drm_kms_helper_is_poll_worker()) {
1259*4882a593Smuzhiyun r = pm_runtime_get_sync(connector->dev->dev);
1260*4882a593Smuzhiyun if (r < 0) {
1261*4882a593Smuzhiyun pm_runtime_put_autosuspend(connector->dev->dev);
1262*4882a593Smuzhiyun return connector_status_disconnected;
1263*4882a593Smuzhiyun }
1264*4882a593Smuzhiyun }
1265*4882a593Smuzhiyun
1266*4882a593Smuzhiyun if (radeon_connector->detected_hpd_without_ddc) {
1267*4882a593Smuzhiyun force = true;
1268*4882a593Smuzhiyun radeon_connector->detected_hpd_without_ddc = false;
1269*4882a593Smuzhiyun }
1270*4882a593Smuzhiyun
1271*4882a593Smuzhiyun if (!force && radeon_check_hpd_status_unchanged(connector)) {
1272*4882a593Smuzhiyun ret = connector->status;
1273*4882a593Smuzhiyun goto exit;
1274*4882a593Smuzhiyun }
1275*4882a593Smuzhiyun
1276*4882a593Smuzhiyun if (radeon_connector->ddc_bus) {
1277*4882a593Smuzhiyun dret = radeon_ddc_probe(radeon_connector, false);
1278*4882a593Smuzhiyun
1279*4882a593Smuzhiyun /* Sometimes the pins required for the DDC probe on DVI
1280*4882a593Smuzhiyun * connectors don't make contact at the same time that the ones
1281*4882a593Smuzhiyun * for HPD do. If the DDC probe fails even though we had an HPD
1282*4882a593Smuzhiyun * signal, try again later */
1283*4882a593Smuzhiyun if (!dret && !force &&
1284*4882a593Smuzhiyun connector->status != connector_status_connected) {
1285*4882a593Smuzhiyun DRM_DEBUG_KMS("hpd detected without ddc, retrying in 1 second\n");
1286*4882a593Smuzhiyun radeon_connector->detected_hpd_without_ddc = true;
1287*4882a593Smuzhiyun schedule_delayed_work(&rdev->hotplug_work,
1288*4882a593Smuzhiyun msecs_to_jiffies(1000));
1289*4882a593Smuzhiyun goto exit;
1290*4882a593Smuzhiyun }
1291*4882a593Smuzhiyun }
1292*4882a593Smuzhiyun if (dret) {
1293*4882a593Smuzhiyun radeon_connector->detected_by_load = false;
1294*4882a593Smuzhiyun radeon_connector_free_edid(connector);
1295*4882a593Smuzhiyun radeon_connector_get_edid(connector);
1296*4882a593Smuzhiyun
1297*4882a593Smuzhiyun if (!radeon_connector->edid) {
1298*4882a593Smuzhiyun DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
1299*4882a593Smuzhiyun connector->name);
1300*4882a593Smuzhiyun /* rs690 seems to have a problem with connectors not existing and always
1301*4882a593Smuzhiyun * return a block of 0's. If we see this just stop polling on this output */
1302*4882a593Smuzhiyun if ((rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) &&
1303*4882a593Smuzhiyun radeon_connector->base.null_edid_counter) {
1304*4882a593Smuzhiyun ret = connector_status_disconnected;
1305*4882a593Smuzhiyun DRM_ERROR("%s: detected RS690 floating bus bug, stopping ddc detect\n",
1306*4882a593Smuzhiyun connector->name);
1307*4882a593Smuzhiyun radeon_connector->ddc_bus = NULL;
1308*4882a593Smuzhiyun } else {
1309*4882a593Smuzhiyun ret = connector_status_connected;
1310*4882a593Smuzhiyun broken_edid = true; /* defer use_digital to later */
1311*4882a593Smuzhiyun }
1312*4882a593Smuzhiyun } else {
1313*4882a593Smuzhiyun radeon_connector->use_digital =
1314*4882a593Smuzhiyun !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
1315*4882a593Smuzhiyun
1316*4882a593Smuzhiyun /* some oems have boards with separate digital and analog connectors
1317*4882a593Smuzhiyun * with a shared ddc line (often vga + hdmi)
1318*4882a593Smuzhiyun */
1319*4882a593Smuzhiyun if ((!radeon_connector->use_digital) && radeon_connector->shared_ddc) {
1320*4882a593Smuzhiyun radeon_connector_free_edid(connector);
1321*4882a593Smuzhiyun ret = connector_status_disconnected;
1322*4882a593Smuzhiyun } else {
1323*4882a593Smuzhiyun ret = connector_status_connected;
1324*4882a593Smuzhiyun }
1325*4882a593Smuzhiyun /* This gets complicated. We have boards with VGA + HDMI with a
1326*4882a593Smuzhiyun * shared DDC line and we have boards with DVI-D + HDMI with a shared
1327*4882a593Smuzhiyun * DDC line. The latter is more complex because with DVI<->HDMI adapters
1328*4882a593Smuzhiyun * you don't really know what's connected to which port as both are digital.
1329*4882a593Smuzhiyun */
1330*4882a593Smuzhiyun if (radeon_connector->shared_ddc && (ret == connector_status_connected)) {
1331*4882a593Smuzhiyun struct drm_connector *list_connector;
1332*4882a593Smuzhiyun struct radeon_connector *list_radeon_connector;
1333*4882a593Smuzhiyun list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) {
1334*4882a593Smuzhiyun if (connector == list_connector)
1335*4882a593Smuzhiyun continue;
1336*4882a593Smuzhiyun list_radeon_connector = to_radeon_connector(list_connector);
1337*4882a593Smuzhiyun if (list_radeon_connector->shared_ddc &&
1338*4882a593Smuzhiyun (list_radeon_connector->ddc_bus->rec.i2c_id ==
1339*4882a593Smuzhiyun radeon_connector->ddc_bus->rec.i2c_id)) {
1340*4882a593Smuzhiyun /* cases where both connectors are digital */
1341*4882a593Smuzhiyun if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
1342*4882a593Smuzhiyun /* hpd is our only option in this case */
1343*4882a593Smuzhiyun if (!radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) {
1344*4882a593Smuzhiyun radeon_connector_free_edid(connector);
1345*4882a593Smuzhiyun ret = connector_status_disconnected;
1346*4882a593Smuzhiyun }
1347*4882a593Smuzhiyun }
1348*4882a593Smuzhiyun }
1349*4882a593Smuzhiyun }
1350*4882a593Smuzhiyun }
1351*4882a593Smuzhiyun }
1352*4882a593Smuzhiyun }
1353*4882a593Smuzhiyun
1354*4882a593Smuzhiyun if ((ret == connector_status_connected) && (radeon_connector->use_digital == true))
1355*4882a593Smuzhiyun goto out;
1356*4882a593Smuzhiyun
1357*4882a593Smuzhiyun /* DVI-D and HDMI-A are digital only */
1358*4882a593Smuzhiyun if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) ||
1359*4882a593Smuzhiyun (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))
1360*4882a593Smuzhiyun goto out;
1361*4882a593Smuzhiyun
1362*4882a593Smuzhiyun /* if we aren't forcing don't do destructive polling */
1363*4882a593Smuzhiyun if (!force) {
1364*4882a593Smuzhiyun /* only return the previous status if we last
1365*4882a593Smuzhiyun * detected a monitor via load.
1366*4882a593Smuzhiyun */
1367*4882a593Smuzhiyun if (radeon_connector->detected_by_load)
1368*4882a593Smuzhiyun ret = connector->status;
1369*4882a593Smuzhiyun goto out;
1370*4882a593Smuzhiyun }
1371*4882a593Smuzhiyun
1372*4882a593Smuzhiyun /* find analog encoder */
1373*4882a593Smuzhiyun if (radeon_connector->dac_load_detect) {
1374*4882a593Smuzhiyun drm_connector_for_each_possible_encoder(connector, encoder) {
1375*4882a593Smuzhiyun if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
1376*4882a593Smuzhiyun encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
1377*4882a593Smuzhiyun continue;
1378*4882a593Smuzhiyun
1379*4882a593Smuzhiyun encoder_funcs = encoder->helper_private;
1380*4882a593Smuzhiyun if (encoder_funcs->detect) {
1381*4882a593Smuzhiyun if (!broken_edid) {
1382*4882a593Smuzhiyun if (ret != connector_status_connected) {
1383*4882a593Smuzhiyun /* deal with analog monitors without DDC */
1384*4882a593Smuzhiyun ret = encoder_funcs->detect(encoder, connector);
1385*4882a593Smuzhiyun if (ret == connector_status_connected) {
1386*4882a593Smuzhiyun radeon_connector->use_digital = false;
1387*4882a593Smuzhiyun }
1388*4882a593Smuzhiyun if (ret != connector_status_disconnected)
1389*4882a593Smuzhiyun radeon_connector->detected_by_load = true;
1390*4882a593Smuzhiyun }
1391*4882a593Smuzhiyun } else {
1392*4882a593Smuzhiyun enum drm_connector_status lret;
1393*4882a593Smuzhiyun /* assume digital unless load detected otherwise */
1394*4882a593Smuzhiyun radeon_connector->use_digital = true;
1395*4882a593Smuzhiyun lret = encoder_funcs->detect(encoder, connector);
1396*4882a593Smuzhiyun DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret);
1397*4882a593Smuzhiyun if (lret == connector_status_connected)
1398*4882a593Smuzhiyun radeon_connector->use_digital = false;
1399*4882a593Smuzhiyun }
1400*4882a593Smuzhiyun break;
1401*4882a593Smuzhiyun }
1402*4882a593Smuzhiyun }
1403*4882a593Smuzhiyun }
1404*4882a593Smuzhiyun
1405*4882a593Smuzhiyun if ((ret == connector_status_connected) && (radeon_connector->use_digital == false) &&
1406*4882a593Smuzhiyun encoder) {
1407*4882a593Smuzhiyun ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, true);
1408*4882a593Smuzhiyun }
1409*4882a593Smuzhiyun
1410*4882a593Smuzhiyun /* RN50 and some RV100 asics in servers often have a hardcoded EDID in the
1411*4882a593Smuzhiyun * vbios to deal with KVMs. If we have one and are not able to detect a monitor
1412*4882a593Smuzhiyun * by other means, assume the DFP is connected and use that EDID. In most
1413*4882a593Smuzhiyun * cases the DVI port is actually a virtual KVM port connected to the service
1414*4882a593Smuzhiyun * processor.
1415*4882a593Smuzhiyun */
1416*4882a593Smuzhiyun out:
1417*4882a593Smuzhiyun if ((!rdev->is_atom_bios) &&
1418*4882a593Smuzhiyun (ret == connector_status_disconnected) &&
1419*4882a593Smuzhiyun rdev->mode_info.bios_hardcoded_edid_size) {
1420*4882a593Smuzhiyun radeon_connector->use_digital = true;
1421*4882a593Smuzhiyun ret = connector_status_connected;
1422*4882a593Smuzhiyun }
1423*4882a593Smuzhiyun
1424*4882a593Smuzhiyun /* updated in get modes as well since we need to know if it's analog or digital */
1425*4882a593Smuzhiyun radeon_connector_update_scratch_regs(connector, ret);
1426*4882a593Smuzhiyun
1427*4882a593Smuzhiyun if ((radeon_audio != 0) && radeon_connector->use_digital) {
1428*4882a593Smuzhiyun const struct drm_connector_helper_funcs *connector_funcs =
1429*4882a593Smuzhiyun connector->helper_private;
1430*4882a593Smuzhiyun
1431*4882a593Smuzhiyun encoder = connector_funcs->best_encoder(connector);
1432*4882a593Smuzhiyun if (encoder && (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)) {
1433*4882a593Smuzhiyun radeon_connector_get_edid(connector);
1434*4882a593Smuzhiyun radeon_audio_detect(connector, encoder, ret);
1435*4882a593Smuzhiyun }
1436*4882a593Smuzhiyun }
1437*4882a593Smuzhiyun
1438*4882a593Smuzhiyun exit:
1439*4882a593Smuzhiyun if (!drm_kms_helper_is_poll_worker()) {
1440*4882a593Smuzhiyun pm_runtime_mark_last_busy(connector->dev->dev);
1441*4882a593Smuzhiyun pm_runtime_put_autosuspend(connector->dev->dev);
1442*4882a593Smuzhiyun }
1443*4882a593Smuzhiyun
1444*4882a593Smuzhiyun return ret;
1445*4882a593Smuzhiyun }
1446*4882a593Smuzhiyun
1447*4882a593Smuzhiyun /* okay need to be smart in here about which encoder to pick */
radeon_dvi_encoder(struct drm_connector * connector)1448*4882a593Smuzhiyun static struct drm_encoder *radeon_dvi_encoder(struct drm_connector *connector)
1449*4882a593Smuzhiyun {
1450*4882a593Smuzhiyun struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1451*4882a593Smuzhiyun struct drm_encoder *encoder;
1452*4882a593Smuzhiyun
1453*4882a593Smuzhiyun drm_connector_for_each_possible_encoder(connector, encoder) {
1454*4882a593Smuzhiyun if (radeon_connector->use_digital == true) {
1455*4882a593Smuzhiyun if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1456*4882a593Smuzhiyun return encoder;
1457*4882a593Smuzhiyun } else {
1458*4882a593Smuzhiyun if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
1459*4882a593Smuzhiyun encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1460*4882a593Smuzhiyun return encoder;
1461*4882a593Smuzhiyun }
1462*4882a593Smuzhiyun }
1463*4882a593Smuzhiyun
1464*4882a593Smuzhiyun /* see if we have a default encoder TODO */
1465*4882a593Smuzhiyun
1466*4882a593Smuzhiyun /* then check use digitial */
1467*4882a593Smuzhiyun /* pick the first one */
1468*4882a593Smuzhiyun drm_connector_for_each_possible_encoder(connector, encoder)
1469*4882a593Smuzhiyun return encoder;
1470*4882a593Smuzhiyun
1471*4882a593Smuzhiyun return NULL;
1472*4882a593Smuzhiyun }
1473*4882a593Smuzhiyun
radeon_dvi_force(struct drm_connector * connector)1474*4882a593Smuzhiyun static void radeon_dvi_force(struct drm_connector *connector)
1475*4882a593Smuzhiyun {
1476*4882a593Smuzhiyun struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1477*4882a593Smuzhiyun if (connector->force == DRM_FORCE_ON)
1478*4882a593Smuzhiyun radeon_connector->use_digital = false;
1479*4882a593Smuzhiyun if (connector->force == DRM_FORCE_ON_DIGITAL)
1480*4882a593Smuzhiyun radeon_connector->use_digital = true;
1481*4882a593Smuzhiyun }
1482*4882a593Smuzhiyun
radeon_dvi_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)1483*4882a593Smuzhiyun static enum drm_mode_status radeon_dvi_mode_valid(struct drm_connector *connector,
1484*4882a593Smuzhiyun struct drm_display_mode *mode)
1485*4882a593Smuzhiyun {
1486*4882a593Smuzhiyun struct drm_device *dev = connector->dev;
1487*4882a593Smuzhiyun struct radeon_device *rdev = dev->dev_private;
1488*4882a593Smuzhiyun struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1489*4882a593Smuzhiyun
1490*4882a593Smuzhiyun /* XXX check mode bandwidth */
1491*4882a593Smuzhiyun
1492*4882a593Smuzhiyun /* clocks over 135 MHz have heat issues with DVI on RV100 */
1493*4882a593Smuzhiyun if (radeon_connector->use_digital &&
1494*4882a593Smuzhiyun (rdev->family == CHIP_RV100) &&
1495*4882a593Smuzhiyun (mode->clock > 135000))
1496*4882a593Smuzhiyun return MODE_CLOCK_HIGH;
1497*4882a593Smuzhiyun
1498*4882a593Smuzhiyun if (radeon_connector->use_digital && (mode->clock > 165000)) {
1499*4882a593Smuzhiyun if ((radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
1500*4882a593Smuzhiyun (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
1501*4882a593Smuzhiyun (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B))
1502*4882a593Smuzhiyun return MODE_OK;
1503*4882a593Smuzhiyun else if (ASIC_IS_DCE6(rdev) && drm_detect_hdmi_monitor(radeon_connector_edid(connector))) {
1504*4882a593Smuzhiyun /* HDMI 1.3+ supports max clock of 340 Mhz */
1505*4882a593Smuzhiyun if (mode->clock > 340000)
1506*4882a593Smuzhiyun return MODE_CLOCK_HIGH;
1507*4882a593Smuzhiyun else
1508*4882a593Smuzhiyun return MODE_OK;
1509*4882a593Smuzhiyun } else {
1510*4882a593Smuzhiyun return MODE_CLOCK_HIGH;
1511*4882a593Smuzhiyun }
1512*4882a593Smuzhiyun }
1513*4882a593Smuzhiyun
1514*4882a593Smuzhiyun /* check against the max pixel clock */
1515*4882a593Smuzhiyun if ((mode->clock / 10) > rdev->clock.max_pixel_clock)
1516*4882a593Smuzhiyun return MODE_CLOCK_HIGH;
1517*4882a593Smuzhiyun
1518*4882a593Smuzhiyun return MODE_OK;
1519*4882a593Smuzhiyun }
1520*4882a593Smuzhiyun
1521*4882a593Smuzhiyun static const struct drm_connector_helper_funcs radeon_dvi_connector_helper_funcs = {
1522*4882a593Smuzhiyun .get_modes = radeon_vga_get_modes,
1523*4882a593Smuzhiyun .mode_valid = radeon_dvi_mode_valid,
1524*4882a593Smuzhiyun .best_encoder = radeon_dvi_encoder,
1525*4882a593Smuzhiyun };
1526*4882a593Smuzhiyun
1527*4882a593Smuzhiyun static const struct drm_connector_funcs radeon_dvi_connector_funcs = {
1528*4882a593Smuzhiyun .dpms = drm_helper_connector_dpms,
1529*4882a593Smuzhiyun .detect = radeon_dvi_detect,
1530*4882a593Smuzhiyun .fill_modes = drm_helper_probe_single_connector_modes,
1531*4882a593Smuzhiyun .set_property = radeon_connector_set_property,
1532*4882a593Smuzhiyun .early_unregister = radeon_connector_unregister,
1533*4882a593Smuzhiyun .destroy = radeon_connector_destroy,
1534*4882a593Smuzhiyun .force = radeon_dvi_force,
1535*4882a593Smuzhiyun };
1536*4882a593Smuzhiyun
radeon_dp_get_modes(struct drm_connector * connector)1537*4882a593Smuzhiyun static int radeon_dp_get_modes(struct drm_connector *connector)
1538*4882a593Smuzhiyun {
1539*4882a593Smuzhiyun struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1540*4882a593Smuzhiyun struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
1541*4882a593Smuzhiyun struct drm_encoder *encoder = radeon_best_single_encoder(connector);
1542*4882a593Smuzhiyun int ret;
1543*4882a593Smuzhiyun
1544*4882a593Smuzhiyun if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1545*4882a593Smuzhiyun (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1546*4882a593Smuzhiyun struct drm_display_mode *mode;
1547*4882a593Smuzhiyun
1548*4882a593Smuzhiyun if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1549*4882a593Smuzhiyun if (!radeon_dig_connector->edp_on)
1550*4882a593Smuzhiyun atombios_set_edp_panel_power(connector,
1551*4882a593Smuzhiyun ATOM_TRANSMITTER_ACTION_POWER_ON);
1552*4882a593Smuzhiyun radeon_connector_get_edid(connector);
1553*4882a593Smuzhiyun ret = radeon_ddc_get_modes(connector);
1554*4882a593Smuzhiyun if (!radeon_dig_connector->edp_on)
1555*4882a593Smuzhiyun atombios_set_edp_panel_power(connector,
1556*4882a593Smuzhiyun ATOM_TRANSMITTER_ACTION_POWER_OFF);
1557*4882a593Smuzhiyun } else {
1558*4882a593Smuzhiyun /* need to setup ddc on the bridge */
1559*4882a593Smuzhiyun if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1560*4882a593Smuzhiyun ENCODER_OBJECT_ID_NONE) {
1561*4882a593Smuzhiyun if (encoder)
1562*4882a593Smuzhiyun radeon_atom_ext_encoder_setup_ddc(encoder);
1563*4882a593Smuzhiyun }
1564*4882a593Smuzhiyun radeon_connector_get_edid(connector);
1565*4882a593Smuzhiyun ret = radeon_ddc_get_modes(connector);
1566*4882a593Smuzhiyun }
1567*4882a593Smuzhiyun
1568*4882a593Smuzhiyun if (ret > 0) {
1569*4882a593Smuzhiyun if (encoder) {
1570*4882a593Smuzhiyun radeon_fixup_lvds_native_mode(encoder, connector);
1571*4882a593Smuzhiyun /* add scaled modes */
1572*4882a593Smuzhiyun radeon_add_common_modes(encoder, connector);
1573*4882a593Smuzhiyun }
1574*4882a593Smuzhiyun return ret;
1575*4882a593Smuzhiyun }
1576*4882a593Smuzhiyun
1577*4882a593Smuzhiyun if (!encoder)
1578*4882a593Smuzhiyun return 0;
1579*4882a593Smuzhiyun
1580*4882a593Smuzhiyun /* we have no EDID modes */
1581*4882a593Smuzhiyun mode = radeon_fp_native_mode(encoder);
1582*4882a593Smuzhiyun if (mode) {
1583*4882a593Smuzhiyun ret = 1;
1584*4882a593Smuzhiyun drm_mode_probed_add(connector, mode);
1585*4882a593Smuzhiyun /* add the width/height from vbios tables if available */
1586*4882a593Smuzhiyun connector->display_info.width_mm = mode->width_mm;
1587*4882a593Smuzhiyun connector->display_info.height_mm = mode->height_mm;
1588*4882a593Smuzhiyun /* add scaled modes */
1589*4882a593Smuzhiyun radeon_add_common_modes(encoder, connector);
1590*4882a593Smuzhiyun }
1591*4882a593Smuzhiyun } else {
1592*4882a593Smuzhiyun /* need to setup ddc on the bridge */
1593*4882a593Smuzhiyun if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1594*4882a593Smuzhiyun ENCODER_OBJECT_ID_NONE) {
1595*4882a593Smuzhiyun if (encoder)
1596*4882a593Smuzhiyun radeon_atom_ext_encoder_setup_ddc(encoder);
1597*4882a593Smuzhiyun }
1598*4882a593Smuzhiyun radeon_connector_get_edid(connector);
1599*4882a593Smuzhiyun ret = radeon_ddc_get_modes(connector);
1600*4882a593Smuzhiyun
1601*4882a593Smuzhiyun radeon_get_native_mode(connector);
1602*4882a593Smuzhiyun }
1603*4882a593Smuzhiyun
1604*4882a593Smuzhiyun return ret;
1605*4882a593Smuzhiyun }
1606*4882a593Smuzhiyun
radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector * connector)1607*4882a593Smuzhiyun u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
1608*4882a593Smuzhiyun {
1609*4882a593Smuzhiyun struct drm_encoder *encoder;
1610*4882a593Smuzhiyun struct radeon_encoder *radeon_encoder;
1611*4882a593Smuzhiyun
1612*4882a593Smuzhiyun drm_connector_for_each_possible_encoder(connector, encoder) {
1613*4882a593Smuzhiyun radeon_encoder = to_radeon_encoder(encoder);
1614*4882a593Smuzhiyun
1615*4882a593Smuzhiyun switch (radeon_encoder->encoder_id) {
1616*4882a593Smuzhiyun case ENCODER_OBJECT_ID_TRAVIS:
1617*4882a593Smuzhiyun case ENCODER_OBJECT_ID_NUTMEG:
1618*4882a593Smuzhiyun return radeon_encoder->encoder_id;
1619*4882a593Smuzhiyun default:
1620*4882a593Smuzhiyun break;
1621*4882a593Smuzhiyun }
1622*4882a593Smuzhiyun }
1623*4882a593Smuzhiyun
1624*4882a593Smuzhiyun return ENCODER_OBJECT_ID_NONE;
1625*4882a593Smuzhiyun }
1626*4882a593Smuzhiyun
radeon_connector_encoder_is_hbr2(struct drm_connector * connector)1627*4882a593Smuzhiyun static bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector)
1628*4882a593Smuzhiyun {
1629*4882a593Smuzhiyun struct drm_encoder *encoder;
1630*4882a593Smuzhiyun struct radeon_encoder *radeon_encoder;
1631*4882a593Smuzhiyun bool found = false;
1632*4882a593Smuzhiyun
1633*4882a593Smuzhiyun drm_connector_for_each_possible_encoder(connector, encoder) {
1634*4882a593Smuzhiyun radeon_encoder = to_radeon_encoder(encoder);
1635*4882a593Smuzhiyun if (radeon_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
1636*4882a593Smuzhiyun found = true;
1637*4882a593Smuzhiyun }
1638*4882a593Smuzhiyun
1639*4882a593Smuzhiyun return found;
1640*4882a593Smuzhiyun }
1641*4882a593Smuzhiyun
radeon_connector_is_dp12_capable(struct drm_connector * connector)1642*4882a593Smuzhiyun bool radeon_connector_is_dp12_capable(struct drm_connector *connector)
1643*4882a593Smuzhiyun {
1644*4882a593Smuzhiyun struct drm_device *dev = connector->dev;
1645*4882a593Smuzhiyun struct radeon_device *rdev = dev->dev_private;
1646*4882a593Smuzhiyun
1647*4882a593Smuzhiyun if (ASIC_IS_DCE5(rdev) &&
1648*4882a593Smuzhiyun (rdev->clock.default_dispclk >= 53900) &&
1649*4882a593Smuzhiyun radeon_connector_encoder_is_hbr2(connector)) {
1650*4882a593Smuzhiyun return true;
1651*4882a593Smuzhiyun }
1652*4882a593Smuzhiyun
1653*4882a593Smuzhiyun return false;
1654*4882a593Smuzhiyun }
1655*4882a593Smuzhiyun
1656*4882a593Smuzhiyun static enum drm_connector_status
radeon_dp_detect(struct drm_connector * connector,bool force)1657*4882a593Smuzhiyun radeon_dp_detect(struct drm_connector *connector, bool force)
1658*4882a593Smuzhiyun {
1659*4882a593Smuzhiyun struct drm_device *dev = connector->dev;
1660*4882a593Smuzhiyun struct radeon_device *rdev = dev->dev_private;
1661*4882a593Smuzhiyun struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1662*4882a593Smuzhiyun enum drm_connector_status ret = connector_status_disconnected;
1663*4882a593Smuzhiyun struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
1664*4882a593Smuzhiyun struct drm_encoder *encoder = radeon_best_single_encoder(connector);
1665*4882a593Smuzhiyun int r;
1666*4882a593Smuzhiyun
1667*4882a593Smuzhiyun if (radeon_dig_connector->is_mst)
1668*4882a593Smuzhiyun return connector_status_disconnected;
1669*4882a593Smuzhiyun
1670*4882a593Smuzhiyun if (!drm_kms_helper_is_poll_worker()) {
1671*4882a593Smuzhiyun r = pm_runtime_get_sync(connector->dev->dev);
1672*4882a593Smuzhiyun if (r < 0) {
1673*4882a593Smuzhiyun pm_runtime_put_autosuspend(connector->dev->dev);
1674*4882a593Smuzhiyun return connector_status_disconnected;
1675*4882a593Smuzhiyun }
1676*4882a593Smuzhiyun }
1677*4882a593Smuzhiyun
1678*4882a593Smuzhiyun if (!force && radeon_check_hpd_status_unchanged(connector)) {
1679*4882a593Smuzhiyun ret = connector->status;
1680*4882a593Smuzhiyun goto out;
1681*4882a593Smuzhiyun }
1682*4882a593Smuzhiyun
1683*4882a593Smuzhiyun radeon_connector_free_edid(connector);
1684*4882a593Smuzhiyun
1685*4882a593Smuzhiyun if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1686*4882a593Smuzhiyun (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1687*4882a593Smuzhiyun if (encoder) {
1688*4882a593Smuzhiyun struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1689*4882a593Smuzhiyun struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
1690*4882a593Smuzhiyun
1691*4882a593Smuzhiyun /* check if panel is valid */
1692*4882a593Smuzhiyun if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
1693*4882a593Smuzhiyun ret = connector_status_connected;
1694*4882a593Smuzhiyun /* don't fetch the edid from the vbios if ddc fails and runpm is
1695*4882a593Smuzhiyun * enabled so we report disconnected.
1696*4882a593Smuzhiyun */
1697*4882a593Smuzhiyun if ((rdev->flags & RADEON_IS_PX) && (radeon_runtime_pm != 0))
1698*4882a593Smuzhiyun ret = connector_status_disconnected;
1699*4882a593Smuzhiyun }
1700*4882a593Smuzhiyun /* eDP is always DP */
1701*4882a593Smuzhiyun radeon_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1702*4882a593Smuzhiyun if (!radeon_dig_connector->edp_on)
1703*4882a593Smuzhiyun atombios_set_edp_panel_power(connector,
1704*4882a593Smuzhiyun ATOM_TRANSMITTER_ACTION_POWER_ON);
1705*4882a593Smuzhiyun if (radeon_dp_getdpcd(radeon_connector))
1706*4882a593Smuzhiyun ret = connector_status_connected;
1707*4882a593Smuzhiyun if (!radeon_dig_connector->edp_on)
1708*4882a593Smuzhiyun atombios_set_edp_panel_power(connector,
1709*4882a593Smuzhiyun ATOM_TRANSMITTER_ACTION_POWER_OFF);
1710*4882a593Smuzhiyun } else if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1711*4882a593Smuzhiyun ENCODER_OBJECT_ID_NONE) {
1712*4882a593Smuzhiyun /* DP bridges are always DP */
1713*4882a593Smuzhiyun radeon_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1714*4882a593Smuzhiyun /* get the DPCD from the bridge */
1715*4882a593Smuzhiyun radeon_dp_getdpcd(radeon_connector);
1716*4882a593Smuzhiyun
1717*4882a593Smuzhiyun if (encoder) {
1718*4882a593Smuzhiyun /* setup ddc on the bridge */
1719*4882a593Smuzhiyun radeon_atom_ext_encoder_setup_ddc(encoder);
1720*4882a593Smuzhiyun /* bridge chips are always aux */
1721*4882a593Smuzhiyun if (radeon_ddc_probe(radeon_connector, true)) /* try DDC */
1722*4882a593Smuzhiyun ret = connector_status_connected;
1723*4882a593Smuzhiyun else if (radeon_connector->dac_load_detect) { /* try load detection */
1724*4882a593Smuzhiyun const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1725*4882a593Smuzhiyun ret = encoder_funcs->detect(encoder, connector);
1726*4882a593Smuzhiyun }
1727*4882a593Smuzhiyun }
1728*4882a593Smuzhiyun } else {
1729*4882a593Smuzhiyun radeon_dig_connector->dp_sink_type = radeon_dp_getsinktype(radeon_connector);
1730*4882a593Smuzhiyun if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) {
1731*4882a593Smuzhiyun ret = connector_status_connected;
1732*4882a593Smuzhiyun if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
1733*4882a593Smuzhiyun radeon_dp_getdpcd(radeon_connector);
1734*4882a593Smuzhiyun r = radeon_dp_mst_probe(radeon_connector);
1735*4882a593Smuzhiyun if (r == 1)
1736*4882a593Smuzhiyun ret = connector_status_disconnected;
1737*4882a593Smuzhiyun }
1738*4882a593Smuzhiyun } else {
1739*4882a593Smuzhiyun if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
1740*4882a593Smuzhiyun if (radeon_dp_getdpcd(radeon_connector)) {
1741*4882a593Smuzhiyun r = radeon_dp_mst_probe(radeon_connector);
1742*4882a593Smuzhiyun if (r == 1)
1743*4882a593Smuzhiyun ret = connector_status_disconnected;
1744*4882a593Smuzhiyun else
1745*4882a593Smuzhiyun ret = connector_status_connected;
1746*4882a593Smuzhiyun }
1747*4882a593Smuzhiyun } else {
1748*4882a593Smuzhiyun /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
1749*4882a593Smuzhiyun if (radeon_ddc_probe(radeon_connector, false))
1750*4882a593Smuzhiyun ret = connector_status_connected;
1751*4882a593Smuzhiyun }
1752*4882a593Smuzhiyun }
1753*4882a593Smuzhiyun }
1754*4882a593Smuzhiyun
1755*4882a593Smuzhiyun radeon_connector_update_scratch_regs(connector, ret);
1756*4882a593Smuzhiyun
1757*4882a593Smuzhiyun if ((radeon_audio != 0) && encoder) {
1758*4882a593Smuzhiyun radeon_connector_get_edid(connector);
1759*4882a593Smuzhiyun radeon_audio_detect(connector, encoder, ret);
1760*4882a593Smuzhiyun }
1761*4882a593Smuzhiyun
1762*4882a593Smuzhiyun out:
1763*4882a593Smuzhiyun if (!drm_kms_helper_is_poll_worker()) {
1764*4882a593Smuzhiyun pm_runtime_mark_last_busy(connector->dev->dev);
1765*4882a593Smuzhiyun pm_runtime_put_autosuspend(connector->dev->dev);
1766*4882a593Smuzhiyun }
1767*4882a593Smuzhiyun
1768*4882a593Smuzhiyun return ret;
1769*4882a593Smuzhiyun }
1770*4882a593Smuzhiyun
radeon_dp_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)1771*4882a593Smuzhiyun static enum drm_mode_status radeon_dp_mode_valid(struct drm_connector *connector,
1772*4882a593Smuzhiyun struct drm_display_mode *mode)
1773*4882a593Smuzhiyun {
1774*4882a593Smuzhiyun struct drm_device *dev = connector->dev;
1775*4882a593Smuzhiyun struct radeon_device *rdev = dev->dev_private;
1776*4882a593Smuzhiyun struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1777*4882a593Smuzhiyun struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
1778*4882a593Smuzhiyun
1779*4882a593Smuzhiyun /* XXX check mode bandwidth */
1780*4882a593Smuzhiyun
1781*4882a593Smuzhiyun if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1782*4882a593Smuzhiyun (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1783*4882a593Smuzhiyun struct drm_encoder *encoder = radeon_best_single_encoder(connector);
1784*4882a593Smuzhiyun
1785*4882a593Smuzhiyun if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
1786*4882a593Smuzhiyun return MODE_PANEL;
1787*4882a593Smuzhiyun
1788*4882a593Smuzhiyun if (encoder) {
1789*4882a593Smuzhiyun struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1790*4882a593Smuzhiyun struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
1791*4882a593Smuzhiyun
1792*4882a593Smuzhiyun /* AVIVO hardware supports downscaling modes larger than the panel
1793*4882a593Smuzhiyun * to the panel size, but I'm not sure this is desirable.
1794*4882a593Smuzhiyun */
1795*4882a593Smuzhiyun if ((mode->hdisplay > native_mode->hdisplay) ||
1796*4882a593Smuzhiyun (mode->vdisplay > native_mode->vdisplay))
1797*4882a593Smuzhiyun return MODE_PANEL;
1798*4882a593Smuzhiyun
1799*4882a593Smuzhiyun /* if scaling is disabled, block non-native modes */
1800*4882a593Smuzhiyun if (radeon_encoder->rmx_type == RMX_OFF) {
1801*4882a593Smuzhiyun if ((mode->hdisplay != native_mode->hdisplay) ||
1802*4882a593Smuzhiyun (mode->vdisplay != native_mode->vdisplay))
1803*4882a593Smuzhiyun return MODE_PANEL;
1804*4882a593Smuzhiyun }
1805*4882a593Smuzhiyun }
1806*4882a593Smuzhiyun } else {
1807*4882a593Smuzhiyun if ((radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
1808*4882a593Smuzhiyun (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
1809*4882a593Smuzhiyun return radeon_dp_mode_valid_helper(connector, mode);
1810*4882a593Smuzhiyun } else {
1811*4882a593Smuzhiyun if (ASIC_IS_DCE6(rdev) && drm_detect_hdmi_monitor(radeon_connector_edid(connector))) {
1812*4882a593Smuzhiyun /* HDMI 1.3+ supports max clock of 340 Mhz */
1813*4882a593Smuzhiyun if (mode->clock > 340000)
1814*4882a593Smuzhiyun return MODE_CLOCK_HIGH;
1815*4882a593Smuzhiyun } else {
1816*4882a593Smuzhiyun if (mode->clock > 165000)
1817*4882a593Smuzhiyun return MODE_CLOCK_HIGH;
1818*4882a593Smuzhiyun }
1819*4882a593Smuzhiyun }
1820*4882a593Smuzhiyun }
1821*4882a593Smuzhiyun
1822*4882a593Smuzhiyun return MODE_OK;
1823*4882a593Smuzhiyun }
1824*4882a593Smuzhiyun
1825*4882a593Smuzhiyun static const struct drm_connector_helper_funcs radeon_dp_connector_helper_funcs = {
1826*4882a593Smuzhiyun .get_modes = radeon_dp_get_modes,
1827*4882a593Smuzhiyun .mode_valid = radeon_dp_mode_valid,
1828*4882a593Smuzhiyun .best_encoder = radeon_dvi_encoder,
1829*4882a593Smuzhiyun };
1830*4882a593Smuzhiyun
1831*4882a593Smuzhiyun static const struct drm_connector_funcs radeon_dp_connector_funcs = {
1832*4882a593Smuzhiyun .dpms = drm_helper_connector_dpms,
1833*4882a593Smuzhiyun .detect = radeon_dp_detect,
1834*4882a593Smuzhiyun .fill_modes = drm_helper_probe_single_connector_modes,
1835*4882a593Smuzhiyun .set_property = radeon_connector_set_property,
1836*4882a593Smuzhiyun .early_unregister = radeon_connector_unregister,
1837*4882a593Smuzhiyun .destroy = radeon_connector_destroy,
1838*4882a593Smuzhiyun .force = radeon_dvi_force,
1839*4882a593Smuzhiyun };
1840*4882a593Smuzhiyun
1841*4882a593Smuzhiyun static const struct drm_connector_funcs radeon_edp_connector_funcs = {
1842*4882a593Smuzhiyun .dpms = drm_helper_connector_dpms,
1843*4882a593Smuzhiyun .detect = radeon_dp_detect,
1844*4882a593Smuzhiyun .fill_modes = drm_helper_probe_single_connector_modes,
1845*4882a593Smuzhiyun .set_property = radeon_lvds_set_property,
1846*4882a593Smuzhiyun .early_unregister = radeon_connector_unregister,
1847*4882a593Smuzhiyun .destroy = radeon_connector_destroy,
1848*4882a593Smuzhiyun .force = radeon_dvi_force,
1849*4882a593Smuzhiyun };
1850*4882a593Smuzhiyun
1851*4882a593Smuzhiyun static const struct drm_connector_funcs radeon_lvds_bridge_connector_funcs = {
1852*4882a593Smuzhiyun .dpms = drm_helper_connector_dpms,
1853*4882a593Smuzhiyun .detect = radeon_dp_detect,
1854*4882a593Smuzhiyun .fill_modes = drm_helper_probe_single_connector_modes,
1855*4882a593Smuzhiyun .set_property = radeon_lvds_set_property,
1856*4882a593Smuzhiyun .early_unregister = radeon_connector_unregister,
1857*4882a593Smuzhiyun .destroy = radeon_connector_destroy,
1858*4882a593Smuzhiyun .force = radeon_dvi_force,
1859*4882a593Smuzhiyun };
1860*4882a593Smuzhiyun
1861*4882a593Smuzhiyun void
radeon_add_atom_connector(struct drm_device * dev,uint32_t connector_id,uint32_t supported_device,int connector_type,struct radeon_i2c_bus_rec * i2c_bus,uint32_t igp_lane_info,uint16_t connector_object_id,struct radeon_hpd * hpd,struct radeon_router * router)1862*4882a593Smuzhiyun radeon_add_atom_connector(struct drm_device *dev,
1863*4882a593Smuzhiyun uint32_t connector_id,
1864*4882a593Smuzhiyun uint32_t supported_device,
1865*4882a593Smuzhiyun int connector_type,
1866*4882a593Smuzhiyun struct radeon_i2c_bus_rec *i2c_bus,
1867*4882a593Smuzhiyun uint32_t igp_lane_info,
1868*4882a593Smuzhiyun uint16_t connector_object_id,
1869*4882a593Smuzhiyun struct radeon_hpd *hpd,
1870*4882a593Smuzhiyun struct radeon_router *router)
1871*4882a593Smuzhiyun {
1872*4882a593Smuzhiyun struct radeon_device *rdev = dev->dev_private;
1873*4882a593Smuzhiyun struct drm_connector *connector;
1874*4882a593Smuzhiyun struct radeon_connector *radeon_connector;
1875*4882a593Smuzhiyun struct radeon_connector_atom_dig *radeon_dig_connector;
1876*4882a593Smuzhiyun struct drm_encoder *encoder;
1877*4882a593Smuzhiyun struct radeon_encoder *radeon_encoder;
1878*4882a593Smuzhiyun struct i2c_adapter *ddc = NULL;
1879*4882a593Smuzhiyun uint32_t subpixel_order = SubPixelNone;
1880*4882a593Smuzhiyun bool shared_ddc = false;
1881*4882a593Smuzhiyun bool is_dp_bridge = false;
1882*4882a593Smuzhiyun bool has_aux = false;
1883*4882a593Smuzhiyun
1884*4882a593Smuzhiyun if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1885*4882a593Smuzhiyun return;
1886*4882a593Smuzhiyun
1887*4882a593Smuzhiyun /* if the user selected tv=0 don't try and add the connector */
1888*4882a593Smuzhiyun if (((connector_type == DRM_MODE_CONNECTOR_SVIDEO) ||
1889*4882a593Smuzhiyun (connector_type == DRM_MODE_CONNECTOR_Composite) ||
1890*4882a593Smuzhiyun (connector_type == DRM_MODE_CONNECTOR_9PinDIN)) &&
1891*4882a593Smuzhiyun (radeon_tv == 0))
1892*4882a593Smuzhiyun return;
1893*4882a593Smuzhiyun
1894*4882a593Smuzhiyun /* see if we already added it */
1895*4882a593Smuzhiyun list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1896*4882a593Smuzhiyun radeon_connector = to_radeon_connector(connector);
1897*4882a593Smuzhiyun if (radeon_connector->connector_id == connector_id) {
1898*4882a593Smuzhiyun radeon_connector->devices |= supported_device;
1899*4882a593Smuzhiyun return;
1900*4882a593Smuzhiyun }
1901*4882a593Smuzhiyun if (radeon_connector->ddc_bus && i2c_bus->valid) {
1902*4882a593Smuzhiyun if (radeon_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
1903*4882a593Smuzhiyun radeon_connector->shared_ddc = true;
1904*4882a593Smuzhiyun shared_ddc = true;
1905*4882a593Smuzhiyun }
1906*4882a593Smuzhiyun if (radeon_connector->router_bus && router->ddc_valid &&
1907*4882a593Smuzhiyun (radeon_connector->router.router_id == router->router_id)) {
1908*4882a593Smuzhiyun radeon_connector->shared_ddc = false;
1909*4882a593Smuzhiyun shared_ddc = false;
1910*4882a593Smuzhiyun }
1911*4882a593Smuzhiyun }
1912*4882a593Smuzhiyun }
1913*4882a593Smuzhiyun
1914*4882a593Smuzhiyun /* check if it's a dp bridge */
1915*4882a593Smuzhiyun list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1916*4882a593Smuzhiyun radeon_encoder = to_radeon_encoder(encoder);
1917*4882a593Smuzhiyun if (radeon_encoder->devices & supported_device) {
1918*4882a593Smuzhiyun switch (radeon_encoder->encoder_id) {
1919*4882a593Smuzhiyun case ENCODER_OBJECT_ID_TRAVIS:
1920*4882a593Smuzhiyun case ENCODER_OBJECT_ID_NUTMEG:
1921*4882a593Smuzhiyun is_dp_bridge = true;
1922*4882a593Smuzhiyun break;
1923*4882a593Smuzhiyun default:
1924*4882a593Smuzhiyun break;
1925*4882a593Smuzhiyun }
1926*4882a593Smuzhiyun }
1927*4882a593Smuzhiyun }
1928*4882a593Smuzhiyun
1929*4882a593Smuzhiyun radeon_connector = kzalloc(sizeof(struct radeon_connector), GFP_KERNEL);
1930*4882a593Smuzhiyun if (!radeon_connector)
1931*4882a593Smuzhiyun return;
1932*4882a593Smuzhiyun
1933*4882a593Smuzhiyun connector = &radeon_connector->base;
1934*4882a593Smuzhiyun
1935*4882a593Smuzhiyun radeon_connector->connector_id = connector_id;
1936*4882a593Smuzhiyun radeon_connector->devices = supported_device;
1937*4882a593Smuzhiyun radeon_connector->shared_ddc = shared_ddc;
1938*4882a593Smuzhiyun radeon_connector->connector_object_id = connector_object_id;
1939*4882a593Smuzhiyun radeon_connector->hpd = *hpd;
1940*4882a593Smuzhiyun
1941*4882a593Smuzhiyun radeon_connector->router = *router;
1942*4882a593Smuzhiyun if (router->ddc_valid || router->cd_valid) {
1943*4882a593Smuzhiyun radeon_connector->router_bus = radeon_i2c_lookup(rdev, &router->i2c_info);
1944*4882a593Smuzhiyun if (!radeon_connector->router_bus)
1945*4882a593Smuzhiyun DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
1946*4882a593Smuzhiyun }
1947*4882a593Smuzhiyun
1948*4882a593Smuzhiyun if (is_dp_bridge) {
1949*4882a593Smuzhiyun radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
1950*4882a593Smuzhiyun if (!radeon_dig_connector)
1951*4882a593Smuzhiyun goto failed;
1952*4882a593Smuzhiyun radeon_dig_connector->igp_lane_info = igp_lane_info;
1953*4882a593Smuzhiyun radeon_connector->con_priv = radeon_dig_connector;
1954*4882a593Smuzhiyun if (i2c_bus->valid) {
1955*4882a593Smuzhiyun radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1956*4882a593Smuzhiyun if (radeon_connector->ddc_bus) {
1957*4882a593Smuzhiyun has_aux = true;
1958*4882a593Smuzhiyun ddc = &radeon_connector->ddc_bus->adapter;
1959*4882a593Smuzhiyun } else {
1960*4882a593Smuzhiyun DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1961*4882a593Smuzhiyun }
1962*4882a593Smuzhiyun }
1963*4882a593Smuzhiyun switch (connector_type) {
1964*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_VGA:
1965*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_DVIA:
1966*4882a593Smuzhiyun default:
1967*4882a593Smuzhiyun drm_connector_init_with_ddc(dev, &radeon_connector->base,
1968*4882a593Smuzhiyun &radeon_dp_connector_funcs,
1969*4882a593Smuzhiyun connector_type,
1970*4882a593Smuzhiyun ddc);
1971*4882a593Smuzhiyun drm_connector_helper_add(&radeon_connector->base,
1972*4882a593Smuzhiyun &radeon_dp_connector_helper_funcs);
1973*4882a593Smuzhiyun connector->interlace_allowed = true;
1974*4882a593Smuzhiyun connector->doublescan_allowed = true;
1975*4882a593Smuzhiyun radeon_connector->dac_load_detect = true;
1976*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
1977*4882a593Smuzhiyun rdev->mode_info.load_detect_property,
1978*4882a593Smuzhiyun 1);
1979*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
1980*4882a593Smuzhiyun dev->mode_config.scaling_mode_property,
1981*4882a593Smuzhiyun DRM_MODE_SCALE_NONE);
1982*4882a593Smuzhiyun if (ASIC_IS_DCE5(rdev))
1983*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
1984*4882a593Smuzhiyun rdev->mode_info.output_csc_property,
1985*4882a593Smuzhiyun RADEON_OUTPUT_CSC_BYPASS);
1986*4882a593Smuzhiyun break;
1987*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_DVII:
1988*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_DVID:
1989*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_HDMIA:
1990*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_HDMIB:
1991*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_DisplayPort:
1992*4882a593Smuzhiyun drm_connector_init_with_ddc(dev, &radeon_connector->base,
1993*4882a593Smuzhiyun &radeon_dp_connector_funcs,
1994*4882a593Smuzhiyun connector_type,
1995*4882a593Smuzhiyun ddc);
1996*4882a593Smuzhiyun drm_connector_helper_add(&radeon_connector->base,
1997*4882a593Smuzhiyun &radeon_dp_connector_helper_funcs);
1998*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
1999*4882a593Smuzhiyun rdev->mode_info.underscan_property,
2000*4882a593Smuzhiyun UNDERSCAN_OFF);
2001*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2002*4882a593Smuzhiyun rdev->mode_info.underscan_hborder_property,
2003*4882a593Smuzhiyun 0);
2004*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2005*4882a593Smuzhiyun rdev->mode_info.underscan_vborder_property,
2006*4882a593Smuzhiyun 0);
2007*4882a593Smuzhiyun
2008*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2009*4882a593Smuzhiyun dev->mode_config.scaling_mode_property,
2010*4882a593Smuzhiyun DRM_MODE_SCALE_NONE);
2011*4882a593Smuzhiyun
2012*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2013*4882a593Smuzhiyun rdev->mode_info.dither_property,
2014*4882a593Smuzhiyun RADEON_FMT_DITHER_DISABLE);
2015*4882a593Smuzhiyun
2016*4882a593Smuzhiyun if (radeon_audio != 0) {
2017*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2018*4882a593Smuzhiyun rdev->mode_info.audio_property,
2019*4882a593Smuzhiyun RADEON_AUDIO_AUTO);
2020*4882a593Smuzhiyun radeon_connector->audio = RADEON_AUDIO_AUTO;
2021*4882a593Smuzhiyun }
2022*4882a593Smuzhiyun if (ASIC_IS_DCE5(rdev))
2023*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2024*4882a593Smuzhiyun rdev->mode_info.output_csc_property,
2025*4882a593Smuzhiyun RADEON_OUTPUT_CSC_BYPASS);
2026*4882a593Smuzhiyun
2027*4882a593Smuzhiyun subpixel_order = SubPixelHorizontalRGB;
2028*4882a593Smuzhiyun connector->interlace_allowed = true;
2029*4882a593Smuzhiyun if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
2030*4882a593Smuzhiyun connector->doublescan_allowed = true;
2031*4882a593Smuzhiyun else
2032*4882a593Smuzhiyun connector->doublescan_allowed = false;
2033*4882a593Smuzhiyun if (connector_type == DRM_MODE_CONNECTOR_DVII) {
2034*4882a593Smuzhiyun radeon_connector->dac_load_detect = true;
2035*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2036*4882a593Smuzhiyun rdev->mode_info.load_detect_property,
2037*4882a593Smuzhiyun 1);
2038*4882a593Smuzhiyun }
2039*4882a593Smuzhiyun break;
2040*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_LVDS:
2041*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_eDP:
2042*4882a593Smuzhiyun drm_connector_init_with_ddc(dev, &radeon_connector->base,
2043*4882a593Smuzhiyun &radeon_lvds_bridge_connector_funcs,
2044*4882a593Smuzhiyun connector_type,
2045*4882a593Smuzhiyun ddc);
2046*4882a593Smuzhiyun drm_connector_helper_add(&radeon_connector->base,
2047*4882a593Smuzhiyun &radeon_dp_connector_helper_funcs);
2048*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2049*4882a593Smuzhiyun dev->mode_config.scaling_mode_property,
2050*4882a593Smuzhiyun DRM_MODE_SCALE_FULLSCREEN);
2051*4882a593Smuzhiyun subpixel_order = SubPixelHorizontalRGB;
2052*4882a593Smuzhiyun connector->interlace_allowed = false;
2053*4882a593Smuzhiyun connector->doublescan_allowed = false;
2054*4882a593Smuzhiyun break;
2055*4882a593Smuzhiyun }
2056*4882a593Smuzhiyun } else {
2057*4882a593Smuzhiyun switch (connector_type) {
2058*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_VGA:
2059*4882a593Smuzhiyun if (i2c_bus->valid) {
2060*4882a593Smuzhiyun radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
2061*4882a593Smuzhiyun if (!radeon_connector->ddc_bus)
2062*4882a593Smuzhiyun DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
2063*4882a593Smuzhiyun else
2064*4882a593Smuzhiyun ddc = &radeon_connector->ddc_bus->adapter;
2065*4882a593Smuzhiyun }
2066*4882a593Smuzhiyun drm_connector_init_with_ddc(dev, &radeon_connector->base,
2067*4882a593Smuzhiyun &radeon_vga_connector_funcs,
2068*4882a593Smuzhiyun connector_type,
2069*4882a593Smuzhiyun ddc);
2070*4882a593Smuzhiyun drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
2071*4882a593Smuzhiyun radeon_connector->dac_load_detect = true;
2072*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2073*4882a593Smuzhiyun rdev->mode_info.load_detect_property,
2074*4882a593Smuzhiyun 1);
2075*4882a593Smuzhiyun if (ASIC_IS_AVIVO(rdev))
2076*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2077*4882a593Smuzhiyun dev->mode_config.scaling_mode_property,
2078*4882a593Smuzhiyun DRM_MODE_SCALE_NONE);
2079*4882a593Smuzhiyun if (ASIC_IS_DCE5(rdev))
2080*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2081*4882a593Smuzhiyun rdev->mode_info.output_csc_property,
2082*4882a593Smuzhiyun RADEON_OUTPUT_CSC_BYPASS);
2083*4882a593Smuzhiyun /* no HPD on analog connectors */
2084*4882a593Smuzhiyun radeon_connector->hpd.hpd = RADEON_HPD_NONE;
2085*4882a593Smuzhiyun connector->interlace_allowed = true;
2086*4882a593Smuzhiyun connector->doublescan_allowed = true;
2087*4882a593Smuzhiyun break;
2088*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_DVIA:
2089*4882a593Smuzhiyun if (i2c_bus->valid) {
2090*4882a593Smuzhiyun radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
2091*4882a593Smuzhiyun if (!radeon_connector->ddc_bus)
2092*4882a593Smuzhiyun DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
2093*4882a593Smuzhiyun else
2094*4882a593Smuzhiyun ddc = &radeon_connector->ddc_bus->adapter;
2095*4882a593Smuzhiyun }
2096*4882a593Smuzhiyun drm_connector_init_with_ddc(dev, &radeon_connector->base,
2097*4882a593Smuzhiyun &radeon_vga_connector_funcs,
2098*4882a593Smuzhiyun connector_type,
2099*4882a593Smuzhiyun ddc);
2100*4882a593Smuzhiyun drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
2101*4882a593Smuzhiyun radeon_connector->dac_load_detect = true;
2102*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2103*4882a593Smuzhiyun rdev->mode_info.load_detect_property,
2104*4882a593Smuzhiyun 1);
2105*4882a593Smuzhiyun if (ASIC_IS_AVIVO(rdev))
2106*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2107*4882a593Smuzhiyun dev->mode_config.scaling_mode_property,
2108*4882a593Smuzhiyun DRM_MODE_SCALE_NONE);
2109*4882a593Smuzhiyun if (ASIC_IS_DCE5(rdev))
2110*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2111*4882a593Smuzhiyun rdev->mode_info.output_csc_property,
2112*4882a593Smuzhiyun RADEON_OUTPUT_CSC_BYPASS);
2113*4882a593Smuzhiyun /* no HPD on analog connectors */
2114*4882a593Smuzhiyun radeon_connector->hpd.hpd = RADEON_HPD_NONE;
2115*4882a593Smuzhiyun connector->interlace_allowed = true;
2116*4882a593Smuzhiyun connector->doublescan_allowed = true;
2117*4882a593Smuzhiyun break;
2118*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_DVII:
2119*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_DVID:
2120*4882a593Smuzhiyun radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
2121*4882a593Smuzhiyun if (!radeon_dig_connector)
2122*4882a593Smuzhiyun goto failed;
2123*4882a593Smuzhiyun radeon_dig_connector->igp_lane_info = igp_lane_info;
2124*4882a593Smuzhiyun radeon_connector->con_priv = radeon_dig_connector;
2125*4882a593Smuzhiyun if (i2c_bus->valid) {
2126*4882a593Smuzhiyun radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
2127*4882a593Smuzhiyun if (!radeon_connector->ddc_bus)
2128*4882a593Smuzhiyun DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
2129*4882a593Smuzhiyun else
2130*4882a593Smuzhiyun ddc = &radeon_connector->ddc_bus->adapter;
2131*4882a593Smuzhiyun }
2132*4882a593Smuzhiyun drm_connector_init_with_ddc(dev, &radeon_connector->base,
2133*4882a593Smuzhiyun &radeon_dvi_connector_funcs,
2134*4882a593Smuzhiyun connector_type,
2135*4882a593Smuzhiyun ddc);
2136*4882a593Smuzhiyun drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs);
2137*4882a593Smuzhiyun subpixel_order = SubPixelHorizontalRGB;
2138*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2139*4882a593Smuzhiyun rdev->mode_info.coherent_mode_property,
2140*4882a593Smuzhiyun 1);
2141*4882a593Smuzhiyun if (ASIC_IS_AVIVO(rdev)) {
2142*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2143*4882a593Smuzhiyun rdev->mode_info.underscan_property,
2144*4882a593Smuzhiyun UNDERSCAN_OFF);
2145*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2146*4882a593Smuzhiyun rdev->mode_info.underscan_hborder_property,
2147*4882a593Smuzhiyun 0);
2148*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2149*4882a593Smuzhiyun rdev->mode_info.underscan_vborder_property,
2150*4882a593Smuzhiyun 0);
2151*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2152*4882a593Smuzhiyun rdev->mode_info.dither_property,
2153*4882a593Smuzhiyun RADEON_FMT_DITHER_DISABLE);
2154*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2155*4882a593Smuzhiyun dev->mode_config.scaling_mode_property,
2156*4882a593Smuzhiyun DRM_MODE_SCALE_NONE);
2157*4882a593Smuzhiyun }
2158*4882a593Smuzhiyun if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) {
2159*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2160*4882a593Smuzhiyun rdev->mode_info.audio_property,
2161*4882a593Smuzhiyun RADEON_AUDIO_AUTO);
2162*4882a593Smuzhiyun radeon_connector->audio = RADEON_AUDIO_AUTO;
2163*4882a593Smuzhiyun }
2164*4882a593Smuzhiyun if (connector_type == DRM_MODE_CONNECTOR_DVII) {
2165*4882a593Smuzhiyun radeon_connector->dac_load_detect = true;
2166*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2167*4882a593Smuzhiyun rdev->mode_info.load_detect_property,
2168*4882a593Smuzhiyun 1);
2169*4882a593Smuzhiyun }
2170*4882a593Smuzhiyun if (ASIC_IS_DCE5(rdev))
2171*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2172*4882a593Smuzhiyun rdev->mode_info.output_csc_property,
2173*4882a593Smuzhiyun RADEON_OUTPUT_CSC_BYPASS);
2174*4882a593Smuzhiyun connector->interlace_allowed = true;
2175*4882a593Smuzhiyun if (connector_type == DRM_MODE_CONNECTOR_DVII)
2176*4882a593Smuzhiyun connector->doublescan_allowed = true;
2177*4882a593Smuzhiyun else
2178*4882a593Smuzhiyun connector->doublescan_allowed = false;
2179*4882a593Smuzhiyun break;
2180*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_HDMIA:
2181*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_HDMIB:
2182*4882a593Smuzhiyun radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
2183*4882a593Smuzhiyun if (!radeon_dig_connector)
2184*4882a593Smuzhiyun goto failed;
2185*4882a593Smuzhiyun radeon_dig_connector->igp_lane_info = igp_lane_info;
2186*4882a593Smuzhiyun radeon_connector->con_priv = radeon_dig_connector;
2187*4882a593Smuzhiyun if (i2c_bus->valid) {
2188*4882a593Smuzhiyun radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
2189*4882a593Smuzhiyun if (!radeon_connector->ddc_bus)
2190*4882a593Smuzhiyun DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
2191*4882a593Smuzhiyun else
2192*4882a593Smuzhiyun ddc = &radeon_connector->ddc_bus->adapter;
2193*4882a593Smuzhiyun }
2194*4882a593Smuzhiyun drm_connector_init_with_ddc(dev, &radeon_connector->base,
2195*4882a593Smuzhiyun &radeon_dvi_connector_funcs,
2196*4882a593Smuzhiyun connector_type,
2197*4882a593Smuzhiyun ddc);
2198*4882a593Smuzhiyun drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs);
2199*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2200*4882a593Smuzhiyun rdev->mode_info.coherent_mode_property,
2201*4882a593Smuzhiyun 1);
2202*4882a593Smuzhiyun if (ASIC_IS_AVIVO(rdev)) {
2203*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2204*4882a593Smuzhiyun rdev->mode_info.underscan_property,
2205*4882a593Smuzhiyun UNDERSCAN_OFF);
2206*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2207*4882a593Smuzhiyun rdev->mode_info.underscan_hborder_property,
2208*4882a593Smuzhiyun 0);
2209*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2210*4882a593Smuzhiyun rdev->mode_info.underscan_vborder_property,
2211*4882a593Smuzhiyun 0);
2212*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2213*4882a593Smuzhiyun rdev->mode_info.dither_property,
2214*4882a593Smuzhiyun RADEON_FMT_DITHER_DISABLE);
2215*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2216*4882a593Smuzhiyun dev->mode_config.scaling_mode_property,
2217*4882a593Smuzhiyun DRM_MODE_SCALE_NONE);
2218*4882a593Smuzhiyun }
2219*4882a593Smuzhiyun if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) {
2220*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2221*4882a593Smuzhiyun rdev->mode_info.audio_property,
2222*4882a593Smuzhiyun RADEON_AUDIO_AUTO);
2223*4882a593Smuzhiyun radeon_connector->audio = RADEON_AUDIO_AUTO;
2224*4882a593Smuzhiyun }
2225*4882a593Smuzhiyun if (ASIC_IS_DCE5(rdev))
2226*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2227*4882a593Smuzhiyun rdev->mode_info.output_csc_property,
2228*4882a593Smuzhiyun RADEON_OUTPUT_CSC_BYPASS);
2229*4882a593Smuzhiyun subpixel_order = SubPixelHorizontalRGB;
2230*4882a593Smuzhiyun connector->interlace_allowed = true;
2231*4882a593Smuzhiyun if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
2232*4882a593Smuzhiyun connector->doublescan_allowed = true;
2233*4882a593Smuzhiyun else
2234*4882a593Smuzhiyun connector->doublescan_allowed = false;
2235*4882a593Smuzhiyun break;
2236*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_DisplayPort:
2237*4882a593Smuzhiyun radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
2238*4882a593Smuzhiyun if (!radeon_dig_connector)
2239*4882a593Smuzhiyun goto failed;
2240*4882a593Smuzhiyun radeon_dig_connector->igp_lane_info = igp_lane_info;
2241*4882a593Smuzhiyun radeon_connector->con_priv = radeon_dig_connector;
2242*4882a593Smuzhiyun if (i2c_bus->valid) {
2243*4882a593Smuzhiyun radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
2244*4882a593Smuzhiyun if (radeon_connector->ddc_bus) {
2245*4882a593Smuzhiyun has_aux = true;
2246*4882a593Smuzhiyun ddc = &radeon_connector->ddc_bus->adapter;
2247*4882a593Smuzhiyun } else {
2248*4882a593Smuzhiyun DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
2249*4882a593Smuzhiyun }
2250*4882a593Smuzhiyun }
2251*4882a593Smuzhiyun drm_connector_init_with_ddc(dev, &radeon_connector->base,
2252*4882a593Smuzhiyun &radeon_dp_connector_funcs,
2253*4882a593Smuzhiyun connector_type,
2254*4882a593Smuzhiyun ddc);
2255*4882a593Smuzhiyun drm_connector_helper_add(&radeon_connector->base, &radeon_dp_connector_helper_funcs);
2256*4882a593Smuzhiyun subpixel_order = SubPixelHorizontalRGB;
2257*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2258*4882a593Smuzhiyun rdev->mode_info.coherent_mode_property,
2259*4882a593Smuzhiyun 1);
2260*4882a593Smuzhiyun if (ASIC_IS_AVIVO(rdev)) {
2261*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2262*4882a593Smuzhiyun rdev->mode_info.underscan_property,
2263*4882a593Smuzhiyun UNDERSCAN_OFF);
2264*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2265*4882a593Smuzhiyun rdev->mode_info.underscan_hborder_property,
2266*4882a593Smuzhiyun 0);
2267*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2268*4882a593Smuzhiyun rdev->mode_info.underscan_vborder_property,
2269*4882a593Smuzhiyun 0);
2270*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2271*4882a593Smuzhiyun rdev->mode_info.dither_property,
2272*4882a593Smuzhiyun RADEON_FMT_DITHER_DISABLE);
2273*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2274*4882a593Smuzhiyun dev->mode_config.scaling_mode_property,
2275*4882a593Smuzhiyun DRM_MODE_SCALE_NONE);
2276*4882a593Smuzhiyun }
2277*4882a593Smuzhiyun if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) {
2278*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2279*4882a593Smuzhiyun rdev->mode_info.audio_property,
2280*4882a593Smuzhiyun RADEON_AUDIO_AUTO);
2281*4882a593Smuzhiyun radeon_connector->audio = RADEON_AUDIO_AUTO;
2282*4882a593Smuzhiyun }
2283*4882a593Smuzhiyun if (ASIC_IS_DCE5(rdev))
2284*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2285*4882a593Smuzhiyun rdev->mode_info.output_csc_property,
2286*4882a593Smuzhiyun RADEON_OUTPUT_CSC_BYPASS);
2287*4882a593Smuzhiyun connector->interlace_allowed = true;
2288*4882a593Smuzhiyun /* in theory with a DP to VGA converter... */
2289*4882a593Smuzhiyun connector->doublescan_allowed = false;
2290*4882a593Smuzhiyun break;
2291*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_eDP:
2292*4882a593Smuzhiyun radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
2293*4882a593Smuzhiyun if (!radeon_dig_connector)
2294*4882a593Smuzhiyun goto failed;
2295*4882a593Smuzhiyun radeon_dig_connector->igp_lane_info = igp_lane_info;
2296*4882a593Smuzhiyun radeon_connector->con_priv = radeon_dig_connector;
2297*4882a593Smuzhiyun if (i2c_bus->valid) {
2298*4882a593Smuzhiyun radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
2299*4882a593Smuzhiyun if (radeon_connector->ddc_bus) {
2300*4882a593Smuzhiyun has_aux = true;
2301*4882a593Smuzhiyun ddc = &radeon_connector->ddc_bus->adapter;
2302*4882a593Smuzhiyun } else {
2303*4882a593Smuzhiyun DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
2304*4882a593Smuzhiyun }
2305*4882a593Smuzhiyun }
2306*4882a593Smuzhiyun drm_connector_init_with_ddc(dev, &radeon_connector->base,
2307*4882a593Smuzhiyun &radeon_edp_connector_funcs,
2308*4882a593Smuzhiyun connector_type,
2309*4882a593Smuzhiyun ddc);
2310*4882a593Smuzhiyun drm_connector_helper_add(&radeon_connector->base, &radeon_dp_connector_helper_funcs);
2311*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2312*4882a593Smuzhiyun dev->mode_config.scaling_mode_property,
2313*4882a593Smuzhiyun DRM_MODE_SCALE_FULLSCREEN);
2314*4882a593Smuzhiyun subpixel_order = SubPixelHorizontalRGB;
2315*4882a593Smuzhiyun connector->interlace_allowed = false;
2316*4882a593Smuzhiyun connector->doublescan_allowed = false;
2317*4882a593Smuzhiyun break;
2318*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_SVIDEO:
2319*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_Composite:
2320*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_9PinDIN:
2321*4882a593Smuzhiyun drm_connector_init_with_ddc(dev, &radeon_connector->base,
2322*4882a593Smuzhiyun &radeon_tv_connector_funcs,
2323*4882a593Smuzhiyun connector_type,
2324*4882a593Smuzhiyun ddc);
2325*4882a593Smuzhiyun drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs);
2326*4882a593Smuzhiyun radeon_connector->dac_load_detect = true;
2327*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2328*4882a593Smuzhiyun rdev->mode_info.load_detect_property,
2329*4882a593Smuzhiyun 1);
2330*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2331*4882a593Smuzhiyun rdev->mode_info.tv_std_property,
2332*4882a593Smuzhiyun radeon_atombios_get_tv_info(rdev));
2333*4882a593Smuzhiyun /* no HPD on analog connectors */
2334*4882a593Smuzhiyun radeon_connector->hpd.hpd = RADEON_HPD_NONE;
2335*4882a593Smuzhiyun connector->interlace_allowed = false;
2336*4882a593Smuzhiyun connector->doublescan_allowed = false;
2337*4882a593Smuzhiyun break;
2338*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_LVDS:
2339*4882a593Smuzhiyun radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
2340*4882a593Smuzhiyun if (!radeon_dig_connector)
2341*4882a593Smuzhiyun goto failed;
2342*4882a593Smuzhiyun radeon_dig_connector->igp_lane_info = igp_lane_info;
2343*4882a593Smuzhiyun radeon_connector->con_priv = radeon_dig_connector;
2344*4882a593Smuzhiyun if (i2c_bus->valid) {
2345*4882a593Smuzhiyun radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
2346*4882a593Smuzhiyun if (!radeon_connector->ddc_bus)
2347*4882a593Smuzhiyun DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
2348*4882a593Smuzhiyun else
2349*4882a593Smuzhiyun ddc = &radeon_connector->ddc_bus->adapter;
2350*4882a593Smuzhiyun }
2351*4882a593Smuzhiyun drm_connector_init_with_ddc(dev, &radeon_connector->base,
2352*4882a593Smuzhiyun &radeon_lvds_connector_funcs,
2353*4882a593Smuzhiyun connector_type,
2354*4882a593Smuzhiyun ddc);
2355*4882a593Smuzhiyun drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs);
2356*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2357*4882a593Smuzhiyun dev->mode_config.scaling_mode_property,
2358*4882a593Smuzhiyun DRM_MODE_SCALE_FULLSCREEN);
2359*4882a593Smuzhiyun subpixel_order = SubPixelHorizontalRGB;
2360*4882a593Smuzhiyun connector->interlace_allowed = false;
2361*4882a593Smuzhiyun connector->doublescan_allowed = false;
2362*4882a593Smuzhiyun break;
2363*4882a593Smuzhiyun }
2364*4882a593Smuzhiyun }
2365*4882a593Smuzhiyun
2366*4882a593Smuzhiyun if (radeon_connector->hpd.hpd == RADEON_HPD_NONE) {
2367*4882a593Smuzhiyun if (i2c_bus->valid) {
2368*4882a593Smuzhiyun connector->polled = DRM_CONNECTOR_POLL_CONNECT |
2369*4882a593Smuzhiyun DRM_CONNECTOR_POLL_DISCONNECT;
2370*4882a593Smuzhiyun }
2371*4882a593Smuzhiyun } else
2372*4882a593Smuzhiyun connector->polled = DRM_CONNECTOR_POLL_HPD;
2373*4882a593Smuzhiyun
2374*4882a593Smuzhiyun connector->display_info.subpixel_order = subpixel_order;
2375*4882a593Smuzhiyun drm_connector_register(connector);
2376*4882a593Smuzhiyun
2377*4882a593Smuzhiyun if (has_aux)
2378*4882a593Smuzhiyun radeon_dp_aux_init(radeon_connector);
2379*4882a593Smuzhiyun
2380*4882a593Smuzhiyun return;
2381*4882a593Smuzhiyun
2382*4882a593Smuzhiyun failed:
2383*4882a593Smuzhiyun drm_connector_cleanup(connector);
2384*4882a593Smuzhiyun kfree(connector);
2385*4882a593Smuzhiyun }
2386*4882a593Smuzhiyun
2387*4882a593Smuzhiyun void
radeon_add_legacy_connector(struct drm_device * dev,uint32_t connector_id,uint32_t supported_device,int connector_type,struct radeon_i2c_bus_rec * i2c_bus,uint16_t connector_object_id,struct radeon_hpd * hpd)2388*4882a593Smuzhiyun radeon_add_legacy_connector(struct drm_device *dev,
2389*4882a593Smuzhiyun uint32_t connector_id,
2390*4882a593Smuzhiyun uint32_t supported_device,
2391*4882a593Smuzhiyun int connector_type,
2392*4882a593Smuzhiyun struct radeon_i2c_bus_rec *i2c_bus,
2393*4882a593Smuzhiyun uint16_t connector_object_id,
2394*4882a593Smuzhiyun struct radeon_hpd *hpd)
2395*4882a593Smuzhiyun {
2396*4882a593Smuzhiyun struct radeon_device *rdev = dev->dev_private;
2397*4882a593Smuzhiyun struct drm_connector *connector;
2398*4882a593Smuzhiyun struct radeon_connector *radeon_connector;
2399*4882a593Smuzhiyun struct i2c_adapter *ddc = NULL;
2400*4882a593Smuzhiyun uint32_t subpixel_order = SubPixelNone;
2401*4882a593Smuzhiyun
2402*4882a593Smuzhiyun if (connector_type == DRM_MODE_CONNECTOR_Unknown)
2403*4882a593Smuzhiyun return;
2404*4882a593Smuzhiyun
2405*4882a593Smuzhiyun /* if the user selected tv=0 don't try and add the connector */
2406*4882a593Smuzhiyun if (((connector_type == DRM_MODE_CONNECTOR_SVIDEO) ||
2407*4882a593Smuzhiyun (connector_type == DRM_MODE_CONNECTOR_Composite) ||
2408*4882a593Smuzhiyun (connector_type == DRM_MODE_CONNECTOR_9PinDIN)) &&
2409*4882a593Smuzhiyun (radeon_tv == 0))
2410*4882a593Smuzhiyun return;
2411*4882a593Smuzhiyun
2412*4882a593Smuzhiyun /* see if we already added it */
2413*4882a593Smuzhiyun list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2414*4882a593Smuzhiyun radeon_connector = to_radeon_connector(connector);
2415*4882a593Smuzhiyun if (radeon_connector->connector_id == connector_id) {
2416*4882a593Smuzhiyun radeon_connector->devices |= supported_device;
2417*4882a593Smuzhiyun return;
2418*4882a593Smuzhiyun }
2419*4882a593Smuzhiyun }
2420*4882a593Smuzhiyun
2421*4882a593Smuzhiyun radeon_connector = kzalloc(sizeof(struct radeon_connector), GFP_KERNEL);
2422*4882a593Smuzhiyun if (!radeon_connector)
2423*4882a593Smuzhiyun return;
2424*4882a593Smuzhiyun
2425*4882a593Smuzhiyun connector = &radeon_connector->base;
2426*4882a593Smuzhiyun
2427*4882a593Smuzhiyun radeon_connector->connector_id = connector_id;
2428*4882a593Smuzhiyun radeon_connector->devices = supported_device;
2429*4882a593Smuzhiyun radeon_connector->connector_object_id = connector_object_id;
2430*4882a593Smuzhiyun radeon_connector->hpd = *hpd;
2431*4882a593Smuzhiyun
2432*4882a593Smuzhiyun switch (connector_type) {
2433*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_VGA:
2434*4882a593Smuzhiyun if (i2c_bus->valid) {
2435*4882a593Smuzhiyun radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
2436*4882a593Smuzhiyun if (!radeon_connector->ddc_bus)
2437*4882a593Smuzhiyun DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
2438*4882a593Smuzhiyun else
2439*4882a593Smuzhiyun ddc = &radeon_connector->ddc_bus->adapter;
2440*4882a593Smuzhiyun }
2441*4882a593Smuzhiyun drm_connector_init_with_ddc(dev, &radeon_connector->base,
2442*4882a593Smuzhiyun &radeon_vga_connector_funcs,
2443*4882a593Smuzhiyun connector_type,
2444*4882a593Smuzhiyun ddc);
2445*4882a593Smuzhiyun drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
2446*4882a593Smuzhiyun radeon_connector->dac_load_detect = true;
2447*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2448*4882a593Smuzhiyun rdev->mode_info.load_detect_property,
2449*4882a593Smuzhiyun 1);
2450*4882a593Smuzhiyun /* no HPD on analog connectors */
2451*4882a593Smuzhiyun radeon_connector->hpd.hpd = RADEON_HPD_NONE;
2452*4882a593Smuzhiyun connector->interlace_allowed = true;
2453*4882a593Smuzhiyun connector->doublescan_allowed = true;
2454*4882a593Smuzhiyun break;
2455*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_DVIA:
2456*4882a593Smuzhiyun if (i2c_bus->valid) {
2457*4882a593Smuzhiyun radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
2458*4882a593Smuzhiyun if (!radeon_connector->ddc_bus)
2459*4882a593Smuzhiyun DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
2460*4882a593Smuzhiyun else
2461*4882a593Smuzhiyun ddc = &radeon_connector->ddc_bus->adapter;
2462*4882a593Smuzhiyun }
2463*4882a593Smuzhiyun drm_connector_init_with_ddc(dev, &radeon_connector->base,
2464*4882a593Smuzhiyun &radeon_vga_connector_funcs,
2465*4882a593Smuzhiyun connector_type,
2466*4882a593Smuzhiyun ddc);
2467*4882a593Smuzhiyun drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
2468*4882a593Smuzhiyun radeon_connector->dac_load_detect = true;
2469*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2470*4882a593Smuzhiyun rdev->mode_info.load_detect_property,
2471*4882a593Smuzhiyun 1);
2472*4882a593Smuzhiyun /* no HPD on analog connectors */
2473*4882a593Smuzhiyun radeon_connector->hpd.hpd = RADEON_HPD_NONE;
2474*4882a593Smuzhiyun connector->interlace_allowed = true;
2475*4882a593Smuzhiyun connector->doublescan_allowed = true;
2476*4882a593Smuzhiyun break;
2477*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_DVII:
2478*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_DVID:
2479*4882a593Smuzhiyun if (i2c_bus->valid) {
2480*4882a593Smuzhiyun radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
2481*4882a593Smuzhiyun if (!radeon_connector->ddc_bus)
2482*4882a593Smuzhiyun DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
2483*4882a593Smuzhiyun else
2484*4882a593Smuzhiyun ddc = &radeon_connector->ddc_bus->adapter;
2485*4882a593Smuzhiyun }
2486*4882a593Smuzhiyun drm_connector_init_with_ddc(dev, &radeon_connector->base,
2487*4882a593Smuzhiyun &radeon_dvi_connector_funcs,
2488*4882a593Smuzhiyun connector_type,
2489*4882a593Smuzhiyun ddc);
2490*4882a593Smuzhiyun drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs);
2491*4882a593Smuzhiyun if (connector_type == DRM_MODE_CONNECTOR_DVII) {
2492*4882a593Smuzhiyun radeon_connector->dac_load_detect = true;
2493*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2494*4882a593Smuzhiyun rdev->mode_info.load_detect_property,
2495*4882a593Smuzhiyun 1);
2496*4882a593Smuzhiyun }
2497*4882a593Smuzhiyun subpixel_order = SubPixelHorizontalRGB;
2498*4882a593Smuzhiyun connector->interlace_allowed = true;
2499*4882a593Smuzhiyun if (connector_type == DRM_MODE_CONNECTOR_DVII)
2500*4882a593Smuzhiyun connector->doublescan_allowed = true;
2501*4882a593Smuzhiyun else
2502*4882a593Smuzhiyun connector->doublescan_allowed = false;
2503*4882a593Smuzhiyun break;
2504*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_SVIDEO:
2505*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_Composite:
2506*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_9PinDIN:
2507*4882a593Smuzhiyun drm_connector_init_with_ddc(dev, &radeon_connector->base,
2508*4882a593Smuzhiyun &radeon_tv_connector_funcs,
2509*4882a593Smuzhiyun connector_type,
2510*4882a593Smuzhiyun ddc);
2511*4882a593Smuzhiyun drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs);
2512*4882a593Smuzhiyun radeon_connector->dac_load_detect = true;
2513*4882a593Smuzhiyun /* RS400,RC410,RS480 chipset seems to report a lot
2514*4882a593Smuzhiyun * of false positive on load detect, we haven't yet
2515*4882a593Smuzhiyun * found a way to make load detect reliable on those
2516*4882a593Smuzhiyun * chipset, thus just disable it for TV.
2517*4882a593Smuzhiyun */
2518*4882a593Smuzhiyun if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480)
2519*4882a593Smuzhiyun radeon_connector->dac_load_detect = false;
2520*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2521*4882a593Smuzhiyun rdev->mode_info.load_detect_property,
2522*4882a593Smuzhiyun radeon_connector->dac_load_detect);
2523*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2524*4882a593Smuzhiyun rdev->mode_info.tv_std_property,
2525*4882a593Smuzhiyun radeon_combios_get_tv_info(rdev));
2526*4882a593Smuzhiyun /* no HPD on analog connectors */
2527*4882a593Smuzhiyun radeon_connector->hpd.hpd = RADEON_HPD_NONE;
2528*4882a593Smuzhiyun connector->interlace_allowed = false;
2529*4882a593Smuzhiyun connector->doublescan_allowed = false;
2530*4882a593Smuzhiyun break;
2531*4882a593Smuzhiyun case DRM_MODE_CONNECTOR_LVDS:
2532*4882a593Smuzhiyun if (i2c_bus->valid) {
2533*4882a593Smuzhiyun radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
2534*4882a593Smuzhiyun if (!radeon_connector->ddc_bus)
2535*4882a593Smuzhiyun DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
2536*4882a593Smuzhiyun else
2537*4882a593Smuzhiyun ddc = &radeon_connector->ddc_bus->adapter;
2538*4882a593Smuzhiyun }
2539*4882a593Smuzhiyun drm_connector_init_with_ddc(dev, &radeon_connector->base,
2540*4882a593Smuzhiyun &radeon_lvds_connector_funcs,
2541*4882a593Smuzhiyun connector_type,
2542*4882a593Smuzhiyun ddc);
2543*4882a593Smuzhiyun drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs);
2544*4882a593Smuzhiyun drm_object_attach_property(&radeon_connector->base.base,
2545*4882a593Smuzhiyun dev->mode_config.scaling_mode_property,
2546*4882a593Smuzhiyun DRM_MODE_SCALE_FULLSCREEN);
2547*4882a593Smuzhiyun subpixel_order = SubPixelHorizontalRGB;
2548*4882a593Smuzhiyun connector->interlace_allowed = false;
2549*4882a593Smuzhiyun connector->doublescan_allowed = false;
2550*4882a593Smuzhiyun break;
2551*4882a593Smuzhiyun }
2552*4882a593Smuzhiyun
2553*4882a593Smuzhiyun if (radeon_connector->hpd.hpd == RADEON_HPD_NONE) {
2554*4882a593Smuzhiyun if (i2c_bus->valid) {
2555*4882a593Smuzhiyun connector->polled = DRM_CONNECTOR_POLL_CONNECT |
2556*4882a593Smuzhiyun DRM_CONNECTOR_POLL_DISCONNECT;
2557*4882a593Smuzhiyun }
2558*4882a593Smuzhiyun } else
2559*4882a593Smuzhiyun connector->polled = DRM_CONNECTOR_POLL_HPD;
2560*4882a593Smuzhiyun
2561*4882a593Smuzhiyun connector->display_info.subpixel_order = subpixel_order;
2562*4882a593Smuzhiyun drm_connector_register(connector);
2563*4882a593Smuzhiyun }
2564*4882a593Smuzhiyun
radeon_setup_mst_connector(struct drm_device * dev)2565*4882a593Smuzhiyun void radeon_setup_mst_connector(struct drm_device *dev)
2566*4882a593Smuzhiyun {
2567*4882a593Smuzhiyun struct radeon_device *rdev = dev->dev_private;
2568*4882a593Smuzhiyun struct drm_connector *connector;
2569*4882a593Smuzhiyun struct radeon_connector *radeon_connector;
2570*4882a593Smuzhiyun
2571*4882a593Smuzhiyun if (!ASIC_IS_DCE5(rdev))
2572*4882a593Smuzhiyun return;
2573*4882a593Smuzhiyun
2574*4882a593Smuzhiyun if (radeon_mst == 0)
2575*4882a593Smuzhiyun return;
2576*4882a593Smuzhiyun
2577*4882a593Smuzhiyun list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2578*4882a593Smuzhiyun int ret;
2579*4882a593Smuzhiyun
2580*4882a593Smuzhiyun radeon_connector = to_radeon_connector(connector);
2581*4882a593Smuzhiyun
2582*4882a593Smuzhiyun if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
2583*4882a593Smuzhiyun continue;
2584*4882a593Smuzhiyun
2585*4882a593Smuzhiyun ret = radeon_dp_mst_init(radeon_connector);
2586*4882a593Smuzhiyun }
2587*4882a593Smuzhiyun }
2588