1*4882a593Smuzhiyun /* SPDX-License-Identifier: MIT */ 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun #include "radeon.h" 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define R100_TRACK_MAX_TEXTURE 3 6*4882a593Smuzhiyun #define R200_TRACK_MAX_TEXTURE 6 7*4882a593Smuzhiyun #define R300_TRACK_MAX_TEXTURE 16 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define R100_MAX_CB 1 10*4882a593Smuzhiyun #define R300_MAX_CB 4 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * CS functions 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun struct r100_cs_track_cb { 16*4882a593Smuzhiyun struct radeon_bo *robj; 17*4882a593Smuzhiyun unsigned pitch; 18*4882a593Smuzhiyun unsigned cpp; 19*4882a593Smuzhiyun unsigned offset; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun struct r100_cs_track_array { 23*4882a593Smuzhiyun struct radeon_bo *robj; 24*4882a593Smuzhiyun unsigned esize; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun struct r100_cs_cube_info { 28*4882a593Smuzhiyun struct radeon_bo *robj; 29*4882a593Smuzhiyun unsigned offset; 30*4882a593Smuzhiyun unsigned width; 31*4882a593Smuzhiyun unsigned height; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define R100_TRACK_COMP_NONE 0 35*4882a593Smuzhiyun #define R100_TRACK_COMP_DXT1 1 36*4882a593Smuzhiyun #define R100_TRACK_COMP_DXT35 2 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun struct r100_cs_track_texture { 39*4882a593Smuzhiyun struct radeon_bo *robj; 40*4882a593Smuzhiyun struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */ 41*4882a593Smuzhiyun unsigned pitch; 42*4882a593Smuzhiyun unsigned width; 43*4882a593Smuzhiyun unsigned height; 44*4882a593Smuzhiyun unsigned num_levels; 45*4882a593Smuzhiyun unsigned cpp; 46*4882a593Smuzhiyun unsigned tex_coord_type; 47*4882a593Smuzhiyun unsigned txdepth; 48*4882a593Smuzhiyun unsigned width_11; 49*4882a593Smuzhiyun unsigned height_11; 50*4882a593Smuzhiyun bool use_pitch; 51*4882a593Smuzhiyun bool enabled; 52*4882a593Smuzhiyun bool lookup_disable; 53*4882a593Smuzhiyun bool roundup_w; 54*4882a593Smuzhiyun bool roundup_h; 55*4882a593Smuzhiyun unsigned compress_format; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun struct r100_cs_track { 59*4882a593Smuzhiyun unsigned num_cb; 60*4882a593Smuzhiyun unsigned num_texture; 61*4882a593Smuzhiyun unsigned maxy; 62*4882a593Smuzhiyun unsigned vtx_size; 63*4882a593Smuzhiyun unsigned vap_vf_cntl; 64*4882a593Smuzhiyun unsigned vap_alt_nverts; 65*4882a593Smuzhiyun unsigned immd_dwords; 66*4882a593Smuzhiyun unsigned num_arrays; 67*4882a593Smuzhiyun unsigned max_indx; 68*4882a593Smuzhiyun unsigned color_channel_mask; 69*4882a593Smuzhiyun struct r100_cs_track_array arrays[16]; 70*4882a593Smuzhiyun struct r100_cs_track_cb cb[R300_MAX_CB]; 71*4882a593Smuzhiyun struct r100_cs_track_cb zb; 72*4882a593Smuzhiyun struct r100_cs_track_cb aa; 73*4882a593Smuzhiyun struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE]; 74*4882a593Smuzhiyun bool z_enabled; 75*4882a593Smuzhiyun bool separate_cube; 76*4882a593Smuzhiyun bool zb_cb_clear; 77*4882a593Smuzhiyun bool blend_read_enable; 78*4882a593Smuzhiyun bool cb_dirty; 79*4882a593Smuzhiyun bool zb_dirty; 80*4882a593Smuzhiyun bool tex_dirty; 81*4882a593Smuzhiyun bool aa_dirty; 82*4882a593Smuzhiyun bool aaresolve; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track); 86*4882a593Smuzhiyun void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track); 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun int r100_cs_packet_parse_vline(struct radeon_cs_parser *p); 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun int r200_packet0_check(struct radeon_cs_parser *p, 91*4882a593Smuzhiyun struct radeon_cs_packet *pkt, 92*4882a593Smuzhiyun unsigned idx, unsigned reg); 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun int r100_reloc_pitch_offset(struct radeon_cs_parser *p, 95*4882a593Smuzhiyun struct radeon_cs_packet *pkt, 96*4882a593Smuzhiyun unsigned idx, 97*4882a593Smuzhiyun unsigned reg); 98*4882a593Smuzhiyun int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, 99*4882a593Smuzhiyun struct radeon_cs_packet *pkt, 100*4882a593Smuzhiyun int idx); 101