1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2010 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * Authors: Alex Deucher 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun #ifndef __NI_REG_H__ 25*4882a593Smuzhiyun #define __NI_REG_H__ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* northern islands - DCE5 */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define NI_INPUT_GAMMA_CONTROL 0x6840 30*4882a593Smuzhiyun # define NI_GRPH_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 0) 31*4882a593Smuzhiyun # define NI_INPUT_GAMMA_USE_LUT 0 32*4882a593Smuzhiyun # define NI_INPUT_GAMMA_BYPASS 1 33*4882a593Smuzhiyun # define NI_INPUT_GAMMA_SRGB_24 2 34*4882a593Smuzhiyun # define NI_INPUT_GAMMA_XVYCC_222 3 35*4882a593Smuzhiyun # define NI_OVL_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 4) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define NI_PRESCALE_GRPH_CONTROL 0x68b4 38*4882a593Smuzhiyun # define NI_GRPH_PRESCALE_BYPASS (1 << 4) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define NI_PRESCALE_OVL_CONTROL 0x68c4 41*4882a593Smuzhiyun # define NI_OVL_PRESCALE_BYPASS (1 << 4) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define NI_INPUT_CSC_CONTROL 0x68d4 44*4882a593Smuzhiyun # define NI_INPUT_CSC_GRPH_MODE(x) (((x) & 0x3) << 0) 45*4882a593Smuzhiyun # define NI_INPUT_CSC_BYPASS 0 46*4882a593Smuzhiyun # define NI_INPUT_CSC_PROG_COEFF 1 47*4882a593Smuzhiyun # define NI_INPUT_CSC_PROG_SHARED_MATRIXA 2 48*4882a593Smuzhiyun # define NI_INPUT_CSC_OVL_MODE(x) (((x) & 0x3) << 4) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define NI_OUTPUT_CSC_CONTROL 0x68f0 51*4882a593Smuzhiyun # define NI_OUTPUT_CSC_GRPH_MODE(x) (((x) & 0x7) << 0) 52*4882a593Smuzhiyun # define NI_OUTPUT_CSC_BYPASS 0 53*4882a593Smuzhiyun # define NI_OUTPUT_CSC_TV_RGB 1 54*4882a593Smuzhiyun # define NI_OUTPUT_CSC_YCBCR_601 2 55*4882a593Smuzhiyun # define NI_OUTPUT_CSC_YCBCR_709 3 56*4882a593Smuzhiyun # define NI_OUTPUT_CSC_PROG_COEFF 4 57*4882a593Smuzhiyun # define NI_OUTPUT_CSC_PROG_SHARED_MATRIXB 5 58*4882a593Smuzhiyun # define NI_OUTPUT_CSC_OVL_MODE(x) (((x) & 0x7) << 4) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define NI_DEGAMMA_CONTROL 0x6960 61*4882a593Smuzhiyun # define NI_GRPH_DEGAMMA_MODE(x) (((x) & 0x3) << 0) 62*4882a593Smuzhiyun # define NI_DEGAMMA_BYPASS 0 63*4882a593Smuzhiyun # define NI_DEGAMMA_SRGB_24 1 64*4882a593Smuzhiyun # define NI_DEGAMMA_XVYCC_222 2 65*4882a593Smuzhiyun # define NI_OVL_DEGAMMA_MODE(x) (((x) & 0x3) << 4) 66*4882a593Smuzhiyun # define NI_ICON_DEGAMMA_MODE(x) (((x) & 0x3) << 8) 67*4882a593Smuzhiyun # define NI_CURSOR_DEGAMMA_MODE(x) (((x) & 0x3) << 12) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define NI_GAMUT_REMAP_CONTROL 0x6964 70*4882a593Smuzhiyun # define NI_GRPH_GAMUT_REMAP_MODE(x) (((x) & 0x3) << 0) 71*4882a593Smuzhiyun # define NI_GAMUT_REMAP_BYPASS 0 72*4882a593Smuzhiyun # define NI_GAMUT_REMAP_PROG_COEFF 1 73*4882a593Smuzhiyun # define NI_GAMUT_REMAP_PROG_SHARED_MATRIXA 2 74*4882a593Smuzhiyun # define NI_GAMUT_REMAP_PROG_SHARED_MATRIXB 3 75*4882a593Smuzhiyun # define NI_OVL_GAMUT_REMAP_MODE(x) (((x) & 0x3) << 4) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define NI_REGAMMA_CONTROL 0x6a80 78*4882a593Smuzhiyun # define NI_GRPH_REGAMMA_MODE(x) (((x) & 0x7) << 0) 79*4882a593Smuzhiyun # define NI_REGAMMA_BYPASS 0 80*4882a593Smuzhiyun # define NI_REGAMMA_SRGB_24 1 81*4882a593Smuzhiyun # define NI_REGAMMA_XVYCC_222 2 82*4882a593Smuzhiyun # define NI_REGAMMA_PROG_A 3 83*4882a593Smuzhiyun # define NI_REGAMMA_PROG_B 4 84*4882a593Smuzhiyun # define NI_OVL_REGAMMA_MODE(x) (((x) & 0x7) << 4) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define NI_DP_MSE_LINK_TIMING 0x73a0 87*4882a593Smuzhiyun # define NI_DP_MSE_LINK_FRAME (((x) & 0x3ff) << 0) 88*4882a593Smuzhiyun # define NI_DP_MSE_LINK_LINE (((x) & 0x3) << 16) 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define NI_DP_MSE_MISC_CNTL 0x736c 91*4882a593Smuzhiyun # define NI_DP_MSE_BLANK_CODE (((x) & 0x1) << 0) 92*4882a593Smuzhiyun # define NI_DP_MSE_TIMESTAMP_MODE (((x) & 0x1) << 4) 93*4882a593Smuzhiyun # define NI_DP_MSE_ZERO_ENCODER (((x) & 0x1) << 8) 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define NI_DP_MSE_RATE_CNTL 0x7384 96*4882a593Smuzhiyun # define NI_DP_MSE_RATE_Y(x) (((x) & 0x3ffffff) << 0) 97*4882a593Smuzhiyun # define NI_DP_MSE_RATE_X(x) (((x) & 0x3f) << 26) 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #define NI_DP_MSE_RATE_UPDATE 0x738c 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define NI_DP_MSE_SAT0 0x7390 102*4882a593Smuzhiyun # define NI_DP_MSE_SAT_SRC0(x) (((x) & 0x7) << 0) 103*4882a593Smuzhiyun # define NI_DP_MSE_SAT_SLOT_COUNT0(x) (((x) & 0x3f) << 8) 104*4882a593Smuzhiyun # define NI_DP_MSE_SAT_SRC1(x) (((x) & 0x7) << 16) 105*4882a593Smuzhiyun # define NI_DP_MSE_SAT_SLOT_COUNT1(x) (((x) & 0x3f) << 24) 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #define NI_DP_MSE_SAT1 0x7394 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #define NI_DP_MSE_SAT2 0x7398 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #define NI_DP_MSE_SAT_UPDATE 0x739c 112*4882a593Smuzhiyun # define NI_DP_MSE_SAT_UPDATE_MASK 0x3 113*4882a593Smuzhiyun # define NI_DP_MSE_16_MTP_KEEPOUT 0x100 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define NI_DIG_BE_CNTL 0x7140 116*4882a593Smuzhiyun # define NI_DIG_FE_SOURCE_SELECT(x) (((x) & 0x7f) << 8) 117*4882a593Smuzhiyun # define NI_DIG_FE_DIG_MODE(x) (((x) & 0x7) << 16) 118*4882a593Smuzhiyun # define NI_DIG_MODE_DP_SST 0 119*4882a593Smuzhiyun # define NI_DIG_MODE_LVDS 1 120*4882a593Smuzhiyun # define NI_DIG_MODE_TMDS_DVI 2 121*4882a593Smuzhiyun # define NI_DIG_MODE_TMDS_HDMI 3 122*4882a593Smuzhiyun # define NI_DIG_MODE_DP_MST 5 123*4882a593Smuzhiyun # define NI_DIG_HPD_SELECT(x) (((x) & 0x7) << 28) 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun #define NI_DIG_FE_CNTL 0x7000 126*4882a593Smuzhiyun # define NI_DIG_SOURCE_SELECT(x) (((x) & 0x3) << 0) 127*4882a593Smuzhiyun # define NI_DIG_STEREOSYNC_SELECT(x) (((x) & 0x3) << 4) 128*4882a593Smuzhiyun # define NI_DIG_STEREOSYNC_GATE_EN(x) (((x) & 0x1) << 8) 129*4882a593Smuzhiyun # define NI_DIG_DUAL_LINK_ENABLE(x) (((x) & 0x1) << 16) 130*4882a593Smuzhiyun # define NI_DIG_SWAP(x) (((x) & 0x1) << 18) 131*4882a593Smuzhiyun # define NI_DIG_SYMCLK_FE_ON (0x1 << 24) 132*4882a593Smuzhiyun #endif 133