xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/kv_dpm.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright 2013 Advanced Micro Devices, Inc.
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Permission is hereby granted, free of charge, to any person obtaining a
5*4882a593Smuzhiyun  * copy of this software and associated documentation files (the "Software"),
6*4882a593Smuzhiyun  * to deal in the Software without restriction, including without limitation
7*4882a593Smuzhiyun  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*4882a593Smuzhiyun  * and/or sell copies of the Software, and to permit persons to whom the
9*4882a593Smuzhiyun  * Software is furnished to do so, subject to the following conditions:
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * The above copyright notice and this permission notice shall be included in
12*4882a593Smuzhiyun  * all copies or substantial portions of the Software.
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*4882a593Smuzhiyun  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17*4882a593Smuzhiyun  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*4882a593Smuzhiyun  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*4882a593Smuzhiyun  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*4882a593Smuzhiyun  * OTHER DEALINGS IN THE SOFTWARE.
21*4882a593Smuzhiyun  *
22*4882a593Smuzhiyun  */
23*4882a593Smuzhiyun #ifndef __KV_DPM_H__
24*4882a593Smuzhiyun #define __KV_DPM_H__
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #define SMU__NUM_SCLK_DPM_STATE  8
27*4882a593Smuzhiyun #define SMU__NUM_MCLK_DPM_LEVELS 4
28*4882a593Smuzhiyun #define SMU__NUM_LCLK_DPM_LEVELS 8
29*4882a593Smuzhiyun #define SMU__NUM_PCIE_DPM_LEVELS 0 /* ??? */
30*4882a593Smuzhiyun #include "smu7_fusion.h"
31*4882a593Smuzhiyun #include "trinity_dpm.h"
32*4882a593Smuzhiyun #include "ppsmc.h"
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #define KV_NUM_NBPSTATES   4
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun enum kv_pt_config_reg_type {
37*4882a593Smuzhiyun 	KV_CONFIGREG_MMR = 0,
38*4882a593Smuzhiyun 	KV_CONFIGREG_SMC_IND,
39*4882a593Smuzhiyun 	KV_CONFIGREG_DIDT_IND,
40*4882a593Smuzhiyun 	KV_CONFIGREG_CACHE,
41*4882a593Smuzhiyun 	KV_CONFIGREG_MAX
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun struct kv_pt_config_reg {
45*4882a593Smuzhiyun 	u32 offset;
46*4882a593Smuzhiyun 	u32 mask;
47*4882a593Smuzhiyun 	u32 shift;
48*4882a593Smuzhiyun 	u32 value;
49*4882a593Smuzhiyun 	enum kv_pt_config_reg_type type;
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun struct kv_lcac_config_values {
53*4882a593Smuzhiyun 	u32 block_id;
54*4882a593Smuzhiyun 	u32 signal_id;
55*4882a593Smuzhiyun 	u32 t;
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun struct kv_lcac_config_reg {
59*4882a593Smuzhiyun 	u32 cntl;
60*4882a593Smuzhiyun 	u32 block_mask;
61*4882a593Smuzhiyun 	u32 block_shift;
62*4882a593Smuzhiyun 	u32 signal_mask;
63*4882a593Smuzhiyun 	u32 signal_shift;
64*4882a593Smuzhiyun 	u32 t_mask;
65*4882a593Smuzhiyun 	u32 t_shift;
66*4882a593Smuzhiyun 	u32 enable_mask;
67*4882a593Smuzhiyun 	u32 enable_shift;
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun struct kv_pl {
71*4882a593Smuzhiyun 	u32 sclk;
72*4882a593Smuzhiyun 	u8 vddc_index;
73*4882a593Smuzhiyun 	u8 ds_divider_index;
74*4882a593Smuzhiyun 	u8 ss_divider_index;
75*4882a593Smuzhiyun 	u8 allow_gnb_slow;
76*4882a593Smuzhiyun 	u8 force_nbp_state;
77*4882a593Smuzhiyun 	u8 display_wm;
78*4882a593Smuzhiyun 	u8 vce_wm;
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun struct kv_ps {
82*4882a593Smuzhiyun 	struct kv_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS];
83*4882a593Smuzhiyun 	u32 num_levels;
84*4882a593Smuzhiyun 	bool need_dfs_bypass;
85*4882a593Smuzhiyun 	u8 dpm0_pg_nb_ps_lo;
86*4882a593Smuzhiyun 	u8 dpm0_pg_nb_ps_hi;
87*4882a593Smuzhiyun 	u8 dpmx_nb_ps_lo;
88*4882a593Smuzhiyun 	u8 dpmx_nb_ps_hi;
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun struct kv_sys_info {
92*4882a593Smuzhiyun 	u32 bootup_uma_clk;
93*4882a593Smuzhiyun 	u32 bootup_sclk;
94*4882a593Smuzhiyun 	u32 dentist_vco_freq;
95*4882a593Smuzhiyun 	u32 nb_dpm_enable;
96*4882a593Smuzhiyun 	u32 nbp_memory_clock[KV_NUM_NBPSTATES];
97*4882a593Smuzhiyun 	u32 nbp_n_clock[KV_NUM_NBPSTATES];
98*4882a593Smuzhiyun 	u16 bootup_nb_voltage_index;
99*4882a593Smuzhiyun 	u8 htc_tmp_lmt;
100*4882a593Smuzhiyun 	u8 htc_hyst_lmt;
101*4882a593Smuzhiyun 	struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table;
102*4882a593Smuzhiyun 	struct sumo_vid_mapping_table vid_mapping_table;
103*4882a593Smuzhiyun 	u32 uma_channel_number;
104*4882a593Smuzhiyun };
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun struct kv_power_info {
107*4882a593Smuzhiyun 	u32 at[SUMO_MAX_HARDWARE_POWERLEVELS];
108*4882a593Smuzhiyun 	u32 voltage_drop_t;
109*4882a593Smuzhiyun 	struct kv_sys_info sys_info;
110*4882a593Smuzhiyun 	struct kv_pl boot_pl;
111*4882a593Smuzhiyun 	bool enable_nb_ps_policy;
112*4882a593Smuzhiyun 	bool disable_nb_ps3_in_battery;
113*4882a593Smuzhiyun 	bool video_start;
114*4882a593Smuzhiyun 	bool battery_state;
115*4882a593Smuzhiyun 	u32 lowest_valid;
116*4882a593Smuzhiyun 	u32 highest_valid;
117*4882a593Smuzhiyun 	u16 high_voltage_t;
118*4882a593Smuzhiyun 	bool cac_enabled;
119*4882a593Smuzhiyun 	bool bapm_enable;
120*4882a593Smuzhiyun 	/* smc offsets */
121*4882a593Smuzhiyun 	u32 sram_end;
122*4882a593Smuzhiyun 	u32 dpm_table_start;
123*4882a593Smuzhiyun 	u32 soft_regs_start;
124*4882a593Smuzhiyun 	/* dpm SMU tables */
125*4882a593Smuzhiyun 	u8 graphics_dpm_level_count;
126*4882a593Smuzhiyun 	u8 uvd_level_count;
127*4882a593Smuzhiyun 	u8 vce_level_count;
128*4882a593Smuzhiyun 	u8 acp_level_count;
129*4882a593Smuzhiyun 	u8 samu_level_count;
130*4882a593Smuzhiyun 	u16 fps_high_t;
131*4882a593Smuzhiyun 	SMU7_Fusion_GraphicsLevel graphics_level[SMU__NUM_SCLK_DPM_STATE];
132*4882a593Smuzhiyun 	SMU7_Fusion_ACPILevel acpi_level;
133*4882a593Smuzhiyun 	SMU7_Fusion_UvdLevel uvd_level[SMU7_MAX_LEVELS_UVD];
134*4882a593Smuzhiyun 	SMU7_Fusion_ExtClkLevel vce_level[SMU7_MAX_LEVELS_VCE];
135*4882a593Smuzhiyun 	SMU7_Fusion_ExtClkLevel acp_level[SMU7_MAX_LEVELS_ACP];
136*4882a593Smuzhiyun 	SMU7_Fusion_ExtClkLevel samu_level[SMU7_MAX_LEVELS_SAMU];
137*4882a593Smuzhiyun 	u8 uvd_boot_level;
138*4882a593Smuzhiyun 	u8 vce_boot_level;
139*4882a593Smuzhiyun 	u8 acp_boot_level;
140*4882a593Smuzhiyun 	u8 samu_boot_level;
141*4882a593Smuzhiyun 	u8 uvd_interval;
142*4882a593Smuzhiyun 	u8 vce_interval;
143*4882a593Smuzhiyun 	u8 acp_interval;
144*4882a593Smuzhiyun 	u8 samu_interval;
145*4882a593Smuzhiyun 	u8 graphics_boot_level;
146*4882a593Smuzhiyun 	u8 graphics_interval;
147*4882a593Smuzhiyun 	u8 graphics_therm_throttle_enable;
148*4882a593Smuzhiyun 	u8 graphics_voltage_change_enable;
149*4882a593Smuzhiyun 	u8 graphics_clk_slow_enable;
150*4882a593Smuzhiyun 	u8 graphics_clk_slow_divider;
151*4882a593Smuzhiyun 	u8 fps_low_t;
152*4882a593Smuzhiyun 	u32 low_sclk_interrupt_t;
153*4882a593Smuzhiyun 	bool uvd_power_gated;
154*4882a593Smuzhiyun 	bool vce_power_gated;
155*4882a593Smuzhiyun 	bool acp_power_gated;
156*4882a593Smuzhiyun 	bool samu_power_gated;
157*4882a593Smuzhiyun 	bool nb_dpm_enabled;
158*4882a593Smuzhiyun 	/* flags */
159*4882a593Smuzhiyun 	bool enable_didt;
160*4882a593Smuzhiyun 	bool enable_dpm;
161*4882a593Smuzhiyun 	bool enable_auto_thermal_throttling;
162*4882a593Smuzhiyun 	bool enable_nb_dpm;
163*4882a593Smuzhiyun 	/* caps */
164*4882a593Smuzhiyun 	bool caps_cac;
165*4882a593Smuzhiyun 	bool caps_power_containment;
166*4882a593Smuzhiyun 	bool caps_sq_ramping;
167*4882a593Smuzhiyun 	bool caps_db_ramping;
168*4882a593Smuzhiyun 	bool caps_td_ramping;
169*4882a593Smuzhiyun 	bool caps_tcp_ramping;
170*4882a593Smuzhiyun 	bool caps_sclk_throttle_low_notification;
171*4882a593Smuzhiyun 	bool caps_fps;
172*4882a593Smuzhiyun 	bool caps_uvd_dpm;
173*4882a593Smuzhiyun 	bool caps_uvd_pg;
174*4882a593Smuzhiyun 	bool caps_vce_pg;
175*4882a593Smuzhiyun 	bool caps_samu_pg;
176*4882a593Smuzhiyun 	bool caps_acp_pg;
177*4882a593Smuzhiyun 	bool caps_stable_p_state;
178*4882a593Smuzhiyun 	bool caps_enable_dfs_bypass;
179*4882a593Smuzhiyun 	bool caps_sclk_ds;
180*4882a593Smuzhiyun 	struct radeon_ps current_rps;
181*4882a593Smuzhiyun 	struct kv_ps current_ps;
182*4882a593Smuzhiyun 	struct radeon_ps requested_rps;
183*4882a593Smuzhiyun 	struct kv_ps requested_ps;
184*4882a593Smuzhiyun };
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun /* kv_smc.c */
188*4882a593Smuzhiyun int kv_notify_message_to_smu(struct radeon_device *rdev, u32 id);
189*4882a593Smuzhiyun int kv_dpm_get_enable_mask(struct radeon_device *rdev, u32 *enable_mask);
190*4882a593Smuzhiyun int kv_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
191*4882a593Smuzhiyun 				      PPSMC_Msg msg, u32 parameter);
192*4882a593Smuzhiyun int kv_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
193*4882a593Smuzhiyun 			   u32 *value, u32 limit);
194*4882a593Smuzhiyun int kv_smc_dpm_enable(struct radeon_device *rdev, bool enable);
195*4882a593Smuzhiyun int kv_smc_bapm_enable(struct radeon_device *rdev, bool enable);
196*4882a593Smuzhiyun int kv_copy_bytes_to_smc(struct radeon_device *rdev,
197*4882a593Smuzhiyun 			 u32 smc_start_address,
198*4882a593Smuzhiyun 			 const u8 *src, u32 byte_count, u32 limit);
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun #endif
201