1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2010 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * Authors: Alex Deucher 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun #ifndef __EVERGREEN_REG_H__ 25*4882a593Smuzhiyun #define __EVERGREEN_REG_H__ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* trinity */ 28*4882a593Smuzhiyun #define TN_SMC_IND_INDEX_0 0x200 29*4882a593Smuzhiyun #define TN_SMC_IND_DATA_0 0x204 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* evergreen */ 32*4882a593Smuzhiyun #define EVERGREEN_PIF_PHY0_INDEX 0x8 33*4882a593Smuzhiyun #define EVERGREEN_PIF_PHY0_DATA 0xc 34*4882a593Smuzhiyun #define EVERGREEN_PIF_PHY1_INDEX 0x10 35*4882a593Smuzhiyun #define EVERGREEN_PIF_PHY1_DATA 0x14 36*4882a593Smuzhiyun #define EVERGREEN_MM_INDEX_HI 0x18 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0x310 39*4882a593Smuzhiyun #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0x324 40*4882a593Smuzhiyun #define EVERGREEN_D3VGA_CONTROL 0x3e0 41*4882a593Smuzhiyun #define EVERGREEN_D4VGA_CONTROL 0x3e4 42*4882a593Smuzhiyun #define EVERGREEN_D5VGA_CONTROL 0x3e8 43*4882a593Smuzhiyun #define EVERGREEN_D6VGA_CONTROL 0x3ec 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define EVERGREEN_P1PLL_SS_CNTL 0x414 46*4882a593Smuzhiyun #define EVERGREEN_P2PLL_SS_CNTL 0x454 47*4882a593Smuzhiyun # define EVERGREEN_PxPLL_SS_EN (1 << 12) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define EVERGREEN_AUDIO_PLL1_MUL 0x5b0 50*4882a593Smuzhiyun #define EVERGREEN_AUDIO_PLL1_DIV 0x5b4 51*4882a593Smuzhiyun #define EVERGREEN_AUDIO_PLL1_UNK 0x5bc 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define EVERGREEN_CG_IND_ADDR 0x8f8 54*4882a593Smuzhiyun #define EVERGREEN_CG_IND_DATA 0x8fc 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define EVERGREEN_AUDIO_ENABLE 0x5e78 57*4882a593Smuzhiyun #define EVERGREEN_AUDIO_VENDOR_ID 0x5ec0 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* GRPH blocks at 0x6800, 0x7400, 0x10000, 0x10c00, 0x11800, 0x12400 */ 60*4882a593Smuzhiyun #define EVERGREEN_GRPH_ENABLE 0x6800 61*4882a593Smuzhiyun #define EVERGREEN_GRPH_CONTROL 0x6804 62*4882a593Smuzhiyun # define EVERGREEN_GRPH_DEPTH(x) (((x) & 0x3) << 0) 63*4882a593Smuzhiyun # define EVERGREEN_GRPH_DEPTH_8BPP 0 64*4882a593Smuzhiyun # define EVERGREEN_GRPH_DEPTH_16BPP 1 65*4882a593Smuzhiyun # define EVERGREEN_GRPH_DEPTH_32BPP 2 66*4882a593Smuzhiyun # define EVERGREEN_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2) 67*4882a593Smuzhiyun # define EVERGREEN_ADDR_SURF_2_BANK 0 68*4882a593Smuzhiyun # define EVERGREEN_ADDR_SURF_4_BANK 1 69*4882a593Smuzhiyun # define EVERGREEN_ADDR_SURF_8_BANK 2 70*4882a593Smuzhiyun # define EVERGREEN_ADDR_SURF_16_BANK 3 71*4882a593Smuzhiyun # define EVERGREEN_GRPH_Z(x) (((x) & 0x3) << 4) 72*4882a593Smuzhiyun # define EVERGREEN_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6) 73*4882a593Smuzhiyun # define EVERGREEN_ADDR_SURF_BANK_WIDTH_1 0 74*4882a593Smuzhiyun # define EVERGREEN_ADDR_SURF_BANK_WIDTH_2 1 75*4882a593Smuzhiyun # define EVERGREEN_ADDR_SURF_BANK_WIDTH_4 2 76*4882a593Smuzhiyun # define EVERGREEN_ADDR_SURF_BANK_WIDTH_8 3 77*4882a593Smuzhiyun # define EVERGREEN_GRPH_FORMAT(x) (((x) & 0x7) << 8) 78*4882a593Smuzhiyun /* 8 BPP */ 79*4882a593Smuzhiyun # define EVERGREEN_GRPH_FORMAT_INDEXED 0 80*4882a593Smuzhiyun /* 16 BPP */ 81*4882a593Smuzhiyun # define EVERGREEN_GRPH_FORMAT_ARGB1555 0 82*4882a593Smuzhiyun # define EVERGREEN_GRPH_FORMAT_ARGB565 1 83*4882a593Smuzhiyun # define EVERGREEN_GRPH_FORMAT_ARGB4444 2 84*4882a593Smuzhiyun # define EVERGREEN_GRPH_FORMAT_AI88 3 85*4882a593Smuzhiyun # define EVERGREEN_GRPH_FORMAT_MONO16 4 86*4882a593Smuzhiyun # define EVERGREEN_GRPH_FORMAT_BGRA5551 5 87*4882a593Smuzhiyun /* 32 BPP */ 88*4882a593Smuzhiyun # define EVERGREEN_GRPH_FORMAT_ARGB8888 0 89*4882a593Smuzhiyun # define EVERGREEN_GRPH_FORMAT_ARGB2101010 1 90*4882a593Smuzhiyun # define EVERGREEN_GRPH_FORMAT_32BPP_DIG 2 91*4882a593Smuzhiyun # define EVERGREEN_GRPH_FORMAT_8B_ARGB2101010 3 92*4882a593Smuzhiyun # define EVERGREEN_GRPH_FORMAT_BGRA1010102 4 93*4882a593Smuzhiyun # define EVERGREEN_GRPH_FORMAT_8B_BGRA1010102 5 94*4882a593Smuzhiyun # define EVERGREEN_GRPH_FORMAT_RGB111110 6 95*4882a593Smuzhiyun # define EVERGREEN_GRPH_FORMAT_BGR101111 7 96*4882a593Smuzhiyun # define EVERGREEN_GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11) 97*4882a593Smuzhiyun # define EVERGREEN_ADDR_SURF_BANK_HEIGHT_1 0 98*4882a593Smuzhiyun # define EVERGREEN_ADDR_SURF_BANK_HEIGHT_2 1 99*4882a593Smuzhiyun # define EVERGREEN_ADDR_SURF_BANK_HEIGHT_4 2 100*4882a593Smuzhiyun # define EVERGREEN_ADDR_SURF_BANK_HEIGHT_8 3 101*4882a593Smuzhiyun # define EVERGREEN_GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13) 102*4882a593Smuzhiyun # define EVERGREEN_ADDR_SURF_TILE_SPLIT_64B 0 103*4882a593Smuzhiyun # define EVERGREEN_ADDR_SURF_TILE_SPLIT_128B 1 104*4882a593Smuzhiyun # define EVERGREEN_ADDR_SURF_TILE_SPLIT_256B 2 105*4882a593Smuzhiyun # define EVERGREEN_ADDR_SURF_TILE_SPLIT_512B 3 106*4882a593Smuzhiyun # define EVERGREEN_ADDR_SURF_TILE_SPLIT_1KB 4 107*4882a593Smuzhiyun # define EVERGREEN_ADDR_SURF_TILE_SPLIT_2KB 5 108*4882a593Smuzhiyun # define EVERGREEN_ADDR_SURF_TILE_SPLIT_4KB 6 109*4882a593Smuzhiyun # define EVERGREEN_GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18) 110*4882a593Smuzhiyun # define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1 0 111*4882a593Smuzhiyun # define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2 1 112*4882a593Smuzhiyun # define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4 2 113*4882a593Smuzhiyun # define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8 3 114*4882a593Smuzhiyun # define EVERGREEN_GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20) 115*4882a593Smuzhiyun # define EVERGREEN_GRPH_ARRAY_LINEAR_GENERAL 0 116*4882a593Smuzhiyun # define EVERGREEN_GRPH_ARRAY_LINEAR_ALIGNED 1 117*4882a593Smuzhiyun # define EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1 2 118*4882a593Smuzhiyun # define EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1 4 119*4882a593Smuzhiyun #define EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL 0x6808 120*4882a593Smuzhiyun # define EVERGREEN_LUT_10BIT_BYPASS_EN (1 << 8) 121*4882a593Smuzhiyun #define EVERGREEN_GRPH_SWAP_CONTROL 0x680c 122*4882a593Smuzhiyun # define EVERGREEN_GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) 123*4882a593Smuzhiyun # define EVERGREEN_GRPH_ENDIAN_NONE 0 124*4882a593Smuzhiyun # define EVERGREEN_GRPH_ENDIAN_8IN16 1 125*4882a593Smuzhiyun # define EVERGREEN_GRPH_ENDIAN_8IN32 2 126*4882a593Smuzhiyun # define EVERGREEN_GRPH_ENDIAN_8IN64 3 127*4882a593Smuzhiyun # define EVERGREEN_GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4) 128*4882a593Smuzhiyun # define EVERGREEN_GRPH_RED_SEL_R 0 129*4882a593Smuzhiyun # define EVERGREEN_GRPH_RED_SEL_G 1 130*4882a593Smuzhiyun # define EVERGREEN_GRPH_RED_SEL_B 2 131*4882a593Smuzhiyun # define EVERGREEN_GRPH_RED_SEL_A 3 132*4882a593Smuzhiyun # define EVERGREEN_GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6) 133*4882a593Smuzhiyun # define EVERGREEN_GRPH_GREEN_SEL_G 0 134*4882a593Smuzhiyun # define EVERGREEN_GRPH_GREEN_SEL_B 1 135*4882a593Smuzhiyun # define EVERGREEN_GRPH_GREEN_SEL_A 2 136*4882a593Smuzhiyun # define EVERGREEN_GRPH_GREEN_SEL_R 3 137*4882a593Smuzhiyun # define EVERGREEN_GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8) 138*4882a593Smuzhiyun # define EVERGREEN_GRPH_BLUE_SEL_B 0 139*4882a593Smuzhiyun # define EVERGREEN_GRPH_BLUE_SEL_A 1 140*4882a593Smuzhiyun # define EVERGREEN_GRPH_BLUE_SEL_R 2 141*4882a593Smuzhiyun # define EVERGREEN_GRPH_BLUE_SEL_G 3 142*4882a593Smuzhiyun # define EVERGREEN_GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10) 143*4882a593Smuzhiyun # define EVERGREEN_GRPH_ALPHA_SEL_A 0 144*4882a593Smuzhiyun # define EVERGREEN_GRPH_ALPHA_SEL_R 1 145*4882a593Smuzhiyun # define EVERGREEN_GRPH_ALPHA_SEL_G 2 146*4882a593Smuzhiyun # define EVERGREEN_GRPH_ALPHA_SEL_B 3 147*4882a593Smuzhiyun #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS 0x6810 148*4882a593Smuzhiyun #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS 0x6814 149*4882a593Smuzhiyun # define EVERGREEN_GRPH_DFQ_ENABLE (1 << 0) 150*4882a593Smuzhiyun # define EVERGREEN_GRPH_SURFACE_ADDRESS_MASK 0xffffff00 151*4882a593Smuzhiyun #define EVERGREEN_GRPH_PITCH 0x6818 152*4882a593Smuzhiyun #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x681c 153*4882a593Smuzhiyun #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x6820 154*4882a593Smuzhiyun #define EVERGREEN_GRPH_SURFACE_OFFSET_X 0x6824 155*4882a593Smuzhiyun #define EVERGREEN_GRPH_SURFACE_OFFSET_Y 0x6828 156*4882a593Smuzhiyun #define EVERGREEN_GRPH_X_START 0x682c 157*4882a593Smuzhiyun #define EVERGREEN_GRPH_Y_START 0x6830 158*4882a593Smuzhiyun #define EVERGREEN_GRPH_X_END 0x6834 159*4882a593Smuzhiyun #define EVERGREEN_GRPH_Y_END 0x6838 160*4882a593Smuzhiyun #define EVERGREEN_GRPH_UPDATE 0x6844 161*4882a593Smuzhiyun # define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING (1 << 2) 162*4882a593Smuzhiyun # define EVERGREEN_GRPH_UPDATE_LOCK (1 << 16) 163*4882a593Smuzhiyun #define EVERGREEN_GRPH_FLIP_CONTROL 0x6848 164*4882a593Smuzhiyun # define EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN (1 << 0) 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun /* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */ 167*4882a593Smuzhiyun #define EVERGREEN_CUR_CONTROL 0x6998 168*4882a593Smuzhiyun # define EVERGREEN_CURSOR_EN (1 << 0) 169*4882a593Smuzhiyun # define EVERGREEN_CURSOR_MODE(x) (((x) & 0x3) << 8) 170*4882a593Smuzhiyun # define EVERGREEN_CURSOR_MONO 0 171*4882a593Smuzhiyun # define EVERGREEN_CURSOR_24_1 1 172*4882a593Smuzhiyun # define EVERGREEN_CURSOR_24_8_PRE_MULT 2 173*4882a593Smuzhiyun # define EVERGREEN_CURSOR_24_8_UNPRE_MULT 3 174*4882a593Smuzhiyun # define EVERGREEN_CURSOR_2X_MAGNIFY (1 << 16) 175*4882a593Smuzhiyun # define EVERGREEN_CURSOR_FORCE_MC_ON (1 << 20) 176*4882a593Smuzhiyun # define EVERGREEN_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24) 177*4882a593Smuzhiyun # define EVERGREEN_CURSOR_URGENT_ALWAYS 0 178*4882a593Smuzhiyun # define EVERGREEN_CURSOR_URGENT_1_8 1 179*4882a593Smuzhiyun # define EVERGREEN_CURSOR_URGENT_1_4 2 180*4882a593Smuzhiyun # define EVERGREEN_CURSOR_URGENT_3_8 3 181*4882a593Smuzhiyun # define EVERGREEN_CURSOR_URGENT_1_2 4 182*4882a593Smuzhiyun #define EVERGREEN_CUR_SURFACE_ADDRESS 0x699c 183*4882a593Smuzhiyun # define EVERGREEN_CUR_SURFACE_ADDRESS_MASK 0xfffff000 184*4882a593Smuzhiyun #define EVERGREEN_CUR_SIZE 0x69a0 185*4882a593Smuzhiyun #define EVERGREEN_CUR_SURFACE_ADDRESS_HIGH 0x69a4 186*4882a593Smuzhiyun #define EVERGREEN_CUR_POSITION 0x69a8 187*4882a593Smuzhiyun #define EVERGREEN_CUR_HOT_SPOT 0x69ac 188*4882a593Smuzhiyun #define EVERGREEN_CUR_COLOR1 0x69b0 189*4882a593Smuzhiyun #define EVERGREEN_CUR_COLOR2 0x69b4 190*4882a593Smuzhiyun #define EVERGREEN_CUR_UPDATE 0x69b8 191*4882a593Smuzhiyun # define EVERGREEN_CURSOR_UPDATE_PENDING (1 << 0) 192*4882a593Smuzhiyun # define EVERGREEN_CURSOR_UPDATE_TAKEN (1 << 1) 193*4882a593Smuzhiyun # define EVERGREEN_CURSOR_UPDATE_LOCK (1 << 16) 194*4882a593Smuzhiyun # define EVERGREEN_CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24) 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun /* LUT blocks at 0x69e0, 0x75e0, 0x101e0, 0x10de0, 0x119e0, 0x125e0 */ 197*4882a593Smuzhiyun #define EVERGREEN_DC_LUT_RW_MODE 0x69e0 198*4882a593Smuzhiyun #define EVERGREEN_DC_LUT_RW_INDEX 0x69e4 199*4882a593Smuzhiyun #define EVERGREEN_DC_LUT_SEQ_COLOR 0x69e8 200*4882a593Smuzhiyun #define EVERGREEN_DC_LUT_PWL_DATA 0x69ec 201*4882a593Smuzhiyun #define EVERGREEN_DC_LUT_30_COLOR 0x69f0 202*4882a593Smuzhiyun #define EVERGREEN_DC_LUT_VGA_ACCESS_ENABLE 0x69f4 203*4882a593Smuzhiyun #define EVERGREEN_DC_LUT_WRITE_EN_MASK 0x69f8 204*4882a593Smuzhiyun #define EVERGREEN_DC_LUT_AUTOFILL 0x69fc 205*4882a593Smuzhiyun #define EVERGREEN_DC_LUT_CONTROL 0x6a00 206*4882a593Smuzhiyun #define EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE 0x6a04 207*4882a593Smuzhiyun #define EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN 0x6a08 208*4882a593Smuzhiyun #define EVERGREEN_DC_LUT_BLACK_OFFSET_RED 0x6a0c 209*4882a593Smuzhiyun #define EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE 0x6a10 210*4882a593Smuzhiyun #define EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN 0x6a14 211*4882a593Smuzhiyun #define EVERGREEN_DC_LUT_WHITE_OFFSET_RED 0x6a18 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun #define EVERGREEN_DATA_FORMAT 0x6b00 214*4882a593Smuzhiyun # define EVERGREEN_INTERLEAVE_EN (1 << 0) 215*4882a593Smuzhiyun #define EVERGREEN_DESKTOP_HEIGHT 0x6b04 216*4882a593Smuzhiyun #define EVERGREEN_VLINE_START_END 0x6b08 217*4882a593Smuzhiyun #define EVERGREEN_VLINE_STATUS 0x6bb8 218*4882a593Smuzhiyun # define EVERGREEN_VLINE_STAT (1 << 12) 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun #define EVERGREEN_VIEWPORT_START 0x6d70 221*4882a593Smuzhiyun #define EVERGREEN_VIEWPORT_SIZE 0x6d74 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun /* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */ 224*4882a593Smuzhiyun #define EVERGREEN_CRTC0_REGISTER_OFFSET (0x6df0 - 0x6df0) 225*4882a593Smuzhiyun #define EVERGREEN_CRTC1_REGISTER_OFFSET (0x79f0 - 0x6df0) 226*4882a593Smuzhiyun #define EVERGREEN_CRTC2_REGISTER_OFFSET (0x105f0 - 0x6df0) 227*4882a593Smuzhiyun #define EVERGREEN_CRTC3_REGISTER_OFFSET (0x111f0 - 0x6df0) 228*4882a593Smuzhiyun #define EVERGREEN_CRTC4_REGISTER_OFFSET (0x11df0 - 0x6df0) 229*4882a593Smuzhiyun #define EVERGREEN_CRTC5_REGISTER_OFFSET (0x129f0 - 0x6df0) 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun /* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */ 232*4882a593Smuzhiyun #define EVERGREEN_CRTC_V_BLANK_START_END 0x6e34 233*4882a593Smuzhiyun #define EVERGREEN_CRTC_CONTROL 0x6e70 234*4882a593Smuzhiyun # define EVERGREEN_CRTC_MASTER_EN (1 << 0) 235*4882a593Smuzhiyun # define EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE (1 << 24) 236*4882a593Smuzhiyun #define EVERGREEN_CRTC_BLANK_CONTROL 0x6e74 237*4882a593Smuzhiyun # define EVERGREEN_CRTC_BLANK_DATA_EN (1 << 8) 238*4882a593Smuzhiyun #define EVERGREEN_CRTC_STATUS 0x6e8c 239*4882a593Smuzhiyun # define EVERGREEN_CRTC_V_BLANK (1 << 0) 240*4882a593Smuzhiyun #define EVERGREEN_CRTC_STATUS_POSITION 0x6e90 241*4882a593Smuzhiyun #define EVERGREEN_CRTC_STATUS_HV_COUNT 0x6ea0 242*4882a593Smuzhiyun #define EVERGREEN_CRTC_UPDATE_LOCK 0x6ed4 243*4882a593Smuzhiyun #define EVERGREEN_MASTER_UPDATE_LOCK 0x6ef4 244*4882a593Smuzhiyun #define EVERGREEN_MASTER_UPDATE_MODE 0x6ef8 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun #define EVERGREEN_DC_GPIO_HPD_MASK 0x64b0 247*4882a593Smuzhiyun #define EVERGREEN_DC_GPIO_HPD_A 0x64b4 248*4882a593Smuzhiyun #define EVERGREEN_DC_GPIO_HPD_EN 0x64b8 249*4882a593Smuzhiyun #define EVERGREEN_DC_GPIO_HPD_Y 0x64bc 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun /* HDMI blocks at 0x7030, 0x7c30, 0x10830, 0x11430, 0x12030, 0x12c30 */ 252*4882a593Smuzhiyun #define EVERGREEN_HDMI_BASE 0x7030 253*4882a593Smuzhiyun /*DIG block*/ 254*4882a593Smuzhiyun #define NI_DIG0_REGISTER_OFFSET (0x7000 - 0x7000) 255*4882a593Smuzhiyun #define NI_DIG1_REGISTER_OFFSET (0x7C00 - 0x7000) 256*4882a593Smuzhiyun #define NI_DIG2_REGISTER_OFFSET (0x10800 - 0x7000) 257*4882a593Smuzhiyun #define NI_DIG3_REGISTER_OFFSET (0x11400 - 0x7000) 258*4882a593Smuzhiyun #define NI_DIG4_REGISTER_OFFSET (0x12000 - 0x7000) 259*4882a593Smuzhiyun #define NI_DIG5_REGISTER_OFFSET (0x12C00 - 0x7000) 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun #define NI_DIG_FE_CNTL 0x7000 263*4882a593Smuzhiyun # define NI_DIG_FE_CNTL_SOURCE_SELECT(x) ((x) & 0x3) 264*4882a593Smuzhiyun # define NI_DIG_FE_CNTL_SYMCLK_FE_ON (1<<24) 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun #define NI_DIG_BE_CNTL 0x7140 268*4882a593Smuzhiyun # define NI_DIG_BE_CNTL_FE_SOURCE_SELECT(x) (((x) >> 8 ) & 0x3F) 269*4882a593Smuzhiyun # define NI_DIG_FE_CNTL_MODE(x) (((x) >> 16) & 0x7 ) 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun #define NI_DIG_BE_EN_CNTL 0x7144 272*4882a593Smuzhiyun # define NI_DIG_BE_EN_CNTL_ENABLE (1 << 0) 273*4882a593Smuzhiyun # define NI_DIG_BE_EN_CNTL_SYMBCLK_ON (1 << 8) 274*4882a593Smuzhiyun # define NI_DIG_BE_DPSST 0 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun /* Display Port block */ 277*4882a593Smuzhiyun #define EVERGREEN_DP0_REGISTER_OFFSET (0x730C - 0x730C) 278*4882a593Smuzhiyun #define EVERGREEN_DP1_REGISTER_OFFSET (0x7F0C - 0x730C) 279*4882a593Smuzhiyun #define EVERGREEN_DP2_REGISTER_OFFSET (0x10B0C - 0x730C) 280*4882a593Smuzhiyun #define EVERGREEN_DP3_REGISTER_OFFSET (0x1170C - 0x730C) 281*4882a593Smuzhiyun #define EVERGREEN_DP4_REGISTER_OFFSET (0x1230C - 0x730C) 282*4882a593Smuzhiyun #define EVERGREEN_DP5_REGISTER_OFFSET (0x12F0C - 0x730C) 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun #define EVERGREEN_DP_VID_STREAM_CNTL 0x730C 286*4882a593Smuzhiyun # define EVERGREEN_DP_VID_STREAM_CNTL_ENABLE (1 << 0) 287*4882a593Smuzhiyun # define EVERGREEN_DP_VID_STREAM_STATUS (1 <<16) 288*4882a593Smuzhiyun #define EVERGREEN_DP_STEER_FIFO 0x7310 289*4882a593Smuzhiyun # define EVERGREEN_DP_STEER_FIFO_RESET (1 << 0) 290*4882a593Smuzhiyun #define EVERGREEN_DP_SEC_CNTL 0x7280 291*4882a593Smuzhiyun # define EVERGREEN_DP_SEC_STREAM_ENABLE (1 << 0) 292*4882a593Smuzhiyun # define EVERGREEN_DP_SEC_ASP_ENABLE (1 << 4) 293*4882a593Smuzhiyun # define EVERGREEN_DP_SEC_ATP_ENABLE (1 << 8) 294*4882a593Smuzhiyun # define EVERGREEN_DP_SEC_AIP_ENABLE (1 << 12) 295*4882a593Smuzhiyun # define EVERGREEN_DP_SEC_GSP_ENABLE (1 << 20) 296*4882a593Smuzhiyun # define EVERGREEN_DP_SEC_AVI_ENABLE (1 << 24) 297*4882a593Smuzhiyun # define EVERGREEN_DP_SEC_MPG_ENABLE (1 << 28) 298*4882a593Smuzhiyun #define EVERGREEN_DP_SEC_TIMESTAMP 0x72a4 299*4882a593Smuzhiyun # define EVERGREEN_DP_SEC_TIMESTAMP_MODE(x) (((x) & 0x3) << 0) 300*4882a593Smuzhiyun #define EVERGREEN_DP_SEC_AUD_N 0x7294 301*4882a593Smuzhiyun # define EVERGREEN_DP_SEC_N_BASE_MULTIPLE(x) (((x) & 0xf) << 24) 302*4882a593Smuzhiyun # define EVERGREEN_DP_SEC_SS_EN (1 << 28) 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun /*DCIO_UNIPHY block*/ 305*4882a593Smuzhiyun #define NI_DCIO_UNIPHY0_UNIPHY_TX_CONTROL1 (0x6600 -0x6600) 306*4882a593Smuzhiyun #define NI_DCIO_UNIPHY1_UNIPHY_TX_CONTROL1 (0x6640 -0x6600) 307*4882a593Smuzhiyun #define NI_DCIO_UNIPHY2_UNIPHY_TX_CONTROL1 (0x6680 - 0x6600) 308*4882a593Smuzhiyun #define NI_DCIO_UNIPHY3_UNIPHY_TX_CONTROL1 (0x66C0 - 0x6600) 309*4882a593Smuzhiyun #define NI_DCIO_UNIPHY4_UNIPHY_TX_CONTROL1 (0x6700 - 0x6600) 310*4882a593Smuzhiyun #define NI_DCIO_UNIPHY5_UNIPHY_TX_CONTROL1 (0x6740 - 0x6600) 311*4882a593Smuzhiyun 312*4882a593Smuzhiyun #define NI_DCIO_UNIPHY0_PLL_CONTROL1 0x6618 313*4882a593Smuzhiyun # define NI_DCIO_UNIPHY0_PLL_CONTROL1_ENABLE (1 << 0) 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun #endif 316