1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2011 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun #ifndef __CYPRESS_DPM_H__ 24*4882a593Smuzhiyun #define __CYPRESS_DPM_H__ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #include "rv770_dpm.h" 27*4882a593Smuzhiyun #include "evergreen_smc.h" 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun struct evergreen_mc_reg_entry { 30*4882a593Smuzhiyun u32 mclk_max; 31*4882a593Smuzhiyun u32 mc_data[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun struct evergreen_mc_reg_table { 35*4882a593Smuzhiyun u8 last; 36*4882a593Smuzhiyun u8 num_entries; 37*4882a593Smuzhiyun u16 valid_flag; 38*4882a593Smuzhiyun struct evergreen_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; 39*4882a593Smuzhiyun SMC_Evergreen_MCRegisterAddress mc_reg_address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun struct evergreen_ulv_param { 43*4882a593Smuzhiyun bool supported; 44*4882a593Smuzhiyun struct rv7xx_pl *pl; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun struct evergreen_arb_registers { 48*4882a593Smuzhiyun u32 mc_arb_dram_timing; 49*4882a593Smuzhiyun u32 mc_arb_dram_timing2; 50*4882a593Smuzhiyun u32 mc_arb_rfsh_rate; 51*4882a593Smuzhiyun u32 mc_arb_burst_time; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun struct at { 55*4882a593Smuzhiyun u32 rlp; 56*4882a593Smuzhiyun u32 rmp; 57*4882a593Smuzhiyun u32 lhp; 58*4882a593Smuzhiyun u32 lmp; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun struct evergreen_power_info { 62*4882a593Smuzhiyun /* must be first! */ 63*4882a593Smuzhiyun struct rv7xx_power_info rv7xx; 64*4882a593Smuzhiyun /* flags */ 65*4882a593Smuzhiyun bool vddci_control; 66*4882a593Smuzhiyun bool dynamic_ac_timing; 67*4882a593Smuzhiyun bool abm; 68*4882a593Smuzhiyun bool mcls; 69*4882a593Smuzhiyun bool light_sleep; 70*4882a593Smuzhiyun bool memory_transition; 71*4882a593Smuzhiyun bool pcie_performance_request; 72*4882a593Smuzhiyun bool pcie_performance_request_registered; 73*4882a593Smuzhiyun bool sclk_deep_sleep; 74*4882a593Smuzhiyun bool dll_default_on; 75*4882a593Smuzhiyun bool ls_clock_gating; 76*4882a593Smuzhiyun bool smu_uvd_hs; 77*4882a593Smuzhiyun bool uvd_enabled; 78*4882a593Smuzhiyun /* stored values */ 79*4882a593Smuzhiyun u16 acpi_vddci; 80*4882a593Smuzhiyun u8 mvdd_high_index; 81*4882a593Smuzhiyun u8 mvdd_low_index; 82*4882a593Smuzhiyun u32 mclk_edc_wr_enable_threshold; 83*4882a593Smuzhiyun struct evergreen_mc_reg_table mc_reg_table; 84*4882a593Smuzhiyun struct atom_voltage_table vddc_voltage_table; 85*4882a593Smuzhiyun struct atom_voltage_table vddci_voltage_table; 86*4882a593Smuzhiyun struct evergreen_arb_registers bootup_arb_registers; 87*4882a593Smuzhiyun struct evergreen_ulv_param ulv; 88*4882a593Smuzhiyun struct at ats[2]; 89*4882a593Smuzhiyun /* smc offsets */ 90*4882a593Smuzhiyun u16 mc_reg_table_start; 91*4882a593Smuzhiyun struct radeon_ps current_rps; 92*4882a593Smuzhiyun struct rv7xx_ps current_ps; 93*4882a593Smuzhiyun struct radeon_ps requested_rps; 94*4882a593Smuzhiyun struct rv7xx_ps requested_ps; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define CYPRESS_HASI_DFLT 400000 98*4882a593Smuzhiyun #define CYPRESS_MGCGTTLOCAL0_DFLT 0x00000000 99*4882a593Smuzhiyun #define CYPRESS_MGCGTTLOCAL1_DFLT 0x00000000 100*4882a593Smuzhiyun #define CYPRESS_MGCGTTLOCAL2_DFLT 0x00000000 101*4882a593Smuzhiyun #define CYPRESS_MGCGTTLOCAL3_DFLT 0x00000000 102*4882a593Smuzhiyun #define CYPRESS_MGCGCGTSSMCTRL_DFLT 0x81944bc0 103*4882a593Smuzhiyun #define REDWOOD_MGCGCGTSSMCTRL_DFLT 0x6e944040 104*4882a593Smuzhiyun #define CEDAR_MGCGCGTSSMCTRL_DFLT 0x46944040 105*4882a593Smuzhiyun #define CYPRESS_VRC_DFLT 0xC00033 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #define PCIE_PERF_REQ_REMOVE_REGISTRY 0 108*4882a593Smuzhiyun #define PCIE_PERF_REQ_FORCE_LOWPOWER 1 109*4882a593Smuzhiyun #define PCIE_PERF_REQ_PECI_GEN1 2 110*4882a593Smuzhiyun #define PCIE_PERF_REQ_PECI_GEN2 3 111*4882a593Smuzhiyun #define PCIE_PERF_REQ_PECI_GEN3 4 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun int cypress_convert_power_level_to_smc(struct radeon_device *rdev, 114*4882a593Smuzhiyun struct rv7xx_pl *pl, 115*4882a593Smuzhiyun RV770_SMC_HW_PERFORMANCE_LEVEL *level, 116*4882a593Smuzhiyun u8 watermark_level); 117*4882a593Smuzhiyun int cypress_populate_smc_acpi_state(struct radeon_device *rdev, 118*4882a593Smuzhiyun RV770_SMC_STATETABLE *table); 119*4882a593Smuzhiyun int cypress_populate_smc_voltage_tables(struct radeon_device *rdev, 120*4882a593Smuzhiyun RV770_SMC_STATETABLE *table); 121*4882a593Smuzhiyun int cypress_populate_smc_initial_state(struct radeon_device *rdev, 122*4882a593Smuzhiyun struct radeon_ps *radeon_initial_state, 123*4882a593Smuzhiyun RV770_SMC_STATETABLE *table); 124*4882a593Smuzhiyun u32 cypress_calculate_burst_time(struct radeon_device *rdev, 125*4882a593Smuzhiyun u32 engine_clock, u32 memory_clock); 126*4882a593Smuzhiyun void cypress_notify_link_speed_change_before_state_change(struct radeon_device *rdev, 127*4882a593Smuzhiyun struct radeon_ps *radeon_new_state, 128*4882a593Smuzhiyun struct radeon_ps *radeon_current_state); 129*4882a593Smuzhiyun int cypress_upload_sw_state(struct radeon_device *rdev, 130*4882a593Smuzhiyun struct radeon_ps *radeon_new_state); 131*4882a593Smuzhiyun int cypress_upload_mc_reg_table(struct radeon_device *rdev, 132*4882a593Smuzhiyun struct radeon_ps *radeon_new_state); 133*4882a593Smuzhiyun void cypress_program_memory_timing_parameters(struct radeon_device *rdev, 134*4882a593Smuzhiyun struct radeon_ps *radeon_new_state); 135*4882a593Smuzhiyun void cypress_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 136*4882a593Smuzhiyun struct radeon_ps *radeon_new_state, 137*4882a593Smuzhiyun struct radeon_ps *radeon_current_state); 138*4882a593Smuzhiyun int cypress_construct_voltage_tables(struct radeon_device *rdev); 139*4882a593Smuzhiyun int cypress_get_mvdd_configuration(struct radeon_device *rdev); 140*4882a593Smuzhiyun void cypress_enable_spread_spectrum(struct radeon_device *rdev, 141*4882a593Smuzhiyun bool enable); 142*4882a593Smuzhiyun void cypress_enable_display_gap(struct radeon_device *rdev); 143*4882a593Smuzhiyun int cypress_get_table_locations(struct radeon_device *rdev); 144*4882a593Smuzhiyun int cypress_populate_mc_reg_table(struct radeon_device *rdev, 145*4882a593Smuzhiyun struct radeon_ps *radeon_boot_state); 146*4882a593Smuzhiyun void cypress_program_response_times(struct radeon_device *rdev); 147*4882a593Smuzhiyun int cypress_notify_smc_display_change(struct radeon_device *rdev, 148*4882a593Smuzhiyun bool has_display); 149*4882a593Smuzhiyun void cypress_enable_sclk_control(struct radeon_device *rdev, 150*4882a593Smuzhiyun bool enable); 151*4882a593Smuzhiyun void cypress_enable_mclk_control(struct radeon_device *rdev, 152*4882a593Smuzhiyun bool enable); 153*4882a593Smuzhiyun void cypress_start_dpm(struct radeon_device *rdev); 154*4882a593Smuzhiyun void cypress_advertise_gen2_capability(struct radeon_device *rdev); 155*4882a593Smuzhiyun u32 cypress_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf); 156*4882a593Smuzhiyun u8 cypress_get_mclk_frequency_ratio(struct radeon_device *rdev, 157*4882a593Smuzhiyun u32 memory_clock, bool strobe_mode); 158*4882a593Smuzhiyun u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk); 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun #endif 161