xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/cayman_blit_shaders.c (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright 2010 Advanced Micro Devices, Inc.
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Permission is hereby granted, free of charge, to any person obtaining a
5*4882a593Smuzhiyun  * copy of this software and associated documentation files (the "Software"),
6*4882a593Smuzhiyun  * to deal in the Software without restriction, including without limitation
7*4882a593Smuzhiyun  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*4882a593Smuzhiyun  * and/or sell copies of the Software, and to permit persons to whom the
9*4882a593Smuzhiyun  * Software is furnished to do so, subject to the following conditions:
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * The above copyright notice and this permission notice (including the next
12*4882a593Smuzhiyun  * paragraph) shall be included in all copies or substantial portions of the
13*4882a593Smuzhiyun  * Software.
14*4882a593Smuzhiyun  *
15*4882a593Smuzhiyun  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16*4882a593Smuzhiyun  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18*4882a593Smuzhiyun  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19*4882a593Smuzhiyun  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20*4882a593Smuzhiyun  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21*4882a593Smuzhiyun  * DEALINGS IN THE SOFTWARE.
22*4882a593Smuzhiyun  *
23*4882a593Smuzhiyun  * Authors:
24*4882a593Smuzhiyun  *     Alex Deucher <alexander.deucher@amd.com>
25*4882a593Smuzhiyun  */
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #include <linux/bug.h>
28*4882a593Smuzhiyun #include <linux/types.h>
29*4882a593Smuzhiyun #include <linux/kernel.h>
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun /*
32*4882a593Smuzhiyun  * evergreen cards need to use the 3D engine to blit data which requires
33*4882a593Smuzhiyun  * quite a bit of hw state setup.  Rather than pull the whole 3D driver
34*4882a593Smuzhiyun  * (which normally generates the 3D state) into the DRM, we opt to use
35*4882a593Smuzhiyun  * statically generated state tables.  The register state and shaders
36*4882a593Smuzhiyun  * were hand generated to support blitting functionality.  See the 3D
37*4882a593Smuzhiyun  * driver or documentation for descriptions of the registers and
38*4882a593Smuzhiyun  * shader instructions.
39*4882a593Smuzhiyun  */
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun const u32 cayman_default_state[] =
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun 	0xc0066900,
44*4882a593Smuzhiyun 	0x00000000,
45*4882a593Smuzhiyun 	0x00000060, /* DB_RENDER_CONTROL */
46*4882a593Smuzhiyun 	0x00000000, /* DB_COUNT_CONTROL */
47*4882a593Smuzhiyun 	0x00000000, /* DB_DEPTH_VIEW */
48*4882a593Smuzhiyun 	0x0000002a, /* DB_RENDER_OVERRIDE */
49*4882a593Smuzhiyun 	0x00000000, /* DB_RENDER_OVERRIDE2 */
50*4882a593Smuzhiyun 	0x00000000, /* DB_HTILE_DATA_BASE */
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 	0xc0026900,
53*4882a593Smuzhiyun 	0x0000000a,
54*4882a593Smuzhiyun 	0x00000000, /* DB_STENCIL_CLEAR */
55*4882a593Smuzhiyun 	0x00000000, /* DB_DEPTH_CLEAR */
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	0xc0036900,
58*4882a593Smuzhiyun 	0x0000000f,
59*4882a593Smuzhiyun 	0x00000000, /* DB_DEPTH_INFO */
60*4882a593Smuzhiyun 	0x00000000, /* DB_Z_INFO */
61*4882a593Smuzhiyun 	0x00000000, /* DB_STENCIL_INFO */
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun 	0xc0016900,
64*4882a593Smuzhiyun 	0x00000080,
65*4882a593Smuzhiyun 	0x00000000, /* PA_SC_WINDOW_OFFSET */
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun 	0xc00d6900,
68*4882a593Smuzhiyun 	0x00000083,
69*4882a593Smuzhiyun 	0x0000ffff, /* PA_SC_CLIPRECT_RULE */
70*4882a593Smuzhiyun 	0x00000000, /* PA_SC_CLIPRECT_0_TL */
71*4882a593Smuzhiyun 	0x20002000, /* PA_SC_CLIPRECT_0_BR */
72*4882a593Smuzhiyun 	0x00000000,
73*4882a593Smuzhiyun 	0x20002000,
74*4882a593Smuzhiyun 	0x00000000,
75*4882a593Smuzhiyun 	0x20002000,
76*4882a593Smuzhiyun 	0x00000000,
77*4882a593Smuzhiyun 	0x20002000,
78*4882a593Smuzhiyun 	0xaaaaaaaa, /* PA_SC_EDGERULE */
79*4882a593Smuzhiyun 	0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */
80*4882a593Smuzhiyun 	0x0000000f, /* CB_TARGET_MASK */
81*4882a593Smuzhiyun 	0x0000000f, /* CB_SHADER_MASK */
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	0xc0226900,
84*4882a593Smuzhiyun 	0x00000094,
85*4882a593Smuzhiyun 	0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
86*4882a593Smuzhiyun 	0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
87*4882a593Smuzhiyun 	0x80000000,
88*4882a593Smuzhiyun 	0x20002000,
89*4882a593Smuzhiyun 	0x80000000,
90*4882a593Smuzhiyun 	0x20002000,
91*4882a593Smuzhiyun 	0x80000000,
92*4882a593Smuzhiyun 	0x20002000,
93*4882a593Smuzhiyun 	0x80000000,
94*4882a593Smuzhiyun 	0x20002000,
95*4882a593Smuzhiyun 	0x80000000,
96*4882a593Smuzhiyun 	0x20002000,
97*4882a593Smuzhiyun 	0x80000000,
98*4882a593Smuzhiyun 	0x20002000,
99*4882a593Smuzhiyun 	0x80000000,
100*4882a593Smuzhiyun 	0x20002000,
101*4882a593Smuzhiyun 	0x80000000,
102*4882a593Smuzhiyun 	0x20002000,
103*4882a593Smuzhiyun 	0x80000000,
104*4882a593Smuzhiyun 	0x20002000,
105*4882a593Smuzhiyun 	0x80000000,
106*4882a593Smuzhiyun 	0x20002000,
107*4882a593Smuzhiyun 	0x80000000,
108*4882a593Smuzhiyun 	0x20002000,
109*4882a593Smuzhiyun 	0x80000000,
110*4882a593Smuzhiyun 	0x20002000,
111*4882a593Smuzhiyun 	0x80000000,
112*4882a593Smuzhiyun 	0x20002000,
113*4882a593Smuzhiyun 	0x80000000,
114*4882a593Smuzhiyun 	0x20002000,
115*4882a593Smuzhiyun 	0x80000000,
116*4882a593Smuzhiyun 	0x20002000,
117*4882a593Smuzhiyun 	0x00000000, /* PA_SC_VPORT_ZMIN_0 */
118*4882a593Smuzhiyun 	0x3f800000, /* PA_SC_VPORT_ZMAX_0 */
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	0xc0016900,
121*4882a593Smuzhiyun 	0x000000d4,
122*4882a593Smuzhiyun 	0x00000000, /* SX_MISC */
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	0xc0026900,
125*4882a593Smuzhiyun 	0x000000d9,
126*4882a593Smuzhiyun 	0x00000000, /* CP_RINGID */
127*4882a593Smuzhiyun 	0x00000000, /* CP_VMID */
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	0xc0096900,
130*4882a593Smuzhiyun 	0x00000100,
131*4882a593Smuzhiyun 	0x00ffffff, /* VGT_MAX_VTX_INDX */
132*4882a593Smuzhiyun 	0x00000000, /* VGT_MIN_VTX_INDX */
133*4882a593Smuzhiyun 	0x00000000, /* VGT_INDX_OFFSET */
134*4882a593Smuzhiyun 	0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
135*4882a593Smuzhiyun 	0x00000000, /* SX_ALPHA_TEST_CONTROL */
136*4882a593Smuzhiyun 	0x00000000, /* CB_BLEND_RED */
137*4882a593Smuzhiyun 	0x00000000, /* CB_BLEND_GREEN */
138*4882a593Smuzhiyun 	0x00000000, /* CB_BLEND_BLUE */
139*4882a593Smuzhiyun 	0x00000000, /* CB_BLEND_ALPHA */
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	0xc0016900,
142*4882a593Smuzhiyun 	0x00000187,
143*4882a593Smuzhiyun 	0x00000100, /* SPI_VS_OUT_ID_0 */
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	0xc0026900,
146*4882a593Smuzhiyun 	0x00000191,
147*4882a593Smuzhiyun 	0x00000100, /* SPI_PS_INPUT_CNTL_0 */
148*4882a593Smuzhiyun 	0x00000101, /* SPI_PS_INPUT_CNTL_1 */
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	0xc0016900,
151*4882a593Smuzhiyun 	0x000001b1,
152*4882a593Smuzhiyun 	0x00000000, /* SPI_VS_OUT_CONFIG */
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	0xc0106900,
155*4882a593Smuzhiyun 	0x000001b3,
156*4882a593Smuzhiyun 	0x20000001, /* SPI_PS_IN_CONTROL_0 */
157*4882a593Smuzhiyun 	0x00000000, /* SPI_PS_IN_CONTROL_1 */
158*4882a593Smuzhiyun 	0x00000000, /* SPI_INTERP_CONTROL_0 */
159*4882a593Smuzhiyun 	0x00000000, /* SPI_INPUT_Z */
160*4882a593Smuzhiyun 	0x00000000, /* SPI_FOG_CNTL */
161*4882a593Smuzhiyun 	0x00100000, /* SPI_BARYC_CNTL */
162*4882a593Smuzhiyun 	0x00000000, /* SPI_PS_IN_CONTROL_2 */
163*4882a593Smuzhiyun 	0x00000000, /* SPI_COMPUTE_INPUT_CNTL */
164*4882a593Smuzhiyun 	0x00000000, /* SPI_COMPUTE_NUM_THREAD_X */
165*4882a593Smuzhiyun 	0x00000000, /* SPI_COMPUTE_NUM_THREAD_Y */
166*4882a593Smuzhiyun 	0x00000000, /* SPI_COMPUTE_NUM_THREAD_Z */
167*4882a593Smuzhiyun 	0x00000000, /* SPI_GPR_MGMT */
168*4882a593Smuzhiyun 	0x00000000, /* SPI_LDS_MGMT */
169*4882a593Smuzhiyun 	0x00000000, /* SPI_STACK_MGMT */
170*4882a593Smuzhiyun 	0x00000000, /* SPI_WAVE_MGMT_1 */
171*4882a593Smuzhiyun 	0x00000000, /* SPI_WAVE_MGMT_2 */
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	0xc0016900,
174*4882a593Smuzhiyun 	0x000001e0,
175*4882a593Smuzhiyun 	0x00000000, /* CB_BLEND0_CONTROL */
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	0xc00e6900,
178*4882a593Smuzhiyun 	0x00000200,
179*4882a593Smuzhiyun 	0x00000000, /* DB_DEPTH_CONTROL */
180*4882a593Smuzhiyun 	0x00000000, /* DB_EQAA */
181*4882a593Smuzhiyun 	0x00cc0010, /* CB_COLOR_CONTROL */
182*4882a593Smuzhiyun 	0x00000210, /* DB_SHADER_CONTROL */
183*4882a593Smuzhiyun 	0x00010000, /* PA_CL_CLIP_CNTL */
184*4882a593Smuzhiyun 	0x00000004, /* PA_SU_SC_MODE_CNTL */
185*4882a593Smuzhiyun 	0x00000100, /* PA_CL_VTE_CNTL */
186*4882a593Smuzhiyun 	0x00000000, /* PA_CL_VS_OUT_CNTL */
187*4882a593Smuzhiyun 	0x00000000, /* PA_CL_NANINF_CNTL */
188*4882a593Smuzhiyun 	0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */
189*4882a593Smuzhiyun 	0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */
190*4882a593Smuzhiyun 	0x00000000, /* PA_SU_PRIM_FILTER_CNTL */
191*4882a593Smuzhiyun 	0x00000000, /*  */
192*4882a593Smuzhiyun 	0x00000000, /*  */
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 	0xc0026900,
195*4882a593Smuzhiyun 	0x00000229,
196*4882a593Smuzhiyun 	0x00000000, /* SQ_PGM_START_FS */
197*4882a593Smuzhiyun 	0x00000000,
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	0xc0016900,
200*4882a593Smuzhiyun 	0x0000023b,
201*4882a593Smuzhiyun 	0x00000000, /* SQ_LDS_ALLOC_PS */
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	0xc0066900,
204*4882a593Smuzhiyun 	0x00000240,
205*4882a593Smuzhiyun 	0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
206*4882a593Smuzhiyun 	0x00000000,
207*4882a593Smuzhiyun 	0x00000000,
208*4882a593Smuzhiyun 	0x00000000,
209*4882a593Smuzhiyun 	0x00000000,
210*4882a593Smuzhiyun 	0x00000000,
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 	0xc0046900,
213*4882a593Smuzhiyun 	0x00000247,
214*4882a593Smuzhiyun 	0x00000000, /* SQ_GS_VERT_ITEMSIZE */
215*4882a593Smuzhiyun 	0x00000000,
216*4882a593Smuzhiyun 	0x00000000,
217*4882a593Smuzhiyun 	0x00000000,
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun 	0xc0116900,
220*4882a593Smuzhiyun 	0x00000280,
221*4882a593Smuzhiyun 	0x00000000, /* PA_SU_POINT_SIZE */
222*4882a593Smuzhiyun 	0x00000000, /* PA_SU_POINT_MINMAX */
223*4882a593Smuzhiyun 	0x00000008, /* PA_SU_LINE_CNTL */
224*4882a593Smuzhiyun 	0x00000000, /* PA_SC_LINE_STIPPLE */
225*4882a593Smuzhiyun 	0x00000000, /* VGT_OUTPUT_PATH_CNTL */
226*4882a593Smuzhiyun 	0x00000000, /* VGT_HOS_CNTL */
227*4882a593Smuzhiyun 	0x00000000,
228*4882a593Smuzhiyun 	0x00000000,
229*4882a593Smuzhiyun 	0x00000000,
230*4882a593Smuzhiyun 	0x00000000,
231*4882a593Smuzhiyun 	0x00000000,
232*4882a593Smuzhiyun 	0x00000000,
233*4882a593Smuzhiyun 	0x00000000,
234*4882a593Smuzhiyun 	0x00000000,
235*4882a593Smuzhiyun 	0x00000000,
236*4882a593Smuzhiyun 	0x00000000,
237*4882a593Smuzhiyun 	0x00000000, /* VGT_GS_MODE */
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun 	0xc0026900,
240*4882a593Smuzhiyun 	0x00000292,
241*4882a593Smuzhiyun 	0x00000000, /* PA_SC_MODE_CNTL_0 */
242*4882a593Smuzhiyun 	0x00000000, /* PA_SC_MODE_CNTL_1 */
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	0xc0016900,
245*4882a593Smuzhiyun 	0x000002a1,
246*4882a593Smuzhiyun 	0x00000000, /* VGT_PRIMITIVEID_EN */
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	0xc0016900,
249*4882a593Smuzhiyun 	0x000002a5,
250*4882a593Smuzhiyun 	0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 	0xc0026900,
253*4882a593Smuzhiyun 	0x000002a8,
254*4882a593Smuzhiyun 	0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
255*4882a593Smuzhiyun 	0x00000000,
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	0xc0026900,
258*4882a593Smuzhiyun 	0x000002ad,
259*4882a593Smuzhiyun 	0x00000000, /* VGT_REUSE_OFF */
260*4882a593Smuzhiyun 	0x00000000,
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 	0xc0016900,
263*4882a593Smuzhiyun 	0x000002d5,
264*4882a593Smuzhiyun 	0x00000000, /* VGT_SHADER_STAGES_EN */
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	0xc0016900,
267*4882a593Smuzhiyun 	0x000002dc,
268*4882a593Smuzhiyun 	0x0000aa00, /* DB_ALPHA_TO_MASK */
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun 	0xc0066900,
271*4882a593Smuzhiyun 	0x000002de,
272*4882a593Smuzhiyun 	0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
273*4882a593Smuzhiyun 	0x00000000,
274*4882a593Smuzhiyun 	0x00000000,
275*4882a593Smuzhiyun 	0x00000000,
276*4882a593Smuzhiyun 	0x00000000,
277*4882a593Smuzhiyun 	0x00000000,
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	0xc0026900,
280*4882a593Smuzhiyun 	0x000002e5,
281*4882a593Smuzhiyun 	0x00000000, /* VGT_STRMOUT_CONFIG */
282*4882a593Smuzhiyun 	0x00000000,
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun 	0xc01b6900,
285*4882a593Smuzhiyun 	0x000002f5,
286*4882a593Smuzhiyun 	0x76543210, /* PA_SC_CENTROID_PRIORITY_0 */
287*4882a593Smuzhiyun 	0xfedcba98, /* PA_SC_CENTROID_PRIORITY_1 */
288*4882a593Smuzhiyun 	0x00000000, /* PA_SC_LINE_CNTL */
289*4882a593Smuzhiyun 	0x00000000, /* PA_SC_AA_CONFIG */
290*4882a593Smuzhiyun 	0x00000005, /* PA_SU_VTX_CNTL */
291*4882a593Smuzhiyun 	0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
292*4882a593Smuzhiyun 	0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */
293*4882a593Smuzhiyun 	0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */
294*4882a593Smuzhiyun 	0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */
295*4882a593Smuzhiyun 	0x00000000, /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */
296*4882a593Smuzhiyun 	0x00000000,
297*4882a593Smuzhiyun 	0x00000000,
298*4882a593Smuzhiyun 	0x00000000,
299*4882a593Smuzhiyun 	0x00000000,
300*4882a593Smuzhiyun 	0x00000000,
301*4882a593Smuzhiyun 	0x00000000,
302*4882a593Smuzhiyun 	0x00000000,
303*4882a593Smuzhiyun 	0x00000000,
304*4882a593Smuzhiyun 	0x00000000,
305*4882a593Smuzhiyun 	0x00000000,
306*4882a593Smuzhiyun 	0x00000000,
307*4882a593Smuzhiyun 	0x00000000,
308*4882a593Smuzhiyun 	0x00000000,
309*4882a593Smuzhiyun 	0x00000000,
310*4882a593Smuzhiyun 	0x00000000,
311*4882a593Smuzhiyun 	0xffffffff, /* PA_SC_AA_MASK_X0Y0_X1Y0 */
312*4882a593Smuzhiyun 	0xffffffff,
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun 	0xc0026900,
315*4882a593Smuzhiyun 	0x00000316,
316*4882a593Smuzhiyun 	0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
317*4882a593Smuzhiyun 	0x00000010, /*  */
318*4882a593Smuzhiyun };
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun const u32 cayman_default_size = ARRAY_SIZE(cayman_default_state);
321