1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2010 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * Authors: Alex Deucher 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun #ifndef _BTCD_H_ 25*4882a593Smuzhiyun #define _BTCD_H_ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* pm registers */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define GENERAL_PWRMGT 0x63c 30*4882a593Smuzhiyun # define GLOBAL_PWRMGT_EN (1 << 0) 31*4882a593Smuzhiyun # define STATIC_PM_EN (1 << 1) 32*4882a593Smuzhiyun # define THERMAL_PROTECTION_DIS (1 << 2) 33*4882a593Smuzhiyun # define THERMAL_PROTECTION_TYPE (1 << 3) 34*4882a593Smuzhiyun # define ENABLE_GEN2PCIE (1 << 4) 35*4882a593Smuzhiyun # define ENABLE_GEN2XSP (1 << 5) 36*4882a593Smuzhiyun # define SW_SMIO_INDEX(x) ((x) << 6) 37*4882a593Smuzhiyun # define SW_SMIO_INDEX_MASK (3 << 6) 38*4882a593Smuzhiyun # define SW_SMIO_INDEX_SHIFT 6 39*4882a593Smuzhiyun # define LOW_VOLT_D2_ACPI (1 << 8) 40*4882a593Smuzhiyun # define LOW_VOLT_D3_ACPI (1 << 9) 41*4882a593Smuzhiyun # define VOLT_PWRMGT_EN (1 << 10) 42*4882a593Smuzhiyun # define BACKBIAS_PAD_EN (1 << 18) 43*4882a593Smuzhiyun # define BACKBIAS_VALUE (1 << 19) 44*4882a593Smuzhiyun # define DYN_SPREAD_SPECTRUM_EN (1 << 23) 45*4882a593Smuzhiyun # define AC_DC_SW (1 << 24) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define TARGET_AND_CURRENT_PROFILE_INDEX 0x66c 48*4882a593Smuzhiyun # define CURRENT_PROFILE_INDEX_MASK (0xf << 4) 49*4882a593Smuzhiyun # define CURRENT_PROFILE_INDEX_SHIFT 4 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define CG_BIF_REQ_AND_RSP 0x7f4 52*4882a593Smuzhiyun #define CG_CLIENT_REQ(x) ((x) << 0) 53*4882a593Smuzhiyun #define CG_CLIENT_REQ_MASK (0xff << 0) 54*4882a593Smuzhiyun #define CG_CLIENT_REQ_SHIFT 0 55*4882a593Smuzhiyun #define CG_CLIENT_RESP(x) ((x) << 8) 56*4882a593Smuzhiyun #define CG_CLIENT_RESP_MASK (0xff << 8) 57*4882a593Smuzhiyun #define CG_CLIENT_RESP_SHIFT 8 58*4882a593Smuzhiyun #define CLIENT_CG_REQ(x) ((x) << 16) 59*4882a593Smuzhiyun #define CLIENT_CG_REQ_MASK (0xff << 16) 60*4882a593Smuzhiyun #define CLIENT_CG_REQ_SHIFT 16 61*4882a593Smuzhiyun #define CLIENT_CG_RESP(x) ((x) << 24) 62*4882a593Smuzhiyun #define CLIENT_CG_RESP_MASK (0xff << 24) 63*4882a593Smuzhiyun #define CLIENT_CG_RESP_SHIFT 24 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define SCLK_PSKIP_CNTL 0x8c0 66*4882a593Smuzhiyun #define PSKIP_ON_ALLOW_STOP_HI(x) ((x) << 16) 67*4882a593Smuzhiyun #define PSKIP_ON_ALLOW_STOP_HI_MASK (0xff << 16) 68*4882a593Smuzhiyun #define PSKIP_ON_ALLOW_STOP_HI_SHIFT 16 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define CG_ULV_CONTROL 0x8c8 71*4882a593Smuzhiyun #define CG_ULV_PARAMETER 0x8cc 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define MC_ARB_DRAM_TIMING 0x2774 74*4882a593Smuzhiyun #define MC_ARB_DRAM_TIMING2 0x2778 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define MC_ARB_RFSH_RATE 0x27b0 77*4882a593Smuzhiyun #define POWERMODE0(x) ((x) << 0) 78*4882a593Smuzhiyun #define POWERMODE0_MASK (0xff << 0) 79*4882a593Smuzhiyun #define POWERMODE0_SHIFT 0 80*4882a593Smuzhiyun #define POWERMODE1(x) ((x) << 8) 81*4882a593Smuzhiyun #define POWERMODE1_MASK (0xff << 8) 82*4882a593Smuzhiyun #define POWERMODE1_SHIFT 8 83*4882a593Smuzhiyun #define POWERMODE2(x) ((x) << 16) 84*4882a593Smuzhiyun #define POWERMODE2_MASK (0xff << 16) 85*4882a593Smuzhiyun #define POWERMODE2_SHIFT 16 86*4882a593Smuzhiyun #define POWERMODE3(x) ((x) << 24) 87*4882a593Smuzhiyun #define POWERMODE3_MASK (0xff << 24) 88*4882a593Smuzhiyun #define POWERMODE3_SHIFT 24 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define MC_ARB_BURST_TIME 0x2808 91*4882a593Smuzhiyun #define STATE0(x) ((x) << 0) 92*4882a593Smuzhiyun #define STATE0_MASK (0x1f << 0) 93*4882a593Smuzhiyun #define STATE0_SHIFT 0 94*4882a593Smuzhiyun #define STATE1(x) ((x) << 5) 95*4882a593Smuzhiyun #define STATE1_MASK (0x1f << 5) 96*4882a593Smuzhiyun #define STATE1_SHIFT 5 97*4882a593Smuzhiyun #define STATE2(x) ((x) << 10) 98*4882a593Smuzhiyun #define STATE2_MASK (0x1f << 10) 99*4882a593Smuzhiyun #define STATE2_SHIFT 10 100*4882a593Smuzhiyun #define STATE3(x) ((x) << 15) 101*4882a593Smuzhiyun #define STATE3_MASK (0x1f << 15) 102*4882a593Smuzhiyun #define STATE3_SHIFT 15 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define MC_SEQ_RAS_TIMING 0x28a0 105*4882a593Smuzhiyun #define MC_SEQ_CAS_TIMING 0x28a4 106*4882a593Smuzhiyun #define MC_SEQ_MISC_TIMING 0x28a8 107*4882a593Smuzhiyun #define MC_SEQ_MISC_TIMING2 0x28ac 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #define MC_SEQ_RD_CTL_D0 0x28b4 110*4882a593Smuzhiyun #define MC_SEQ_RD_CTL_D1 0x28b8 111*4882a593Smuzhiyun #define MC_SEQ_WR_CTL_D0 0x28bc 112*4882a593Smuzhiyun #define MC_SEQ_WR_CTL_D1 0x28c0 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #define MC_PMG_AUTO_CFG 0x28d4 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #define MC_SEQ_STATUS_M 0x29f4 117*4882a593Smuzhiyun # define PMG_PWRSTATE (1 << 16) 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define MC_SEQ_MISC0 0x2a00 120*4882a593Smuzhiyun #define MC_SEQ_MISC0_GDDR5_SHIFT 28 121*4882a593Smuzhiyun #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 122*4882a593Smuzhiyun #define MC_SEQ_MISC0_GDDR5_VALUE 5 123*4882a593Smuzhiyun #define MC_SEQ_MISC1 0x2a04 124*4882a593Smuzhiyun #define MC_SEQ_RESERVE_M 0x2a08 125*4882a593Smuzhiyun #define MC_PMG_CMD_EMRS 0x2a0c 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #define MC_SEQ_MISC3 0x2a2c 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #define MC_SEQ_MISC5 0x2a54 130*4882a593Smuzhiyun #define MC_SEQ_MISC6 0x2a58 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #define MC_SEQ_MISC7 0x2a64 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #define MC_SEQ_CG 0x2a68 135*4882a593Smuzhiyun #define CG_SEQ_REQ(x) ((x) << 0) 136*4882a593Smuzhiyun #define CG_SEQ_REQ_MASK (0xff << 0) 137*4882a593Smuzhiyun #define CG_SEQ_REQ_SHIFT 0 138*4882a593Smuzhiyun #define CG_SEQ_RESP(x) ((x) << 8) 139*4882a593Smuzhiyun #define CG_SEQ_RESP_MASK (0xff << 8) 140*4882a593Smuzhiyun #define CG_SEQ_RESP_SHIFT 8 141*4882a593Smuzhiyun #define SEQ_CG_REQ(x) ((x) << 16) 142*4882a593Smuzhiyun #define SEQ_CG_REQ_MASK (0xff << 16) 143*4882a593Smuzhiyun #define SEQ_CG_REQ_SHIFT 16 144*4882a593Smuzhiyun #define SEQ_CG_RESP(x) ((x) << 24) 145*4882a593Smuzhiyun #define SEQ_CG_RESP_MASK (0xff << 24) 146*4882a593Smuzhiyun #define SEQ_CG_RESP_SHIFT 24 147*4882a593Smuzhiyun #define MC_SEQ_RAS_TIMING_LP 0x2a6c 148*4882a593Smuzhiyun #define MC_SEQ_CAS_TIMING_LP 0x2a70 149*4882a593Smuzhiyun #define MC_SEQ_MISC_TIMING_LP 0x2a74 150*4882a593Smuzhiyun #define MC_SEQ_MISC_TIMING2_LP 0x2a78 151*4882a593Smuzhiyun #define MC_SEQ_WR_CTL_D0_LP 0x2a7c 152*4882a593Smuzhiyun #define MC_SEQ_WR_CTL_D1_LP 0x2a80 153*4882a593Smuzhiyun #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84 154*4882a593Smuzhiyun #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun #define MC_PMG_CMD_MRS 0x2aac 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun #define MC_SEQ_RD_CTL_D0_LP 0x2b1c 159*4882a593Smuzhiyun #define MC_SEQ_RD_CTL_D1_LP 0x2b20 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun #define MC_PMG_CMD_MRS1 0x2b44 162*4882a593Smuzhiyun #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun #define LB_SYNC_RESET_SEL 0x6b28 165*4882a593Smuzhiyun #define LB_SYNC_RESET_SEL_MASK (3 << 0) 166*4882a593Smuzhiyun #define LB_SYNC_RESET_SEL_SHIFT 0 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun /* PCIE link stuff */ 169*4882a593Smuzhiyun #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 170*4882a593Smuzhiyun # define LC_GEN2_EN_STRAP (1 << 0) 171*4882a593Smuzhiyun # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 172*4882a593Smuzhiyun # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 173*4882a593Smuzhiyun # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 174*4882a593Smuzhiyun # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 175*4882a593Smuzhiyun # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 176*4882a593Smuzhiyun # define LC_CURRENT_DATA_RATE (1 << 11) 177*4882a593Smuzhiyun # define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12) 178*4882a593Smuzhiyun # define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12) 179*4882a593Smuzhiyun # define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12 180*4882a593Smuzhiyun # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 181*4882a593Smuzhiyun # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 182*4882a593Smuzhiyun # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 183*4882a593Smuzhiyun # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun #endif 186