1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2013 Red Hat Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a
5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"),
6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation
7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the
9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions:
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in
12*4882a593Smuzhiyun * all copies or substantial portions of the Software.
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE.
21*4882a593Smuzhiyun *
22*4882a593Smuzhiyun * Authors: Dave Airlie
23*4882a593Smuzhiyun * Alon Levy
24*4882a593Smuzhiyun */
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #include <linux/io-mapping.h>
27*4882a593Smuzhiyun #include <linux/pci.h>
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #include <drm/drm_drv.h>
30*4882a593Smuzhiyun #include <drm/drm_managed.h>
31*4882a593Smuzhiyun #include <drm/drm_probe_helper.h>
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #include "qxl_drv.h"
34*4882a593Smuzhiyun #include "qxl_object.h"
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun int qxl_log_level;
37*4882a593Smuzhiyun
qxl_check_device(struct qxl_device * qdev)38*4882a593Smuzhiyun static bool qxl_check_device(struct qxl_device *qdev)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun struct qxl_rom *rom = qdev->rom;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun if (rom->magic != 0x4f525851) {
43*4882a593Smuzhiyun DRM_ERROR("bad rom signature %x\n", rom->magic);
44*4882a593Smuzhiyun return false;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun DRM_INFO("Device Version %d.%d\n", rom->id, rom->update_id);
48*4882a593Smuzhiyun DRM_INFO("Compression level %d log level %d\n", rom->compression_level,
49*4882a593Smuzhiyun rom->log_level);
50*4882a593Smuzhiyun DRM_INFO("%d io pages at offset 0x%x\n",
51*4882a593Smuzhiyun rom->num_io_pages, rom->pages_offset);
52*4882a593Smuzhiyun DRM_INFO("%d byte draw area at offset 0x%x\n",
53*4882a593Smuzhiyun rom->surface0_area_size, rom->draw_area_offset);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun qdev->vram_size = rom->surface0_area_size;
56*4882a593Smuzhiyun DRM_INFO("RAM header offset: 0x%x\n", rom->ram_header_offset);
57*4882a593Smuzhiyun return true;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
setup_hw_slot(struct qxl_device * qdev,struct qxl_memslot * slot)60*4882a593Smuzhiyun static void setup_hw_slot(struct qxl_device *qdev, struct qxl_memslot *slot)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun qdev->ram_header->mem_slot.mem_start = slot->start_phys_addr;
63*4882a593Smuzhiyun qdev->ram_header->mem_slot.mem_end = slot->start_phys_addr + slot->size;
64*4882a593Smuzhiyun qxl_io_memslot_add(qdev, qdev->rom->slots_start + slot->index);
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
setup_slot(struct qxl_device * qdev,struct qxl_memslot * slot,unsigned int slot_index,const char * slot_name,unsigned long start_phys_addr,unsigned long size)67*4882a593Smuzhiyun static void setup_slot(struct qxl_device *qdev,
68*4882a593Smuzhiyun struct qxl_memslot *slot,
69*4882a593Smuzhiyun unsigned int slot_index,
70*4882a593Smuzhiyun const char *slot_name,
71*4882a593Smuzhiyun unsigned long start_phys_addr,
72*4882a593Smuzhiyun unsigned long size)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun uint64_t high_bits;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun slot->index = slot_index;
77*4882a593Smuzhiyun slot->name = slot_name;
78*4882a593Smuzhiyun slot->start_phys_addr = start_phys_addr;
79*4882a593Smuzhiyun slot->size = size;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun setup_hw_slot(qdev, slot);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun slot->generation = qdev->rom->slot_generation;
84*4882a593Smuzhiyun high_bits = (qdev->rom->slots_start + slot->index)
85*4882a593Smuzhiyun << qdev->rom->slot_gen_bits;
86*4882a593Smuzhiyun high_bits |= slot->generation;
87*4882a593Smuzhiyun high_bits <<= (64 - (qdev->rom->slot_gen_bits + qdev->rom->slot_id_bits));
88*4882a593Smuzhiyun slot->high_bits = high_bits;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun DRM_INFO("slot %d (%s): base 0x%08lx, size 0x%08lx\n",
91*4882a593Smuzhiyun slot->index, slot->name,
92*4882a593Smuzhiyun (unsigned long)slot->start_phys_addr,
93*4882a593Smuzhiyun (unsigned long)slot->size);
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
qxl_reinit_memslots(struct qxl_device * qdev)96*4882a593Smuzhiyun void qxl_reinit_memslots(struct qxl_device *qdev)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun setup_hw_slot(qdev, &qdev->main_slot);
99*4882a593Smuzhiyun setup_hw_slot(qdev, &qdev->surfaces_slot);
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
qxl_gc_work(struct work_struct * work)102*4882a593Smuzhiyun static void qxl_gc_work(struct work_struct *work)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun struct qxl_device *qdev = container_of(work, struct qxl_device, gc_work);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun qxl_garbage_collect(qdev);
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
qxl_device_init(struct qxl_device * qdev,struct pci_dev * pdev)109*4882a593Smuzhiyun int qxl_device_init(struct qxl_device *qdev,
110*4882a593Smuzhiyun struct pci_dev *pdev)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun int r, sb;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun qdev->ddev.pdev = pdev;
115*4882a593Smuzhiyun pci_set_drvdata(pdev, &qdev->ddev);
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun mutex_init(&qdev->gem.mutex);
118*4882a593Smuzhiyun mutex_init(&qdev->update_area_mutex);
119*4882a593Smuzhiyun mutex_init(&qdev->release_mutex);
120*4882a593Smuzhiyun mutex_init(&qdev->surf_evict_mutex);
121*4882a593Smuzhiyun qxl_gem_init(qdev);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun qdev->rom_base = pci_resource_start(pdev, 2);
124*4882a593Smuzhiyun qdev->rom_size = pci_resource_len(pdev, 2);
125*4882a593Smuzhiyun qdev->vram_base = pci_resource_start(pdev, 0);
126*4882a593Smuzhiyun qdev->io_base = pci_resource_start(pdev, 3);
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun qdev->vram_mapping = io_mapping_create_wc(qdev->vram_base, pci_resource_len(pdev, 0));
129*4882a593Smuzhiyun if (!qdev->vram_mapping) {
130*4882a593Smuzhiyun pr_err("Unable to create vram_mapping");
131*4882a593Smuzhiyun return -ENOMEM;
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun if (pci_resource_len(pdev, 4) > 0) {
135*4882a593Smuzhiyun /* 64bit surface bar present */
136*4882a593Smuzhiyun sb = 4;
137*4882a593Smuzhiyun qdev->surfaceram_base = pci_resource_start(pdev, sb);
138*4882a593Smuzhiyun qdev->surfaceram_size = pci_resource_len(pdev, sb);
139*4882a593Smuzhiyun qdev->surface_mapping =
140*4882a593Smuzhiyun io_mapping_create_wc(qdev->surfaceram_base,
141*4882a593Smuzhiyun qdev->surfaceram_size);
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun if (qdev->surface_mapping == NULL) {
144*4882a593Smuzhiyun /* 64bit surface bar not present (or mapping failed) */
145*4882a593Smuzhiyun sb = 1;
146*4882a593Smuzhiyun qdev->surfaceram_base = pci_resource_start(pdev, sb);
147*4882a593Smuzhiyun qdev->surfaceram_size = pci_resource_len(pdev, sb);
148*4882a593Smuzhiyun qdev->surface_mapping =
149*4882a593Smuzhiyun io_mapping_create_wc(qdev->surfaceram_base,
150*4882a593Smuzhiyun qdev->surfaceram_size);
151*4882a593Smuzhiyun if (!qdev->surface_mapping) {
152*4882a593Smuzhiyun pr_err("Unable to create surface_mapping");
153*4882a593Smuzhiyun r = -ENOMEM;
154*4882a593Smuzhiyun goto vram_mapping_free;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun DRM_DEBUG_KMS("qxl: vram %llx-%llx(%dM %dk), surface %llx-%llx(%dM %dk, %s)\n",
159*4882a593Smuzhiyun (unsigned long long)qdev->vram_base,
160*4882a593Smuzhiyun (unsigned long long)pci_resource_end(pdev, 0),
161*4882a593Smuzhiyun (int)pci_resource_len(pdev, 0) / 1024 / 1024,
162*4882a593Smuzhiyun (int)pci_resource_len(pdev, 0) / 1024,
163*4882a593Smuzhiyun (unsigned long long)qdev->surfaceram_base,
164*4882a593Smuzhiyun (unsigned long long)pci_resource_end(pdev, sb),
165*4882a593Smuzhiyun (int)qdev->surfaceram_size / 1024 / 1024,
166*4882a593Smuzhiyun (int)qdev->surfaceram_size / 1024,
167*4882a593Smuzhiyun (sb == 4) ? "64bit" : "32bit");
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun qdev->rom = ioremap(qdev->rom_base, qdev->rom_size);
170*4882a593Smuzhiyun if (!qdev->rom) {
171*4882a593Smuzhiyun pr_err("Unable to ioremap ROM\n");
172*4882a593Smuzhiyun r = -ENOMEM;
173*4882a593Smuzhiyun goto surface_mapping_free;
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun if (!qxl_check_device(qdev)) {
177*4882a593Smuzhiyun r = -ENODEV;
178*4882a593Smuzhiyun goto rom_unmap;
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun r = qxl_bo_init(qdev);
182*4882a593Smuzhiyun if (r) {
183*4882a593Smuzhiyun DRM_ERROR("bo init failed %d\n", r);
184*4882a593Smuzhiyun goto rom_unmap;
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun qdev->ram_header = ioremap(qdev->vram_base +
188*4882a593Smuzhiyun qdev->rom->ram_header_offset,
189*4882a593Smuzhiyun sizeof(*qdev->ram_header));
190*4882a593Smuzhiyun if (!qdev->ram_header) {
191*4882a593Smuzhiyun DRM_ERROR("Unable to ioremap RAM header\n");
192*4882a593Smuzhiyun r = -ENOMEM;
193*4882a593Smuzhiyun goto bo_fini;
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun qdev->command_ring = qxl_ring_create(&(qdev->ram_header->cmd_ring_hdr),
197*4882a593Smuzhiyun sizeof(struct qxl_command),
198*4882a593Smuzhiyun QXL_COMMAND_RING_SIZE,
199*4882a593Smuzhiyun qdev->io_base + QXL_IO_NOTIFY_CMD,
200*4882a593Smuzhiyun false,
201*4882a593Smuzhiyun &qdev->display_event);
202*4882a593Smuzhiyun if (!qdev->command_ring) {
203*4882a593Smuzhiyun DRM_ERROR("Unable to create command ring\n");
204*4882a593Smuzhiyun r = -ENOMEM;
205*4882a593Smuzhiyun goto ram_header_unmap;
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun qdev->cursor_ring = qxl_ring_create(
209*4882a593Smuzhiyun &(qdev->ram_header->cursor_ring_hdr),
210*4882a593Smuzhiyun sizeof(struct qxl_command),
211*4882a593Smuzhiyun QXL_CURSOR_RING_SIZE,
212*4882a593Smuzhiyun qdev->io_base + QXL_IO_NOTIFY_CURSOR,
213*4882a593Smuzhiyun false,
214*4882a593Smuzhiyun &qdev->cursor_event);
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun if (!qdev->cursor_ring) {
217*4882a593Smuzhiyun DRM_ERROR("Unable to create cursor ring\n");
218*4882a593Smuzhiyun r = -ENOMEM;
219*4882a593Smuzhiyun goto command_ring_free;
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun qdev->release_ring = qxl_ring_create(
223*4882a593Smuzhiyun &(qdev->ram_header->release_ring_hdr),
224*4882a593Smuzhiyun sizeof(uint64_t),
225*4882a593Smuzhiyun QXL_RELEASE_RING_SIZE, 0, true,
226*4882a593Smuzhiyun NULL);
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun if (!qdev->release_ring) {
229*4882a593Smuzhiyun DRM_ERROR("Unable to create release ring\n");
230*4882a593Smuzhiyun r = -ENOMEM;
231*4882a593Smuzhiyun goto cursor_ring_free;
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun idr_init(&qdev->release_idr);
235*4882a593Smuzhiyun spin_lock_init(&qdev->release_idr_lock);
236*4882a593Smuzhiyun spin_lock_init(&qdev->release_lock);
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun idr_init(&qdev->surf_id_idr);
239*4882a593Smuzhiyun spin_lock_init(&qdev->surf_id_idr_lock);
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun mutex_init(&qdev->async_io_mutex);
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun /* reset the device into a known state - no memslots, no primary
244*4882a593Smuzhiyun * created, no surfaces. */
245*4882a593Smuzhiyun qxl_io_reset(qdev);
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun /* must initialize irq before first async io - slot creation */
248*4882a593Smuzhiyun r = qxl_irq_init(qdev);
249*4882a593Smuzhiyun if (r) {
250*4882a593Smuzhiyun DRM_ERROR("Unable to init qxl irq\n");
251*4882a593Smuzhiyun goto release_ring_free;
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun /*
255*4882a593Smuzhiyun * Note that virtual is surface0. We rely on the single ioremap done
256*4882a593Smuzhiyun * before.
257*4882a593Smuzhiyun */
258*4882a593Smuzhiyun setup_slot(qdev, &qdev->main_slot, 0, "main",
259*4882a593Smuzhiyun (unsigned long)qdev->vram_base,
260*4882a593Smuzhiyun (unsigned long)qdev->rom->ram_header_offset);
261*4882a593Smuzhiyun setup_slot(qdev, &qdev->surfaces_slot, 1, "surfaces",
262*4882a593Smuzhiyun (unsigned long)qdev->surfaceram_base,
263*4882a593Smuzhiyun (unsigned long)qdev->surfaceram_size);
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun INIT_WORK(&qdev->gc_work, qxl_gc_work);
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun return 0;
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun release_ring_free:
270*4882a593Smuzhiyun qxl_ring_free(qdev->release_ring);
271*4882a593Smuzhiyun cursor_ring_free:
272*4882a593Smuzhiyun qxl_ring_free(qdev->cursor_ring);
273*4882a593Smuzhiyun command_ring_free:
274*4882a593Smuzhiyun qxl_ring_free(qdev->command_ring);
275*4882a593Smuzhiyun ram_header_unmap:
276*4882a593Smuzhiyun iounmap(qdev->ram_header);
277*4882a593Smuzhiyun bo_fini:
278*4882a593Smuzhiyun qxl_bo_fini(qdev);
279*4882a593Smuzhiyun rom_unmap:
280*4882a593Smuzhiyun iounmap(qdev->rom);
281*4882a593Smuzhiyun surface_mapping_free:
282*4882a593Smuzhiyun io_mapping_free(qdev->surface_mapping);
283*4882a593Smuzhiyun vram_mapping_free:
284*4882a593Smuzhiyun io_mapping_free(qdev->vram_mapping);
285*4882a593Smuzhiyun return r;
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun
qxl_device_fini(struct qxl_device * qdev)288*4882a593Smuzhiyun void qxl_device_fini(struct qxl_device *qdev)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun qxl_bo_unref(&qdev->current_release_bo[0]);
291*4882a593Smuzhiyun qxl_bo_unref(&qdev->current_release_bo[1]);
292*4882a593Smuzhiyun qxl_gem_fini(qdev);
293*4882a593Smuzhiyun qxl_bo_fini(qdev);
294*4882a593Smuzhiyun flush_work(&qdev->gc_work);
295*4882a593Smuzhiyun qxl_ring_free(qdev->command_ring);
296*4882a593Smuzhiyun qxl_ring_free(qdev->cursor_ring);
297*4882a593Smuzhiyun qxl_ring_free(qdev->release_ring);
298*4882a593Smuzhiyun io_mapping_free(qdev->surface_mapping);
299*4882a593Smuzhiyun io_mapping_free(qdev->vram_mapping);
300*4882a593Smuzhiyun iounmap(qdev->ram_header);
301*4882a593Smuzhiyun iounmap(qdev->rom);
302*4882a593Smuzhiyun qdev->rom = NULL;
303*4882a593Smuzhiyun }
304