1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */ 3*4882a593Smuzhiyun /* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */ 4*4882a593Smuzhiyun /* 5*4882a593Smuzhiyun * Register definitions based on mali_midg_regmap.h 6*4882a593Smuzhiyun * (C) COPYRIGHT 2010-2018 ARM Limited. All rights reserved. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef __PANFROST_REGS_H__ 9*4882a593Smuzhiyun #define __PANFROST_REGS_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define GPU_ID 0x00 12*4882a593Smuzhiyun #define GPU_L2_FEATURES 0x004 /* (RO) Level 2 cache features */ 13*4882a593Smuzhiyun #define GPU_CORE_FEATURES 0x008 /* (RO) Shader Core Features */ 14*4882a593Smuzhiyun #define GPU_TILER_FEATURES 0x00C /* (RO) Tiler Features */ 15*4882a593Smuzhiyun #define GPU_MEM_FEATURES 0x010 /* (RO) Memory system features */ 16*4882a593Smuzhiyun #define GROUPS_L2_COHERENT BIT(0) /* Cores groups are l2 coherent */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define GPU_MMU_FEATURES 0x014 /* (RO) MMU features */ 19*4882a593Smuzhiyun #define GPU_AS_PRESENT 0x018 /* (RO) Address space slots present */ 20*4882a593Smuzhiyun #define GPU_JS_PRESENT 0x01C /* (RO) Job slots present */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define GPU_INT_RAWSTAT 0x20 23*4882a593Smuzhiyun #define GPU_INT_CLEAR 0x24 24*4882a593Smuzhiyun #define GPU_INT_MASK 0x28 25*4882a593Smuzhiyun #define GPU_INT_STAT 0x2c 26*4882a593Smuzhiyun #define GPU_IRQ_FAULT BIT(0) 27*4882a593Smuzhiyun #define GPU_IRQ_MULTIPLE_FAULT BIT(7) 28*4882a593Smuzhiyun #define GPU_IRQ_RESET_COMPLETED BIT(8) 29*4882a593Smuzhiyun #define GPU_IRQ_POWER_CHANGED BIT(9) 30*4882a593Smuzhiyun #define GPU_IRQ_POWER_CHANGED_ALL BIT(10) 31*4882a593Smuzhiyun #define GPU_IRQ_PERFCNT_SAMPLE_COMPLETED BIT(16) 32*4882a593Smuzhiyun #define GPU_IRQ_CLEAN_CACHES_COMPLETED BIT(17) 33*4882a593Smuzhiyun #define GPU_IRQ_MASK_ALL \ 34*4882a593Smuzhiyun (GPU_IRQ_FAULT |\ 35*4882a593Smuzhiyun GPU_IRQ_MULTIPLE_FAULT |\ 36*4882a593Smuzhiyun GPU_IRQ_RESET_COMPLETED |\ 37*4882a593Smuzhiyun GPU_IRQ_POWER_CHANGED |\ 38*4882a593Smuzhiyun GPU_IRQ_POWER_CHANGED_ALL |\ 39*4882a593Smuzhiyun GPU_IRQ_PERFCNT_SAMPLE_COMPLETED |\ 40*4882a593Smuzhiyun GPU_IRQ_CLEAN_CACHES_COMPLETED) 41*4882a593Smuzhiyun #define GPU_IRQ_MASK_ERROR \ 42*4882a593Smuzhiyun ( \ 43*4882a593Smuzhiyun GPU_IRQ_FAULT |\ 44*4882a593Smuzhiyun GPU_IRQ_MULTIPLE_FAULT) 45*4882a593Smuzhiyun #define GPU_CMD 0x30 46*4882a593Smuzhiyun #define GPU_CMD_SOFT_RESET 0x01 47*4882a593Smuzhiyun #define GPU_CMD_PERFCNT_CLEAR 0x03 48*4882a593Smuzhiyun #define GPU_CMD_PERFCNT_SAMPLE 0x04 49*4882a593Smuzhiyun #define GPU_CMD_CLEAN_CACHES 0x07 50*4882a593Smuzhiyun #define GPU_CMD_CLEAN_INV_CACHES 0x08 51*4882a593Smuzhiyun #define GPU_STATUS 0x34 52*4882a593Smuzhiyun #define GPU_STATUS_PRFCNT_ACTIVE BIT(2) 53*4882a593Smuzhiyun #define GPU_LATEST_FLUSH_ID 0x38 54*4882a593Smuzhiyun #define GPU_PWR_KEY 0x50 /* (WO) Power manager key register */ 55*4882a593Smuzhiyun #define GPU_PWR_KEY_UNLOCK 0x2968A819 56*4882a593Smuzhiyun #define GPU_PWR_OVERRIDE0 0x54 /* (RW) Power manager override settings */ 57*4882a593Smuzhiyun #define GPU_PWR_OVERRIDE1 0x58 /* (RW) Power manager override settings */ 58*4882a593Smuzhiyun #define GPU_FAULT_STATUS 0x3C 59*4882a593Smuzhiyun #define GPU_FAULT_ADDRESS_LO 0x40 60*4882a593Smuzhiyun #define GPU_FAULT_ADDRESS_HI 0x44 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define GPU_PERFCNT_BASE_LO 0x60 63*4882a593Smuzhiyun #define GPU_PERFCNT_BASE_HI 0x64 64*4882a593Smuzhiyun #define GPU_PERFCNT_CFG 0x68 65*4882a593Smuzhiyun #define GPU_PERFCNT_CFG_MODE(x) (x) 66*4882a593Smuzhiyun #define GPU_PERFCNT_CFG_MODE_OFF 0 67*4882a593Smuzhiyun #define GPU_PERFCNT_CFG_MODE_MANUAL 1 68*4882a593Smuzhiyun #define GPU_PERFCNT_CFG_MODE_TILE 2 69*4882a593Smuzhiyun #define GPU_PERFCNT_CFG_AS(x) ((x) << 4) 70*4882a593Smuzhiyun #define GPU_PERFCNT_CFG_SETSEL(x) ((x) << 8) 71*4882a593Smuzhiyun #define GPU_PRFCNT_JM_EN 0x6c 72*4882a593Smuzhiyun #define GPU_PRFCNT_SHADER_EN 0x70 73*4882a593Smuzhiyun #define GPU_PRFCNT_TILER_EN 0x74 74*4882a593Smuzhiyun #define GPU_PRFCNT_MMU_L2_EN 0x7c 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define GPU_THREAD_MAX_THREADS 0x0A0 /* (RO) Maximum number of threads per core */ 77*4882a593Smuzhiyun #define GPU_THREAD_MAX_WORKGROUP_SIZE 0x0A4 /* (RO) Maximum workgroup size */ 78*4882a593Smuzhiyun #define GPU_THREAD_MAX_BARRIER_SIZE 0x0A8 /* (RO) Maximum threads waiting at a barrier */ 79*4882a593Smuzhiyun #define GPU_THREAD_FEATURES 0x0AC /* (RO) Thread features */ 80*4882a593Smuzhiyun #define GPU_THREAD_TLS_ALLOC 0x310 /* (RO) Number of threads per core that 81*4882a593Smuzhiyun * TLS must be allocated for */ 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define GPU_TEXTURE_FEATURES(n) (0x0B0 + ((n) * 4)) 84*4882a593Smuzhiyun #define GPU_JS_FEATURES(n) (0x0C0 + ((n) * 4)) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define GPU_SHADER_PRESENT_LO 0x100 /* (RO) Shader core present bitmap, low word */ 87*4882a593Smuzhiyun #define GPU_SHADER_PRESENT_HI 0x104 /* (RO) Shader core present bitmap, high word */ 88*4882a593Smuzhiyun #define GPU_TILER_PRESENT_LO 0x110 /* (RO) Tiler core present bitmap, low word */ 89*4882a593Smuzhiyun #define GPU_TILER_PRESENT_HI 0x114 /* (RO) Tiler core present bitmap, high word */ 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define GPU_L2_PRESENT_LO 0x120 /* (RO) Level 2 cache present bitmap, low word */ 92*4882a593Smuzhiyun #define GPU_L2_PRESENT_HI 0x124 /* (RO) Level 2 cache present bitmap, high word */ 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define GPU_COHERENCY_FEATURES 0x300 /* (RO) Coherency features present */ 95*4882a593Smuzhiyun #define COHERENCY_ACE_LITE BIT(0) 96*4882a593Smuzhiyun #define COHERENCY_ACE BIT(1) 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #define GPU_STACK_PRESENT_LO 0xE00 /* (RO) Core stack present bitmap, low word */ 99*4882a593Smuzhiyun #define GPU_STACK_PRESENT_HI 0xE04 /* (RO) Core stack present bitmap, high word */ 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define SHADER_READY_LO 0x140 /* (RO) Shader core ready bitmap, low word */ 102*4882a593Smuzhiyun #define SHADER_READY_HI 0x144 /* (RO) Shader core ready bitmap, high word */ 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define TILER_READY_LO 0x150 /* (RO) Tiler core ready bitmap, low word */ 105*4882a593Smuzhiyun #define TILER_READY_HI 0x154 /* (RO) Tiler core ready bitmap, high word */ 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #define L2_READY_LO 0x160 /* (RO) Level 2 cache ready bitmap, low word */ 108*4882a593Smuzhiyun #define L2_READY_HI 0x164 /* (RO) Level 2 cache ready bitmap, high word */ 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #define STACK_READY_LO 0xE10 /* (RO) Core stack ready bitmap, low word */ 111*4882a593Smuzhiyun #define STACK_READY_HI 0xE14 /* (RO) Core stack ready bitmap, high word */ 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #define SHADER_PWRON_LO 0x180 /* (WO) Shader core power on bitmap, low word */ 115*4882a593Smuzhiyun #define SHADER_PWRON_HI 0x184 /* (WO) Shader core power on bitmap, high word */ 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define TILER_PWRON_LO 0x190 /* (WO) Tiler core power on bitmap, low word */ 118*4882a593Smuzhiyun #define TILER_PWRON_HI 0x194 /* (WO) Tiler core power on bitmap, high word */ 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #define L2_PWRON_LO 0x1A0 /* (WO) Level 2 cache power on bitmap, low word */ 121*4882a593Smuzhiyun #define L2_PWRON_HI 0x1A4 /* (WO) Level 2 cache power on bitmap, high word */ 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #define STACK_PWRON_LO 0xE20 /* (RO) Core stack power on bitmap, low word */ 124*4882a593Smuzhiyun #define STACK_PWRON_HI 0xE24 /* (RO) Core stack power on bitmap, high word */ 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #define SHADER_PWROFF_LO 0x1C0 /* (WO) Shader core power off bitmap, low word */ 128*4882a593Smuzhiyun #define SHADER_PWROFF_HI 0x1C4 /* (WO) Shader core power off bitmap, high word */ 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #define TILER_PWROFF_LO 0x1D0 /* (WO) Tiler core power off bitmap, low word */ 131*4882a593Smuzhiyun #define TILER_PWROFF_HI 0x1D4 /* (WO) Tiler core power off bitmap, high word */ 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #define L2_PWROFF_LO 0x1E0 /* (WO) Level 2 cache power off bitmap, low word */ 134*4882a593Smuzhiyun #define L2_PWROFF_HI 0x1E4 /* (WO) Level 2 cache power off bitmap, high word */ 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #define STACK_PWROFF_LO 0xE30 /* (RO) Core stack power off bitmap, low word */ 137*4882a593Smuzhiyun #define STACK_PWROFF_HI 0xE34 /* (RO) Core stack power off bitmap, high word */ 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun #define SHADER_PWRTRANS_LO 0x200 /* (RO) Shader core power transition bitmap, low word */ 141*4882a593Smuzhiyun #define SHADER_PWRTRANS_HI 0x204 /* (RO) Shader core power transition bitmap, high word */ 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #define TILER_PWRTRANS_LO 0x210 /* (RO) Tiler core power transition bitmap, low word */ 144*4882a593Smuzhiyun #define TILER_PWRTRANS_HI 0x214 /* (RO) Tiler core power transition bitmap, high word */ 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #define L2_PWRTRANS_LO 0x220 /* (RO) Level 2 cache power transition bitmap, low word */ 147*4882a593Smuzhiyun #define L2_PWRTRANS_HI 0x224 /* (RO) Level 2 cache power transition bitmap, high word */ 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun #define STACK_PWRTRANS_LO 0xE40 /* (RO) Core stack power transition bitmap, low word */ 150*4882a593Smuzhiyun #define STACK_PWRTRANS_HI 0xE44 /* (RO) Core stack power transition bitmap, high word */ 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun #define SHADER_PWRACTIVE_LO 0x240 /* (RO) Shader core active bitmap, low word */ 154*4882a593Smuzhiyun #define SHADER_PWRACTIVE_HI 0x244 /* (RO) Shader core active bitmap, high word */ 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun #define TILER_PWRACTIVE_LO 0x250 /* (RO) Tiler core active bitmap, low word */ 157*4882a593Smuzhiyun #define TILER_PWRACTIVE_HI 0x254 /* (RO) Tiler core active bitmap, high word */ 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun #define L2_PWRACTIVE_LO 0x260 /* (RO) Level 2 cache active bitmap, low word */ 160*4882a593Smuzhiyun #define L2_PWRACTIVE_HI 0x264 /* (RO) Level 2 cache active bitmap, high word */ 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun #define GPU_JM_CONFIG 0xF00 /* (RW) Job Manager configuration register (Implementation specific register) */ 163*4882a593Smuzhiyun #define GPU_SHADER_CONFIG 0xF04 /* (RW) Shader core configuration settings (Implementation specific register) */ 164*4882a593Smuzhiyun #define GPU_TILER_CONFIG 0xF08 /* (RW) Tiler core configuration settings (Implementation specific register) */ 165*4882a593Smuzhiyun #define GPU_L2_MMU_CONFIG 0xF0C /* (RW) Configuration of the L2 cache and MMU (Implementation specific register) */ 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun /* L2_MMU_CONFIG register */ 168*4882a593Smuzhiyun #define L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY_SHIFT 23 169*4882a593Smuzhiyun #define L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY (0x1 << L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY_SHIFT) 170*4882a593Smuzhiyun #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT 24 171*4882a593Smuzhiyun #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT) 172*4882a593Smuzhiyun #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_OCTANT (0x1 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT) 173*4882a593Smuzhiyun #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_QUARTER (0x2 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT) 174*4882a593Smuzhiyun #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_HALF (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT) 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT 26 177*4882a593Smuzhiyun #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT) 178*4882a593Smuzhiyun #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_OCTANT (0x1 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT) 179*4882a593Smuzhiyun #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_QUARTER (0x2 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT) 180*4882a593Smuzhiyun #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_HALF (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT) 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun #define L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_READS_SHIFT 12 183*4882a593Smuzhiyun #define L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_READS (0x7 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT) 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun #define L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_WRITES_SHIFT 15 186*4882a593Smuzhiyun #define L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_WRITES (0x7 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT) 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun /* SHADER_CONFIG register */ 189*4882a593Smuzhiyun #define SC_ALT_COUNTERS BIT(3) 190*4882a593Smuzhiyun #define SC_OVERRIDE_FWD_PIXEL_KILL BIT(4) 191*4882a593Smuzhiyun #define SC_SDC_DISABLE_OQ_DISCARD BIT(6) 192*4882a593Smuzhiyun #define SC_LS_ALLOW_ATTR_TYPES BIT(16) 193*4882a593Smuzhiyun #define SC_LS_PAUSEBUFFER_DISABLE BIT(16) 194*4882a593Smuzhiyun #define SC_TLS_HASH_ENABLE BIT(17) 195*4882a593Smuzhiyun #define SC_LS_ATTR_CHECK_DISABLE BIT(18) 196*4882a593Smuzhiyun #define SC_ENABLE_TEXGRD_FLAGS BIT(25) 197*4882a593Smuzhiyun /* End SHADER_CONFIG register */ 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun /* TILER_CONFIG register */ 200*4882a593Smuzhiyun #define TC_CLOCK_GATE_OVERRIDE BIT(0) 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun /* JM_CONFIG register */ 203*4882a593Smuzhiyun #define JM_TIMESTAMP_OVERRIDE BIT(0) 204*4882a593Smuzhiyun #define JM_CLOCK_GATE_OVERRIDE BIT(1) 205*4882a593Smuzhiyun #define JM_JOB_THROTTLE_ENABLE BIT(2) 206*4882a593Smuzhiyun #define JM_JOB_THROTTLE_LIMIT_SHIFT 3 207*4882a593Smuzhiyun #define JM_MAX_JOB_THROTTLE_LIMIT 0x3F 208*4882a593Smuzhiyun #define JM_FORCE_COHERENCY_FEATURES_SHIFT 2 209*4882a593Smuzhiyun #define JM_IDVS_GROUP_SIZE_SHIFT 16 210*4882a593Smuzhiyun #define JM_MAX_IDVS_GROUP_SIZE 0x3F 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun /* Job Control regs */ 214*4882a593Smuzhiyun #define JOB_INT_RAWSTAT 0x1000 215*4882a593Smuzhiyun #define JOB_INT_CLEAR 0x1004 216*4882a593Smuzhiyun #define JOB_INT_MASK 0x1008 217*4882a593Smuzhiyun #define JOB_INT_STAT 0x100c 218*4882a593Smuzhiyun #define JOB_INT_JS_STATE 0x1010 219*4882a593Smuzhiyun #define JOB_INT_THROTTLE 0x1014 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun #define MK_JS_MASK(j) (0x10001 << (j)) 222*4882a593Smuzhiyun #define JOB_INT_MASK_ERR(j) BIT((j) + 16) 223*4882a593Smuzhiyun #define JOB_INT_MASK_DONE(j) BIT(j) 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun #define JS_BASE 0x1800 226*4882a593Smuzhiyun #define JS_HEAD_LO(n) (JS_BASE + ((n) * 0x80) + 0x00) 227*4882a593Smuzhiyun #define JS_HEAD_HI(n) (JS_BASE + ((n) * 0x80) + 0x04) 228*4882a593Smuzhiyun #define JS_TAIL_LO(n) (JS_BASE + ((n) * 0x80) + 0x08) 229*4882a593Smuzhiyun #define JS_TAIL_HI(n) (JS_BASE + ((n) * 0x80) + 0x0c) 230*4882a593Smuzhiyun #define JS_AFFINITY_LO(n) (JS_BASE + ((n) * 0x80) + 0x10) 231*4882a593Smuzhiyun #define JS_AFFINITY_HI(n) (JS_BASE + ((n) * 0x80) + 0x14) 232*4882a593Smuzhiyun #define JS_CONFIG(n) (JS_BASE + ((n) * 0x80) + 0x18) 233*4882a593Smuzhiyun #define JS_XAFFINITY(n) (JS_BASE + ((n) * 0x80) + 0x1c) 234*4882a593Smuzhiyun #define JS_COMMAND(n) (JS_BASE + ((n) * 0x80) + 0x20) 235*4882a593Smuzhiyun #define JS_STATUS(n) (JS_BASE + ((n) * 0x80) + 0x24) 236*4882a593Smuzhiyun #define JS_HEAD_NEXT_LO(n) (JS_BASE + ((n) * 0x80) + 0x40) 237*4882a593Smuzhiyun #define JS_HEAD_NEXT_HI(n) (JS_BASE + ((n) * 0x80) + 0x44) 238*4882a593Smuzhiyun #define JS_AFFINITY_NEXT_LO(n) (JS_BASE + ((n) * 0x80) + 0x50) 239*4882a593Smuzhiyun #define JS_AFFINITY_NEXT_HI(n) (JS_BASE + ((n) * 0x80) + 0x54) 240*4882a593Smuzhiyun #define JS_CONFIG_NEXT(n) (JS_BASE + ((n) * 0x80) + 0x58) 241*4882a593Smuzhiyun #define JS_COMMAND_NEXT(n) (JS_BASE + ((n) * 0x80) + 0x60) 242*4882a593Smuzhiyun #define JS_FLUSH_ID_NEXT(n) (JS_BASE + ((n) * 0x80) + 0x70) 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun /* Possible values of JS_CONFIG and JS_CONFIG_NEXT registers */ 245*4882a593Smuzhiyun #define JS_CONFIG_START_FLUSH_CLEAN BIT(8) 246*4882a593Smuzhiyun #define JS_CONFIG_START_FLUSH_CLEAN_INVALIDATE (3u << 8) 247*4882a593Smuzhiyun #define JS_CONFIG_START_MMU BIT(10) 248*4882a593Smuzhiyun #define JS_CONFIG_JOB_CHAIN_FLAG BIT(11) 249*4882a593Smuzhiyun #define JS_CONFIG_END_FLUSH_CLEAN BIT(12) 250*4882a593Smuzhiyun #define JS_CONFIG_END_FLUSH_CLEAN_INVALIDATE (3u << 12) 251*4882a593Smuzhiyun #define JS_CONFIG_ENABLE_FLUSH_REDUCTION BIT(14) 252*4882a593Smuzhiyun #define JS_CONFIG_DISABLE_DESCRIPTOR_WR_BK BIT(15) 253*4882a593Smuzhiyun #define JS_CONFIG_THREAD_PRI(n) ((n) << 16) 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun #define JS_COMMAND_NOP 0x00 256*4882a593Smuzhiyun #define JS_COMMAND_START 0x01 257*4882a593Smuzhiyun #define JS_COMMAND_SOFT_STOP 0x02 /* Gently stop processing a job chain */ 258*4882a593Smuzhiyun #define JS_COMMAND_HARD_STOP 0x03 /* Rudely stop processing a job chain */ 259*4882a593Smuzhiyun #define JS_COMMAND_SOFT_STOP_0 0x04 /* Execute SOFT_STOP if JOB_CHAIN_FLAG is 0 */ 260*4882a593Smuzhiyun #define JS_COMMAND_HARD_STOP_0 0x05 /* Execute HARD_STOP if JOB_CHAIN_FLAG is 0 */ 261*4882a593Smuzhiyun #define JS_COMMAND_SOFT_STOP_1 0x06 /* Execute SOFT_STOP if JOB_CHAIN_FLAG is 1 */ 262*4882a593Smuzhiyun #define JS_COMMAND_HARD_STOP_1 0x07 /* Execute HARD_STOP if JOB_CHAIN_FLAG is 1 */ 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun #define JS_STATUS_EVENT_ACTIVE 0x08 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun /* MMU regs */ 268*4882a593Smuzhiyun #define MMU_INT_RAWSTAT 0x2000 269*4882a593Smuzhiyun #define MMU_INT_CLEAR 0x2004 270*4882a593Smuzhiyun #define MMU_INT_MASK 0x2008 271*4882a593Smuzhiyun #define MMU_INT_STAT 0x200c 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun /* AS_COMMAND register commands */ 274*4882a593Smuzhiyun #define AS_COMMAND_NOP 0x00 /* NOP Operation */ 275*4882a593Smuzhiyun #define AS_COMMAND_UPDATE 0x01 /* Broadcasts the values in AS_TRANSTAB and ASn_MEMATTR to all MMUs */ 276*4882a593Smuzhiyun #define AS_COMMAND_LOCK 0x02 /* Issue a lock region command to all MMUs */ 277*4882a593Smuzhiyun #define AS_COMMAND_UNLOCK 0x03 /* Issue a flush region command to all MMUs */ 278*4882a593Smuzhiyun #define AS_COMMAND_FLUSH 0x04 /* Flush all L2 caches then issue a flush region command to all MMUs 279*4882a593Smuzhiyun (deprecated - only for use with T60x) */ 280*4882a593Smuzhiyun #define AS_COMMAND_FLUSH_PT 0x04 /* Flush all L2 caches then issue a flush region command to all MMUs */ 281*4882a593Smuzhiyun #define AS_COMMAND_FLUSH_MEM 0x05 /* Wait for memory accesses to complete, flush all the L1s cache then 282*4882a593Smuzhiyun flush all L2 caches then issue a flush region command to all MMUs */ 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun #define MMU_AS(as) (0x2400 + ((as) << 6)) 285*4882a593Smuzhiyun 286*4882a593Smuzhiyun #define AS_TRANSTAB_LO(as) (MMU_AS(as) + 0x00) /* (RW) Translation Table Base Address for address space n, low word */ 287*4882a593Smuzhiyun #define AS_TRANSTAB_HI(as) (MMU_AS(as) + 0x04) /* (RW) Translation Table Base Address for address space n, high word */ 288*4882a593Smuzhiyun #define AS_MEMATTR_LO(as) (MMU_AS(as) + 0x08) /* (RW) Memory attributes for address space n, low word. */ 289*4882a593Smuzhiyun #define AS_MEMATTR_HI(as) (MMU_AS(as) + 0x0C) /* (RW) Memory attributes for address space n, high word. */ 290*4882a593Smuzhiyun #define AS_LOCKADDR_LO(as) (MMU_AS(as) + 0x10) /* (RW) Lock region address for address space n, low word */ 291*4882a593Smuzhiyun #define AS_LOCKADDR_HI(as) (MMU_AS(as) + 0x14) /* (RW) Lock region address for address space n, high word */ 292*4882a593Smuzhiyun #define AS_COMMAND(as) (MMU_AS(as) + 0x18) /* (WO) MMU command register for address space n */ 293*4882a593Smuzhiyun #define AS_FAULTSTATUS(as) (MMU_AS(as) + 0x1C) /* (RO) MMU fault status register for address space n */ 294*4882a593Smuzhiyun #define AS_FAULTADDRESS_LO(as) (MMU_AS(as) + 0x20) /* (RO) Fault Address for address space n, low word */ 295*4882a593Smuzhiyun #define AS_FAULTADDRESS_HI(as) (MMU_AS(as) + 0x24) /* (RO) Fault Address for address space n, high word */ 296*4882a593Smuzhiyun #define AS_STATUS(as) (MMU_AS(as) + 0x28) /* (RO) Status flags for address space n */ 297*4882a593Smuzhiyun /* Additional Bifrost AS regsiters */ 298*4882a593Smuzhiyun #define AS_TRANSCFG_LO(as) (MMU_AS(as) + 0x30) /* (RW) Translation table configuration for address space n, low word */ 299*4882a593Smuzhiyun #define AS_TRANSCFG_HI(as) (MMU_AS(as) + 0x34) /* (RW) Translation table configuration for address space n, high word */ 300*4882a593Smuzhiyun #define AS_FAULTEXTRA_LO(as) (MMU_AS(as) + 0x38) /* (RO) Secondary fault address for address space n, low word */ 301*4882a593Smuzhiyun #define AS_FAULTEXTRA_HI(as) (MMU_AS(as) + 0x3C) /* (RO) Secondary fault address for address space n, high word */ 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun /* 304*4882a593Smuzhiyun * Begin LPAE MMU TRANSTAB register values 305*4882a593Smuzhiyun */ 306*4882a593Smuzhiyun #define AS_TRANSTAB_LPAE_ADDR_SPACE_MASK 0xfffffffffffff000 307*4882a593Smuzhiyun #define AS_TRANSTAB_LPAE_ADRMODE_IDENTITY 0x2 308*4882a593Smuzhiyun #define AS_TRANSTAB_LPAE_ADRMODE_TABLE 0x3 309*4882a593Smuzhiyun #define AS_TRANSTAB_LPAE_ADRMODE_MASK 0x3 310*4882a593Smuzhiyun #define AS_TRANSTAB_LPAE_READ_INNER BIT(2) 311*4882a593Smuzhiyun #define AS_TRANSTAB_LPAE_SHARE_OUTER BIT(4) 312*4882a593Smuzhiyun 313*4882a593Smuzhiyun #define AS_STATUS_AS_ACTIVE 0x01 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun #define AS_FAULTSTATUS_ACCESS_TYPE_MASK (0x3 << 8) 316*4882a593Smuzhiyun #define AS_FAULTSTATUS_ACCESS_TYPE_ATOMIC (0x0 << 8) 317*4882a593Smuzhiyun #define AS_FAULTSTATUS_ACCESS_TYPE_EX (0x1 << 8) 318*4882a593Smuzhiyun #define AS_FAULTSTATUS_ACCESS_TYPE_READ (0x2 << 8) 319*4882a593Smuzhiyun #define AS_FAULTSTATUS_ACCESS_TYPE_WRITE (0x3 << 8) 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun #define AS_LOCK_REGION_MIN_SIZE (1ULL << 15) 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun #define gpu_write(dev, reg, data) writel(data, dev->iomem + reg) 324*4882a593Smuzhiyun #define gpu_read(dev, reg) readl(dev->iomem + reg) 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun #endif 327