xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/panel/panel-visionox-rm69299.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2019, The Linux Foundation. All rights reserved.
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #include <linux/delay.h>
7*4882a593Smuzhiyun #include <linux/module.h>
8*4882a593Smuzhiyun #include <linux/of_device.h>
9*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
10*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include <video/mipi_display.h>
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #include <drm/drm_mipi_dsi.h>
15*4882a593Smuzhiyun #include <drm/drm_modes.h>
16*4882a593Smuzhiyun #include <drm/drm_panel.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun struct visionox_rm69299 {
19*4882a593Smuzhiyun 	struct drm_panel panel;
20*4882a593Smuzhiyun 	struct regulator_bulk_data supplies[2];
21*4882a593Smuzhiyun 	struct gpio_desc *reset_gpio;
22*4882a593Smuzhiyun 	struct mipi_dsi_device *dsi;
23*4882a593Smuzhiyun 	bool prepared;
24*4882a593Smuzhiyun 	bool enabled;
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun 
panel_to_ctx(struct drm_panel * panel)27*4882a593Smuzhiyun static inline struct visionox_rm69299 *panel_to_ctx(struct drm_panel *panel)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun 	return container_of(panel, struct visionox_rm69299, panel);
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun 
visionox_rm69299_power_on(struct visionox_rm69299 * ctx)32*4882a593Smuzhiyun static int visionox_rm69299_power_on(struct visionox_rm69299 *ctx)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun 	int ret;
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun 	ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
37*4882a593Smuzhiyun 	if (ret < 0)
38*4882a593Smuzhiyun 		return ret;
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun 	/*
41*4882a593Smuzhiyun 	 * Reset sequence of visionox panel requires the panel to be
42*4882a593Smuzhiyun 	 * out of reset for 10ms, followed by being held in reset
43*4882a593Smuzhiyun 	 * for 10ms and then out again
44*4882a593Smuzhiyun 	 */
45*4882a593Smuzhiyun 	gpiod_set_value(ctx->reset_gpio, 1);
46*4882a593Smuzhiyun 	usleep_range(10000, 20000);
47*4882a593Smuzhiyun 	gpiod_set_value(ctx->reset_gpio, 0);
48*4882a593Smuzhiyun 	usleep_range(10000, 20000);
49*4882a593Smuzhiyun 	gpiod_set_value(ctx->reset_gpio, 1);
50*4882a593Smuzhiyun 	usleep_range(10000, 20000);
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 	return 0;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun 
visionox_rm69299_power_off(struct visionox_rm69299 * ctx)55*4882a593Smuzhiyun static int visionox_rm69299_power_off(struct visionox_rm69299 *ctx)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun 	gpiod_set_value(ctx->reset_gpio, 0);
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun 	return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun 
visionox_rm69299_unprepare(struct drm_panel * panel)62*4882a593Smuzhiyun static int visionox_rm69299_unprepare(struct drm_panel *panel)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun 	struct visionox_rm69299 *ctx = panel_to_ctx(panel);
65*4882a593Smuzhiyun 	int ret;
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun 	ctx->dsi->mode_flags = 0;
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	ret = mipi_dsi_dcs_write(ctx->dsi, MIPI_DCS_SET_DISPLAY_OFF, NULL, 0);
70*4882a593Smuzhiyun 	if (ret < 0)
71*4882a593Smuzhiyun 		dev_err(ctx->panel.dev, "set_display_off cmd failed ret = %d\n", ret);
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	/* 120ms delay required here as per DCS spec */
74*4882a593Smuzhiyun 	msleep(120);
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	ret = mipi_dsi_dcs_write(ctx->dsi, MIPI_DCS_ENTER_SLEEP_MODE, NULL, 0);
77*4882a593Smuzhiyun 	if (ret < 0) {
78*4882a593Smuzhiyun 		dev_err(ctx->panel.dev, "enter_sleep cmd failed ret = %d\n", ret);
79*4882a593Smuzhiyun 	}
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun 	ret = visionox_rm69299_power_off(ctx);
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	ctx->prepared = false;
84*4882a593Smuzhiyun 	return ret;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun 
visionox_rm69299_prepare(struct drm_panel * panel)87*4882a593Smuzhiyun static int visionox_rm69299_prepare(struct drm_panel *panel)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun 	struct visionox_rm69299 *ctx = panel_to_ctx(panel);
90*4882a593Smuzhiyun 	int ret;
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	if (ctx->prepared)
93*4882a593Smuzhiyun 		return 0;
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 	ret = visionox_rm69299_power_on(ctx);
96*4882a593Smuzhiyun 	if (ret < 0)
97*4882a593Smuzhiyun 		return ret;
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 	ctx->dsi->mode_flags |= MIPI_DSI_MODE_LPM;
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	ret = mipi_dsi_dcs_write_buffer(ctx->dsi, (u8[]) { 0xfe, 0x00 }, 2);
102*4882a593Smuzhiyun 	if (ret < 0) {
103*4882a593Smuzhiyun 		dev_err(ctx->panel.dev, "cmd set tx 0 failed, ret = %d\n", ret);
104*4882a593Smuzhiyun 		goto power_off;
105*4882a593Smuzhiyun 	}
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	ret = mipi_dsi_dcs_write_buffer(ctx->dsi, (u8[]) { 0xc2, 0x08 }, 2);
108*4882a593Smuzhiyun 	if (ret < 0) {
109*4882a593Smuzhiyun 		dev_err(ctx->panel.dev, "cmd set tx 1 failed, ret = %d\n", ret);
110*4882a593Smuzhiyun 		goto power_off;
111*4882a593Smuzhiyun 	}
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	ret = mipi_dsi_dcs_write_buffer(ctx->dsi, (u8[]) { 0x35, 0x00 }, 2);
114*4882a593Smuzhiyun 	if (ret < 0) {
115*4882a593Smuzhiyun 		dev_err(ctx->panel.dev, "cmd set tx 2 failed, ret = %d\n", ret);
116*4882a593Smuzhiyun 		goto power_off;
117*4882a593Smuzhiyun 	}
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	ret = mipi_dsi_dcs_write_buffer(ctx->dsi, (u8[]) { 0x51, 0xff }, 2);
120*4882a593Smuzhiyun 	if (ret < 0) {
121*4882a593Smuzhiyun 		dev_err(ctx->panel.dev, "cmd set tx 3 failed, ret = %d\n", ret);
122*4882a593Smuzhiyun 		goto power_off;
123*4882a593Smuzhiyun 	}
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	ret = mipi_dsi_dcs_write(ctx->dsi, MIPI_DCS_EXIT_SLEEP_MODE, NULL, 0);
126*4882a593Smuzhiyun 	if (ret < 0) {
127*4882a593Smuzhiyun 		dev_err(ctx->panel.dev, "exit_sleep_mode cmd failed ret = %d\n", ret);
128*4882a593Smuzhiyun 		goto power_off;
129*4882a593Smuzhiyun 	}
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 	/* Per DSI spec wait 120ms after sending exit sleep DCS command */
132*4882a593Smuzhiyun 	msleep(120);
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	ret = mipi_dsi_dcs_write(ctx->dsi, MIPI_DCS_SET_DISPLAY_ON, NULL, 0);
135*4882a593Smuzhiyun 	if (ret < 0) {
136*4882a593Smuzhiyun 		dev_err(ctx->panel.dev, "set_display_on cmd failed ret = %d\n", ret);
137*4882a593Smuzhiyun 		goto power_off;
138*4882a593Smuzhiyun 	}
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	/* Per DSI spec wait 120ms after sending set_display_on DCS command */
141*4882a593Smuzhiyun 	msleep(120);
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	ctx->prepared = true;
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	return 0;
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun power_off:
148*4882a593Smuzhiyun 	return ret;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun static const struct drm_display_mode visionox_rm69299_1080x2248_60hz = {
152*4882a593Smuzhiyun 	.name = "1080x2248",
153*4882a593Smuzhiyun 	.clock = 158695,
154*4882a593Smuzhiyun 	.hdisplay = 1080,
155*4882a593Smuzhiyun 	.hsync_start = 1080 + 26,
156*4882a593Smuzhiyun 	.hsync_end = 1080 + 26 + 2,
157*4882a593Smuzhiyun 	.htotal = 1080 + 26 + 2 + 36,
158*4882a593Smuzhiyun 	.vdisplay = 2248,
159*4882a593Smuzhiyun 	.vsync_start = 2248 + 56,
160*4882a593Smuzhiyun 	.vsync_end = 2248 + 56 + 4,
161*4882a593Smuzhiyun 	.vtotal = 2248 + 56 + 4 + 4,
162*4882a593Smuzhiyun 	.flags = 0,
163*4882a593Smuzhiyun };
164*4882a593Smuzhiyun 
visionox_rm69299_get_modes(struct drm_panel * panel,struct drm_connector * connector)165*4882a593Smuzhiyun static int visionox_rm69299_get_modes(struct drm_panel *panel,
166*4882a593Smuzhiyun 				      struct drm_connector *connector)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun 	struct visionox_rm69299 *ctx = panel_to_ctx(panel);
169*4882a593Smuzhiyun 	struct drm_display_mode *mode;
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 	mode = drm_mode_create(connector->dev);
172*4882a593Smuzhiyun 	if (!mode) {
173*4882a593Smuzhiyun 		dev_err(ctx->panel.dev, "failed to create a new display mode\n");
174*4882a593Smuzhiyun 		return 0;
175*4882a593Smuzhiyun 	}
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	connector->display_info.width_mm = 74;
178*4882a593Smuzhiyun 	connector->display_info.height_mm = 131;
179*4882a593Smuzhiyun 	drm_mode_copy(mode, &visionox_rm69299_1080x2248_60hz);
180*4882a593Smuzhiyun 	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
181*4882a593Smuzhiyun 	drm_mode_probed_add(connector, mode);
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 	return 1;
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun static const struct drm_panel_funcs visionox_rm69299_drm_funcs = {
187*4882a593Smuzhiyun 	.unprepare = visionox_rm69299_unprepare,
188*4882a593Smuzhiyun 	.prepare = visionox_rm69299_prepare,
189*4882a593Smuzhiyun 	.get_modes = visionox_rm69299_get_modes,
190*4882a593Smuzhiyun };
191*4882a593Smuzhiyun 
visionox_rm69299_probe(struct mipi_dsi_device * dsi)192*4882a593Smuzhiyun static int visionox_rm69299_probe(struct mipi_dsi_device *dsi)
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun 	struct device *dev = &dsi->dev;
195*4882a593Smuzhiyun 	struct visionox_rm69299 *ctx;
196*4882a593Smuzhiyun 	int ret;
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
199*4882a593Smuzhiyun 	if (!ctx)
200*4882a593Smuzhiyun 		return -ENOMEM;
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	mipi_dsi_set_drvdata(dsi, ctx);
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun 	ctx->panel.dev = dev;
205*4882a593Smuzhiyun 	ctx->dsi = dsi;
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	ctx->supplies[0].supply = "vdda";
208*4882a593Smuzhiyun 	ctx->supplies[1].supply = "vdd3p3";
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 	ret = devm_regulator_bulk_get(ctx->panel.dev, ARRAY_SIZE(ctx->supplies),
211*4882a593Smuzhiyun 				      ctx->supplies);
212*4882a593Smuzhiyun 	if (ret < 0)
213*4882a593Smuzhiyun 		return ret;
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun 	ctx->reset_gpio = devm_gpiod_get(ctx->panel.dev,
216*4882a593Smuzhiyun 					 "reset", GPIOD_OUT_LOW);
217*4882a593Smuzhiyun 	if (IS_ERR(ctx->reset_gpio)) {
218*4882a593Smuzhiyun 		dev_err(dev, "cannot get reset gpio %ld\n", PTR_ERR(ctx->reset_gpio));
219*4882a593Smuzhiyun 		return PTR_ERR(ctx->reset_gpio);
220*4882a593Smuzhiyun 	}
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	drm_panel_init(&ctx->panel, dev, &visionox_rm69299_drm_funcs,
223*4882a593Smuzhiyun 		       DRM_MODE_CONNECTOR_DSI);
224*4882a593Smuzhiyun 	ctx->panel.dev = dev;
225*4882a593Smuzhiyun 	ctx->panel.funcs = &visionox_rm69299_drm_funcs;
226*4882a593Smuzhiyun 	drm_panel_add(&ctx->panel);
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun 	dsi->lanes = 4;
229*4882a593Smuzhiyun 	dsi->format = MIPI_DSI_FMT_RGB888;
230*4882a593Smuzhiyun 	dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM |
231*4882a593Smuzhiyun 			  MIPI_DSI_CLOCK_NON_CONTINUOUS;
232*4882a593Smuzhiyun 	ret = mipi_dsi_attach(dsi);
233*4882a593Smuzhiyun 	if (ret < 0) {
234*4882a593Smuzhiyun 		dev_err(dev, "dsi attach failed ret = %d\n", ret);
235*4882a593Smuzhiyun 		goto err_dsi_attach;
236*4882a593Smuzhiyun 	}
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 	ret = regulator_set_load(ctx->supplies[0].consumer, 32000);
239*4882a593Smuzhiyun 	if (ret) {
240*4882a593Smuzhiyun 		dev_err(dev, "regulator set load failed for vdda supply ret = %d\n", ret);
241*4882a593Smuzhiyun 		goto err_set_load;
242*4882a593Smuzhiyun 	}
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	ret = regulator_set_load(ctx->supplies[1].consumer, 13200);
245*4882a593Smuzhiyun 	if (ret) {
246*4882a593Smuzhiyun 		dev_err(dev, "regulator set load failed for vdd3p3 supply ret = %d\n", ret);
247*4882a593Smuzhiyun 		goto err_set_load;
248*4882a593Smuzhiyun 	}
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun 	return 0;
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun err_set_load:
253*4882a593Smuzhiyun 	mipi_dsi_detach(dsi);
254*4882a593Smuzhiyun err_dsi_attach:
255*4882a593Smuzhiyun 	drm_panel_remove(&ctx->panel);
256*4882a593Smuzhiyun 	return ret;
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun 
visionox_rm69299_remove(struct mipi_dsi_device * dsi)259*4882a593Smuzhiyun static int visionox_rm69299_remove(struct mipi_dsi_device *dsi)
260*4882a593Smuzhiyun {
261*4882a593Smuzhiyun 	struct visionox_rm69299 *ctx = mipi_dsi_get_drvdata(dsi);
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	mipi_dsi_detach(ctx->dsi);
264*4882a593Smuzhiyun 	mipi_dsi_device_unregister(ctx->dsi);
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	drm_panel_remove(&ctx->panel);
267*4882a593Smuzhiyun 	return 0;
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun static const struct of_device_id visionox_rm69299_of_match[] = {
271*4882a593Smuzhiyun 	{ .compatible = "visionox,rm69299-1080p-display", },
272*4882a593Smuzhiyun 	{ /* sentinel */ }
273*4882a593Smuzhiyun };
274*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, visionox_rm69299_of_match);
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun static struct mipi_dsi_driver visionox_rm69299_driver = {
277*4882a593Smuzhiyun 	.driver = {
278*4882a593Smuzhiyun 		.name = "panel-visionox-rm69299",
279*4882a593Smuzhiyun 		.of_match_table = visionox_rm69299_of_match,
280*4882a593Smuzhiyun 	},
281*4882a593Smuzhiyun 	.probe = visionox_rm69299_probe,
282*4882a593Smuzhiyun 	.remove = visionox_rm69299_remove,
283*4882a593Smuzhiyun };
284*4882a593Smuzhiyun module_mipi_dsi_driver(visionox_rm69299_driver);
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun MODULE_DESCRIPTION("Visionox RM69299 DSI Panel Driver");
287*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
288