1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2017 Free Electrons
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/delay.h>
7*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
10*4882a593Smuzhiyun #include <linux/spi/spi.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <video/mipi_display.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <drm/drm_device.h>
15*4882a593Smuzhiyun #include <drm/drm_modes.h>
16*4882a593Smuzhiyun #include <drm/drm_panel.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define ST7789V_COLMOD_RGB_FMT_18BITS (6 << 4)
19*4882a593Smuzhiyun #define ST7789V_COLMOD_CTRL_FMT_18BITS (6 << 0)
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define ST7789V_RAMCTRL_CMD 0xb0
22*4882a593Smuzhiyun #define ST7789V_RAMCTRL_RM_RGB BIT(4)
23*4882a593Smuzhiyun #define ST7789V_RAMCTRL_DM_RGB BIT(0)
24*4882a593Smuzhiyun #define ST7789V_RAMCTRL_MAGIC (3 << 6)
25*4882a593Smuzhiyun #define ST7789V_RAMCTRL_EPF(n) (((n) & 3) << 4)
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define ST7789V_RGBCTRL_CMD 0xb1
28*4882a593Smuzhiyun #define ST7789V_RGBCTRL_WO BIT(7)
29*4882a593Smuzhiyun #define ST7789V_RGBCTRL_RCM(n) (((n) & 3) << 5)
30*4882a593Smuzhiyun #define ST7789V_RGBCTRL_VSYNC_HIGH BIT(3)
31*4882a593Smuzhiyun #define ST7789V_RGBCTRL_HSYNC_HIGH BIT(2)
32*4882a593Smuzhiyun #define ST7789V_RGBCTRL_PCLK_HIGH BIT(1)
33*4882a593Smuzhiyun #define ST7789V_RGBCTRL_VBP(n) ((n) & 0x7f)
34*4882a593Smuzhiyun #define ST7789V_RGBCTRL_HBP(n) ((n) & 0x1f)
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define ST7789V_PORCTRL_CMD 0xb2
37*4882a593Smuzhiyun #define ST7789V_PORCTRL_IDLE_BP(n) (((n) & 0xf) << 4)
38*4882a593Smuzhiyun #define ST7789V_PORCTRL_IDLE_FP(n) ((n) & 0xf)
39*4882a593Smuzhiyun #define ST7789V_PORCTRL_PARTIAL_BP(n) (((n) & 0xf) << 4)
40*4882a593Smuzhiyun #define ST7789V_PORCTRL_PARTIAL_FP(n) ((n) & 0xf)
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define ST7789V_GCTRL_CMD 0xb7
43*4882a593Smuzhiyun #define ST7789V_GCTRL_VGHS(n) (((n) & 7) << 4)
44*4882a593Smuzhiyun #define ST7789V_GCTRL_VGLS(n) ((n) & 7)
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun #define ST7789V_VCOMS_CMD 0xbb
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #define ST7789V_LCMCTRL_CMD 0xc0
49*4882a593Smuzhiyun #define ST7789V_LCMCTRL_XBGR BIT(5)
50*4882a593Smuzhiyun #define ST7789V_LCMCTRL_XMX BIT(3)
51*4882a593Smuzhiyun #define ST7789V_LCMCTRL_XMH BIT(2)
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun #define ST7789V_VDVVRHEN_CMD 0xc2
54*4882a593Smuzhiyun #define ST7789V_VDVVRHEN_CMDEN BIT(0)
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun #define ST7789V_VRHS_CMD 0xc3
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun #define ST7789V_VDVS_CMD 0xc4
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #define ST7789V_FRCTRL2_CMD 0xc6
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun #define ST7789V_PWCTRL1_CMD 0xd0
63*4882a593Smuzhiyun #define ST7789V_PWCTRL1_MAGIC 0xa4
64*4882a593Smuzhiyun #define ST7789V_PWCTRL1_AVDD(n) (((n) & 3) << 6)
65*4882a593Smuzhiyun #define ST7789V_PWCTRL1_AVCL(n) (((n) & 3) << 4)
66*4882a593Smuzhiyun #define ST7789V_PWCTRL1_VDS(n) ((n) & 3)
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun #define ST7789V_PVGAMCTRL_CMD 0xe0
69*4882a593Smuzhiyun #define ST7789V_PVGAMCTRL_JP0(n) (((n) & 3) << 4)
70*4882a593Smuzhiyun #define ST7789V_PVGAMCTRL_JP1(n) (((n) & 3) << 4)
71*4882a593Smuzhiyun #define ST7789V_PVGAMCTRL_VP0(n) ((n) & 0xf)
72*4882a593Smuzhiyun #define ST7789V_PVGAMCTRL_VP1(n) ((n) & 0x3f)
73*4882a593Smuzhiyun #define ST7789V_PVGAMCTRL_VP2(n) ((n) & 0x3f)
74*4882a593Smuzhiyun #define ST7789V_PVGAMCTRL_VP4(n) ((n) & 0x1f)
75*4882a593Smuzhiyun #define ST7789V_PVGAMCTRL_VP6(n) ((n) & 0x1f)
76*4882a593Smuzhiyun #define ST7789V_PVGAMCTRL_VP13(n) ((n) & 0xf)
77*4882a593Smuzhiyun #define ST7789V_PVGAMCTRL_VP20(n) ((n) & 0x7f)
78*4882a593Smuzhiyun #define ST7789V_PVGAMCTRL_VP27(n) ((n) & 7)
79*4882a593Smuzhiyun #define ST7789V_PVGAMCTRL_VP36(n) (((n) & 7) << 4)
80*4882a593Smuzhiyun #define ST7789V_PVGAMCTRL_VP43(n) ((n) & 0x7f)
81*4882a593Smuzhiyun #define ST7789V_PVGAMCTRL_VP50(n) ((n) & 0xf)
82*4882a593Smuzhiyun #define ST7789V_PVGAMCTRL_VP57(n) ((n) & 0x1f)
83*4882a593Smuzhiyun #define ST7789V_PVGAMCTRL_VP59(n) ((n) & 0x1f)
84*4882a593Smuzhiyun #define ST7789V_PVGAMCTRL_VP61(n) ((n) & 0x3f)
85*4882a593Smuzhiyun #define ST7789V_PVGAMCTRL_VP62(n) ((n) & 0x3f)
86*4882a593Smuzhiyun #define ST7789V_PVGAMCTRL_VP63(n) (((n) & 0xf) << 4)
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun #define ST7789V_NVGAMCTRL_CMD 0xe1
89*4882a593Smuzhiyun #define ST7789V_NVGAMCTRL_JN0(n) (((n) & 3) << 4)
90*4882a593Smuzhiyun #define ST7789V_NVGAMCTRL_JN1(n) (((n) & 3) << 4)
91*4882a593Smuzhiyun #define ST7789V_NVGAMCTRL_VN0(n) ((n) & 0xf)
92*4882a593Smuzhiyun #define ST7789V_NVGAMCTRL_VN1(n) ((n) & 0x3f)
93*4882a593Smuzhiyun #define ST7789V_NVGAMCTRL_VN2(n) ((n) & 0x3f)
94*4882a593Smuzhiyun #define ST7789V_NVGAMCTRL_VN4(n) ((n) & 0x1f)
95*4882a593Smuzhiyun #define ST7789V_NVGAMCTRL_VN6(n) ((n) & 0x1f)
96*4882a593Smuzhiyun #define ST7789V_NVGAMCTRL_VN13(n) ((n) & 0xf)
97*4882a593Smuzhiyun #define ST7789V_NVGAMCTRL_VN20(n) ((n) & 0x7f)
98*4882a593Smuzhiyun #define ST7789V_NVGAMCTRL_VN27(n) ((n) & 7)
99*4882a593Smuzhiyun #define ST7789V_NVGAMCTRL_VN36(n) (((n) & 7) << 4)
100*4882a593Smuzhiyun #define ST7789V_NVGAMCTRL_VN43(n) ((n) & 0x7f)
101*4882a593Smuzhiyun #define ST7789V_NVGAMCTRL_VN50(n) ((n) & 0xf)
102*4882a593Smuzhiyun #define ST7789V_NVGAMCTRL_VN57(n) ((n) & 0x1f)
103*4882a593Smuzhiyun #define ST7789V_NVGAMCTRL_VN59(n) ((n) & 0x1f)
104*4882a593Smuzhiyun #define ST7789V_NVGAMCTRL_VN61(n) ((n) & 0x3f)
105*4882a593Smuzhiyun #define ST7789V_NVGAMCTRL_VN62(n) ((n) & 0x3f)
106*4882a593Smuzhiyun #define ST7789V_NVGAMCTRL_VN63(n) (((n) & 0xf) << 4)
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun #define ST7789V_TEST(val, func) \
109*4882a593Smuzhiyun do { \
110*4882a593Smuzhiyun if ((val = (func))) \
111*4882a593Smuzhiyun return val; \
112*4882a593Smuzhiyun } while (0)
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun struct st7789v {
115*4882a593Smuzhiyun struct drm_panel panel;
116*4882a593Smuzhiyun struct spi_device *spi;
117*4882a593Smuzhiyun struct gpio_desc *reset;
118*4882a593Smuzhiyun struct regulator *power;
119*4882a593Smuzhiyun };
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun enum st7789v_prefix {
122*4882a593Smuzhiyun ST7789V_COMMAND = 0,
123*4882a593Smuzhiyun ST7789V_DATA = 1,
124*4882a593Smuzhiyun };
125*4882a593Smuzhiyun
panel_to_st7789v(struct drm_panel * panel)126*4882a593Smuzhiyun static inline struct st7789v *panel_to_st7789v(struct drm_panel *panel)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun return container_of(panel, struct st7789v, panel);
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
st7789v_spi_write(struct st7789v * ctx,enum st7789v_prefix prefix,u8 data)131*4882a593Smuzhiyun static int st7789v_spi_write(struct st7789v *ctx, enum st7789v_prefix prefix,
132*4882a593Smuzhiyun u8 data)
133*4882a593Smuzhiyun {
134*4882a593Smuzhiyun struct spi_transfer xfer = { };
135*4882a593Smuzhiyun struct spi_message msg;
136*4882a593Smuzhiyun u16 txbuf = ((prefix & 1) << 8) | data;
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun spi_message_init(&msg);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun xfer.tx_buf = &txbuf;
141*4882a593Smuzhiyun xfer.bits_per_word = 9;
142*4882a593Smuzhiyun xfer.len = sizeof(txbuf);
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun spi_message_add_tail(&xfer, &msg);
145*4882a593Smuzhiyun return spi_sync(ctx->spi, &msg);
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
st7789v_write_command(struct st7789v * ctx,u8 cmd)148*4882a593Smuzhiyun static int st7789v_write_command(struct st7789v *ctx, u8 cmd)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun return st7789v_spi_write(ctx, ST7789V_COMMAND, cmd);
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
st7789v_write_data(struct st7789v * ctx,u8 cmd)153*4882a593Smuzhiyun static int st7789v_write_data(struct st7789v *ctx, u8 cmd)
154*4882a593Smuzhiyun {
155*4882a593Smuzhiyun return st7789v_spi_write(ctx, ST7789V_DATA, cmd);
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun static const struct drm_display_mode default_mode = {
159*4882a593Smuzhiyun .clock = 7000,
160*4882a593Smuzhiyun .hdisplay = 240,
161*4882a593Smuzhiyun .hsync_start = 240 + 38,
162*4882a593Smuzhiyun .hsync_end = 240 + 38 + 10,
163*4882a593Smuzhiyun .htotal = 240 + 38 + 10 + 10,
164*4882a593Smuzhiyun .vdisplay = 320,
165*4882a593Smuzhiyun .vsync_start = 320 + 8,
166*4882a593Smuzhiyun .vsync_end = 320 + 8 + 4,
167*4882a593Smuzhiyun .vtotal = 320 + 8 + 4 + 4,
168*4882a593Smuzhiyun };
169*4882a593Smuzhiyun
st7789v_get_modes(struct drm_panel * panel,struct drm_connector * connector)170*4882a593Smuzhiyun static int st7789v_get_modes(struct drm_panel *panel,
171*4882a593Smuzhiyun struct drm_connector *connector)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun struct drm_display_mode *mode;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun mode = drm_mode_duplicate(connector->dev, &default_mode);
176*4882a593Smuzhiyun if (!mode) {
177*4882a593Smuzhiyun dev_err(panel->dev, "failed to add mode %ux%ux@%u\n",
178*4882a593Smuzhiyun default_mode.hdisplay, default_mode.vdisplay,
179*4882a593Smuzhiyun drm_mode_vrefresh(&default_mode));
180*4882a593Smuzhiyun return -ENOMEM;
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun drm_mode_set_name(mode);
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
186*4882a593Smuzhiyun drm_mode_probed_add(connector, mode);
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun connector->display_info.width_mm = 61;
189*4882a593Smuzhiyun connector->display_info.height_mm = 103;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun return 1;
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun
st7789v_prepare(struct drm_panel * panel)194*4882a593Smuzhiyun static int st7789v_prepare(struct drm_panel *panel)
195*4882a593Smuzhiyun {
196*4882a593Smuzhiyun struct st7789v *ctx = panel_to_st7789v(panel);
197*4882a593Smuzhiyun int ret;
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun ret = regulator_enable(ctx->power);
200*4882a593Smuzhiyun if (ret)
201*4882a593Smuzhiyun return ret;
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun gpiod_set_value(ctx->reset, 1);
204*4882a593Smuzhiyun msleep(30);
205*4882a593Smuzhiyun gpiod_set_value(ctx->reset, 0);
206*4882a593Smuzhiyun msleep(120);
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_command(ctx, MIPI_DCS_EXIT_SLEEP_MODE));
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun /* We need to wait 120ms after a sleep out command */
211*4882a593Smuzhiyun msleep(120);
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_command(ctx,
214*4882a593Smuzhiyun MIPI_DCS_SET_ADDRESS_MODE));
215*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, 0));
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_command(ctx,
218*4882a593Smuzhiyun MIPI_DCS_SET_PIXEL_FORMAT));
219*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx,
220*4882a593Smuzhiyun (MIPI_DCS_PIXEL_FMT_18BIT << 4) |
221*4882a593Smuzhiyun (MIPI_DCS_PIXEL_FMT_18BIT)));
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_command(ctx, ST7789V_PORCTRL_CMD));
224*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, 0xc));
225*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, 0xc));
226*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, 0));
227*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PORCTRL_IDLE_BP(3) |
228*4882a593Smuzhiyun ST7789V_PORCTRL_IDLE_FP(3)));
229*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx,
230*4882a593Smuzhiyun ST7789V_PORCTRL_PARTIAL_BP(3) |
231*4882a593Smuzhiyun ST7789V_PORCTRL_PARTIAL_FP(3)));
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_command(ctx, ST7789V_GCTRL_CMD));
234*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_GCTRL_VGLS(5) |
235*4882a593Smuzhiyun ST7789V_GCTRL_VGHS(3)));
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_command(ctx, ST7789V_VCOMS_CMD));
238*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, 0x2b));
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_command(ctx, ST7789V_LCMCTRL_CMD));
241*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_LCMCTRL_XMH |
242*4882a593Smuzhiyun ST7789V_LCMCTRL_XMX |
243*4882a593Smuzhiyun ST7789V_LCMCTRL_XBGR));
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_command(ctx, ST7789V_VDVVRHEN_CMD));
246*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_VDVVRHEN_CMDEN));
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_command(ctx, ST7789V_VRHS_CMD));
249*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, 0xf));
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_command(ctx, ST7789V_VDVS_CMD));
252*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, 0x20));
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_command(ctx, ST7789V_FRCTRL2_CMD));
255*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, 0xf));
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_command(ctx, ST7789V_PWCTRL1_CMD));
258*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PWCTRL1_MAGIC));
259*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PWCTRL1_AVDD(2) |
260*4882a593Smuzhiyun ST7789V_PWCTRL1_AVCL(2) |
261*4882a593Smuzhiyun ST7789V_PWCTRL1_VDS(1)));
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_command(ctx, ST7789V_PVGAMCTRL_CMD));
264*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PVGAMCTRL_VP63(0xd)));
265*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PVGAMCTRL_VP1(0xca)));
266*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PVGAMCTRL_VP2(0xe)));
267*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PVGAMCTRL_VP4(8)));
268*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PVGAMCTRL_VP6(9)));
269*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PVGAMCTRL_VP13(7)));
270*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PVGAMCTRL_VP20(0x2d)));
271*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PVGAMCTRL_VP27(0xb) |
272*4882a593Smuzhiyun ST7789V_PVGAMCTRL_VP36(3)));
273*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PVGAMCTRL_VP43(0x3d)));
274*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PVGAMCTRL_JP1(3) |
275*4882a593Smuzhiyun ST7789V_PVGAMCTRL_VP50(4)));
276*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PVGAMCTRL_VP57(0xa)));
277*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PVGAMCTRL_VP59(0xa)));
278*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PVGAMCTRL_VP61(0x1b)));
279*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_PVGAMCTRL_VP62(0x28)));
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_command(ctx, ST7789V_NVGAMCTRL_CMD));
282*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_NVGAMCTRL_VN63(0xd)));
283*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_NVGAMCTRL_VN1(0xca)));
284*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_NVGAMCTRL_VN2(0xf)));
285*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_NVGAMCTRL_VN4(8)));
286*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_NVGAMCTRL_VN6(8)));
287*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_NVGAMCTRL_VN13(7)));
288*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_NVGAMCTRL_VN20(0x2e)));
289*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_NVGAMCTRL_VN27(0xc) |
290*4882a593Smuzhiyun ST7789V_NVGAMCTRL_VN36(5)));
291*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_NVGAMCTRL_VN43(0x40)));
292*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_NVGAMCTRL_JN1(3) |
293*4882a593Smuzhiyun ST7789V_NVGAMCTRL_VN50(4)));
294*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_NVGAMCTRL_VN57(9)));
295*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_NVGAMCTRL_VN59(0xb)));
296*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_NVGAMCTRL_VN61(0x1b)));
297*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_NVGAMCTRL_VN62(0x28)));
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_command(ctx, MIPI_DCS_ENTER_INVERT_MODE));
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_command(ctx, ST7789V_RAMCTRL_CMD));
302*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_RAMCTRL_DM_RGB |
303*4882a593Smuzhiyun ST7789V_RAMCTRL_RM_RGB));
304*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_RAMCTRL_EPF(3) |
305*4882a593Smuzhiyun ST7789V_RAMCTRL_MAGIC));
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_command(ctx, ST7789V_RGBCTRL_CMD));
308*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_RGBCTRL_WO |
309*4882a593Smuzhiyun ST7789V_RGBCTRL_RCM(2) |
310*4882a593Smuzhiyun ST7789V_RGBCTRL_VSYNC_HIGH |
311*4882a593Smuzhiyun ST7789V_RGBCTRL_HSYNC_HIGH |
312*4882a593Smuzhiyun ST7789V_RGBCTRL_PCLK_HIGH));
313*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_RGBCTRL_VBP(8)));
314*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_RGBCTRL_HBP(20)));
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun return 0;
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun
st7789v_enable(struct drm_panel * panel)319*4882a593Smuzhiyun static int st7789v_enable(struct drm_panel *panel)
320*4882a593Smuzhiyun {
321*4882a593Smuzhiyun struct st7789v *ctx = panel_to_st7789v(panel);
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun return st7789v_write_command(ctx, MIPI_DCS_SET_DISPLAY_ON);
324*4882a593Smuzhiyun }
325*4882a593Smuzhiyun
st7789v_disable(struct drm_panel * panel)326*4882a593Smuzhiyun static int st7789v_disable(struct drm_panel *panel)
327*4882a593Smuzhiyun {
328*4882a593Smuzhiyun struct st7789v *ctx = panel_to_st7789v(panel);
329*4882a593Smuzhiyun int ret;
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_command(ctx, MIPI_DCS_SET_DISPLAY_OFF));
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun return 0;
334*4882a593Smuzhiyun }
335*4882a593Smuzhiyun
st7789v_unprepare(struct drm_panel * panel)336*4882a593Smuzhiyun static int st7789v_unprepare(struct drm_panel *panel)
337*4882a593Smuzhiyun {
338*4882a593Smuzhiyun struct st7789v *ctx = panel_to_st7789v(panel);
339*4882a593Smuzhiyun int ret;
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun ST7789V_TEST(ret, st7789v_write_command(ctx, MIPI_DCS_ENTER_SLEEP_MODE));
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun regulator_disable(ctx->power);
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun return 0;
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun static const struct drm_panel_funcs st7789v_drm_funcs = {
349*4882a593Smuzhiyun .disable = st7789v_disable,
350*4882a593Smuzhiyun .enable = st7789v_enable,
351*4882a593Smuzhiyun .get_modes = st7789v_get_modes,
352*4882a593Smuzhiyun .prepare = st7789v_prepare,
353*4882a593Smuzhiyun .unprepare = st7789v_unprepare,
354*4882a593Smuzhiyun };
355*4882a593Smuzhiyun
st7789v_probe(struct spi_device * spi)356*4882a593Smuzhiyun static int st7789v_probe(struct spi_device *spi)
357*4882a593Smuzhiyun {
358*4882a593Smuzhiyun struct st7789v *ctx;
359*4882a593Smuzhiyun int ret;
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun ctx = devm_kzalloc(&spi->dev, sizeof(*ctx), GFP_KERNEL);
362*4882a593Smuzhiyun if (!ctx)
363*4882a593Smuzhiyun return -ENOMEM;
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun spi_set_drvdata(spi, ctx);
366*4882a593Smuzhiyun ctx->spi = spi;
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun drm_panel_init(&ctx->panel, &spi->dev, &st7789v_drm_funcs,
369*4882a593Smuzhiyun DRM_MODE_CONNECTOR_DPI);
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun ctx->power = devm_regulator_get(&spi->dev, "power");
372*4882a593Smuzhiyun if (IS_ERR(ctx->power))
373*4882a593Smuzhiyun return PTR_ERR(ctx->power);
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun ctx->reset = devm_gpiod_get(&spi->dev, "reset", GPIOD_OUT_LOW);
376*4882a593Smuzhiyun if (IS_ERR(ctx->reset)) {
377*4882a593Smuzhiyun dev_err(&spi->dev, "Couldn't get our reset line\n");
378*4882a593Smuzhiyun return PTR_ERR(ctx->reset);
379*4882a593Smuzhiyun }
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun ret = drm_panel_of_backlight(&ctx->panel);
382*4882a593Smuzhiyun if (ret)
383*4882a593Smuzhiyun return ret;
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun drm_panel_add(&ctx->panel);
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun return 0;
388*4882a593Smuzhiyun }
389*4882a593Smuzhiyun
st7789v_remove(struct spi_device * spi)390*4882a593Smuzhiyun static int st7789v_remove(struct spi_device *spi)
391*4882a593Smuzhiyun {
392*4882a593Smuzhiyun struct st7789v *ctx = spi_get_drvdata(spi);
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun drm_panel_remove(&ctx->panel);
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun return 0;
397*4882a593Smuzhiyun }
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun static const struct of_device_id st7789v_of_match[] = {
400*4882a593Smuzhiyun { .compatible = "sitronix,st7789v" },
401*4882a593Smuzhiyun { }
402*4882a593Smuzhiyun };
403*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, st7789v_of_match);
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun static struct spi_driver st7789v_driver = {
406*4882a593Smuzhiyun .probe = st7789v_probe,
407*4882a593Smuzhiyun .remove = st7789v_remove,
408*4882a593Smuzhiyun .driver = {
409*4882a593Smuzhiyun .name = "st7789v",
410*4882a593Smuzhiyun .of_match_table = st7789v_of_match,
411*4882a593Smuzhiyun },
412*4882a593Smuzhiyun };
413*4882a593Smuzhiyun module_spi_driver(st7789v_driver);
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
416*4882a593Smuzhiyun MODULE_DESCRIPTION("Sitronix st7789v LCD Driver");
417*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
418