1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun // Copyright (C) 2019, Michael Srba
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #include <linux/delay.h>
5*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
6*4882a593Smuzhiyun #include <linux/module.h>
7*4882a593Smuzhiyun #include <linux/of.h>
8*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <video/mipi_display.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <drm/drm_mipi_dsi.h>
13*4882a593Smuzhiyun #include <drm/drm_modes.h>
14*4882a593Smuzhiyun #include <drm/drm_panel.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun struct s6e88a0_ams452ef01 {
17*4882a593Smuzhiyun struct drm_panel panel;
18*4882a593Smuzhiyun struct mipi_dsi_device *dsi;
19*4882a593Smuzhiyun struct regulator_bulk_data supplies[2];
20*4882a593Smuzhiyun struct gpio_desc *reset_gpio;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun bool prepared;
23*4882a593Smuzhiyun };
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun static inline struct
to_s6e88a0_ams452ef01(struct drm_panel * panel)26*4882a593Smuzhiyun s6e88a0_ams452ef01 *to_s6e88a0_ams452ef01(struct drm_panel *panel)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun return container_of(panel, struct s6e88a0_ams452ef01, panel);
29*4882a593Smuzhiyun }
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #define dsi_dcs_write_seq(dsi, seq...) do { \
32*4882a593Smuzhiyun static const u8 d[] = { seq }; \
33*4882a593Smuzhiyun int ret; \
34*4882a593Smuzhiyun ret = mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d)); \
35*4882a593Smuzhiyun if (ret < 0) \
36*4882a593Smuzhiyun return ret; \
37*4882a593Smuzhiyun } while (0)
38*4882a593Smuzhiyun
s6e88a0_ams452ef01_reset(struct s6e88a0_ams452ef01 * ctx)39*4882a593Smuzhiyun static void s6e88a0_ams452ef01_reset(struct s6e88a0_ams452ef01 *ctx)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun gpiod_set_value_cansleep(ctx->reset_gpio, 1);
42*4882a593Smuzhiyun usleep_range(5000, 6000);
43*4882a593Smuzhiyun gpiod_set_value_cansleep(ctx->reset_gpio, 0);
44*4882a593Smuzhiyun usleep_range(1000, 2000);
45*4882a593Smuzhiyun gpiod_set_value_cansleep(ctx->reset_gpio, 1);
46*4882a593Smuzhiyun usleep_range(10000, 11000);
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
s6e88a0_ams452ef01_on(struct s6e88a0_ams452ef01 * ctx)49*4882a593Smuzhiyun static int s6e88a0_ams452ef01_on(struct s6e88a0_ams452ef01 *ctx)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun struct mipi_dsi_device *dsi = ctx->dsi;
52*4882a593Smuzhiyun struct device *dev = &dsi->dev;
53*4882a593Smuzhiyun int ret;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun dsi->mode_flags |= MIPI_DSI_MODE_LPM;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); // enable LEVEL2 commands
58*4882a593Smuzhiyun dsi_dcs_write_seq(dsi, 0xcc, 0x4c); // set Pixel Clock Divider polarity
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
61*4882a593Smuzhiyun if (ret < 0) {
62*4882a593Smuzhiyun dev_err(dev, "Failed to exit sleep mode: %d\n", ret);
63*4882a593Smuzhiyun return ret;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun msleep(120);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun // set default brightness/gama
68*4882a593Smuzhiyun dsi_dcs_write_seq(dsi, 0xca,
69*4882a593Smuzhiyun 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, // V255 RR,GG,BB
70*4882a593Smuzhiyun 0x80, 0x80, 0x80, // V203 R,G,B
71*4882a593Smuzhiyun 0x80, 0x80, 0x80, // V151 R,G,B
72*4882a593Smuzhiyun 0x80, 0x80, 0x80, // V87 R,G,B
73*4882a593Smuzhiyun 0x80, 0x80, 0x80, // V51 R,G,B
74*4882a593Smuzhiyun 0x80, 0x80, 0x80, // V35 R,G,B
75*4882a593Smuzhiyun 0x80, 0x80, 0x80, // V23 R,G,B
76*4882a593Smuzhiyun 0x80, 0x80, 0x80, // V11 R,G,B
77*4882a593Smuzhiyun 0x6b, 0x68, 0x71, // V3 R,G,B
78*4882a593Smuzhiyun 0x00, 0x00, 0x00); // V1 R,G,B
79*4882a593Smuzhiyun // set default Amoled Off Ratio
80*4882a593Smuzhiyun dsi_dcs_write_seq(dsi, 0xb2, 0x40, 0x0a, 0x17, 0x00, 0x0a);
81*4882a593Smuzhiyun dsi_dcs_write_seq(dsi, 0xb6, 0x2c, 0x0b); // set default elvss voltage
82*4882a593Smuzhiyun dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00);
83*4882a593Smuzhiyun dsi_dcs_write_seq(dsi, 0xf7, 0x03); // gamma/aor update
84*4882a593Smuzhiyun dsi_dcs_write_seq(dsi, 0xf0, 0xa5, 0xa5); // disable LEVEL2 commands
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun ret = mipi_dsi_dcs_set_display_on(dsi);
87*4882a593Smuzhiyun if (ret < 0) {
88*4882a593Smuzhiyun dev_err(dev, "Failed to set display on: %d\n", ret);
89*4882a593Smuzhiyun return ret;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun return 0;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
s6e88a0_ams452ef01_off(struct s6e88a0_ams452ef01 * ctx)95*4882a593Smuzhiyun static int s6e88a0_ams452ef01_off(struct s6e88a0_ams452ef01 *ctx)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun struct mipi_dsi_device *dsi = ctx->dsi;
98*4882a593Smuzhiyun struct device *dev = &dsi->dev;
99*4882a593Smuzhiyun int ret;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun ret = mipi_dsi_dcs_set_display_off(dsi);
104*4882a593Smuzhiyun if (ret < 0) {
105*4882a593Smuzhiyun dev_err(dev, "Failed to set display off: %d\n", ret);
106*4882a593Smuzhiyun return ret;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun msleep(35);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
111*4882a593Smuzhiyun if (ret < 0) {
112*4882a593Smuzhiyun dev_err(dev, "Failed to enter sleep mode: %d\n", ret);
113*4882a593Smuzhiyun return ret;
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun msleep(120);
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun return 0;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
s6e88a0_ams452ef01_prepare(struct drm_panel * panel)120*4882a593Smuzhiyun static int s6e88a0_ams452ef01_prepare(struct drm_panel *panel)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun struct s6e88a0_ams452ef01 *ctx = to_s6e88a0_ams452ef01(panel);
123*4882a593Smuzhiyun struct device *dev = &ctx->dsi->dev;
124*4882a593Smuzhiyun int ret;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun if (ctx->prepared)
127*4882a593Smuzhiyun return 0;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
130*4882a593Smuzhiyun if (ret < 0) {
131*4882a593Smuzhiyun dev_err(dev, "Failed to enable regulators: %d\n", ret);
132*4882a593Smuzhiyun return ret;
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun s6e88a0_ams452ef01_reset(ctx);
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun ret = s6e88a0_ams452ef01_on(ctx);
138*4882a593Smuzhiyun if (ret < 0) {
139*4882a593Smuzhiyun dev_err(dev, "Failed to initialize panel: %d\n", ret);
140*4882a593Smuzhiyun gpiod_set_value_cansleep(ctx->reset_gpio, 0);
141*4882a593Smuzhiyun regulator_bulk_disable(ARRAY_SIZE(ctx->supplies),
142*4882a593Smuzhiyun ctx->supplies);
143*4882a593Smuzhiyun return ret;
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun ctx->prepared = true;
147*4882a593Smuzhiyun return 0;
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
s6e88a0_ams452ef01_unprepare(struct drm_panel * panel)150*4882a593Smuzhiyun static int s6e88a0_ams452ef01_unprepare(struct drm_panel *panel)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun struct s6e88a0_ams452ef01 *ctx = to_s6e88a0_ams452ef01(panel);
153*4882a593Smuzhiyun struct device *dev = &ctx->dsi->dev;
154*4882a593Smuzhiyun int ret;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun if (!ctx->prepared)
157*4882a593Smuzhiyun return 0;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun ret = s6e88a0_ams452ef01_off(ctx);
160*4882a593Smuzhiyun if (ret < 0)
161*4882a593Smuzhiyun dev_err(dev, "Failed to un-initialize panel: %d\n", ret);
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun gpiod_set_value_cansleep(ctx->reset_gpio, 0);
164*4882a593Smuzhiyun regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun ctx->prepared = false;
167*4882a593Smuzhiyun return 0;
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun static const struct drm_display_mode s6e88a0_ams452ef01_mode = {
171*4882a593Smuzhiyun .clock = (540 + 88 + 4 + 20) * (960 + 14 + 2 + 8) * 60 / 1000,
172*4882a593Smuzhiyun .hdisplay = 540,
173*4882a593Smuzhiyun .hsync_start = 540 + 88,
174*4882a593Smuzhiyun .hsync_end = 540 + 88 + 4,
175*4882a593Smuzhiyun .htotal = 540 + 88 + 4 + 20,
176*4882a593Smuzhiyun .vdisplay = 960,
177*4882a593Smuzhiyun .vsync_start = 960 + 14,
178*4882a593Smuzhiyun .vsync_end = 960 + 14 + 2,
179*4882a593Smuzhiyun .vtotal = 960 + 14 + 2 + 8,
180*4882a593Smuzhiyun .width_mm = 56,
181*4882a593Smuzhiyun .height_mm = 100,
182*4882a593Smuzhiyun };
183*4882a593Smuzhiyun
s6e88a0_ams452ef01_get_modes(struct drm_panel * panel,struct drm_connector * connector)184*4882a593Smuzhiyun static int s6e88a0_ams452ef01_get_modes(struct drm_panel *panel,
185*4882a593Smuzhiyun struct drm_connector *connector)
186*4882a593Smuzhiyun {
187*4882a593Smuzhiyun struct drm_display_mode *mode;
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun mode = drm_mode_duplicate(connector->dev, &s6e88a0_ams452ef01_mode);
190*4882a593Smuzhiyun if (!mode)
191*4882a593Smuzhiyun return -ENOMEM;
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun drm_mode_set_name(mode);
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
196*4882a593Smuzhiyun connector->display_info.width_mm = mode->width_mm;
197*4882a593Smuzhiyun connector->display_info.height_mm = mode->height_mm;
198*4882a593Smuzhiyun drm_mode_probed_add(connector, mode);
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun return 1;
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun static const struct drm_panel_funcs s6e88a0_ams452ef01_panel_funcs = {
204*4882a593Smuzhiyun .unprepare = s6e88a0_ams452ef01_unprepare,
205*4882a593Smuzhiyun .prepare = s6e88a0_ams452ef01_prepare,
206*4882a593Smuzhiyun .get_modes = s6e88a0_ams452ef01_get_modes,
207*4882a593Smuzhiyun };
208*4882a593Smuzhiyun
s6e88a0_ams452ef01_probe(struct mipi_dsi_device * dsi)209*4882a593Smuzhiyun static int s6e88a0_ams452ef01_probe(struct mipi_dsi_device *dsi)
210*4882a593Smuzhiyun {
211*4882a593Smuzhiyun struct device *dev = &dsi->dev;
212*4882a593Smuzhiyun struct s6e88a0_ams452ef01 *ctx;
213*4882a593Smuzhiyun int ret;
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
216*4882a593Smuzhiyun if (!ctx)
217*4882a593Smuzhiyun return -ENOMEM;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun ctx->supplies[0].supply = "vdd3";
220*4882a593Smuzhiyun ctx->supplies[1].supply = "vci";
221*4882a593Smuzhiyun ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ctx->supplies),
222*4882a593Smuzhiyun ctx->supplies);
223*4882a593Smuzhiyun if (ret < 0) {
224*4882a593Smuzhiyun dev_err(dev, "Failed to get regulators: %d\n", ret);
225*4882a593Smuzhiyun return ret;
226*4882a593Smuzhiyun }
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
229*4882a593Smuzhiyun if (IS_ERR(ctx->reset_gpio)) {
230*4882a593Smuzhiyun ret = PTR_ERR(ctx->reset_gpio);
231*4882a593Smuzhiyun dev_err(dev, "Failed to get reset-gpios: %d\n", ret);
232*4882a593Smuzhiyun return ret;
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun ctx->dsi = dsi;
236*4882a593Smuzhiyun mipi_dsi_set_drvdata(dsi, ctx);
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun dsi->lanes = 2;
239*4882a593Smuzhiyun dsi->format = MIPI_DSI_FMT_RGB888;
240*4882a593Smuzhiyun dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun drm_panel_init(&ctx->panel, dev, &s6e88a0_ams452ef01_panel_funcs,
243*4882a593Smuzhiyun DRM_MODE_CONNECTOR_DSI);
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun drm_panel_add(&ctx->panel);
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun ret = mipi_dsi_attach(dsi);
248*4882a593Smuzhiyun if (ret < 0) {
249*4882a593Smuzhiyun dev_err(dev, "Failed to attach to DSI host: %d\n", ret);
250*4882a593Smuzhiyun return ret;
251*4882a593Smuzhiyun }
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun return 0;
254*4882a593Smuzhiyun }
255*4882a593Smuzhiyun
s6e88a0_ams452ef01_remove(struct mipi_dsi_device * dsi)256*4882a593Smuzhiyun static int s6e88a0_ams452ef01_remove(struct mipi_dsi_device *dsi)
257*4882a593Smuzhiyun {
258*4882a593Smuzhiyun struct s6e88a0_ams452ef01 *ctx = mipi_dsi_get_drvdata(dsi);
259*4882a593Smuzhiyun int ret;
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun ret = mipi_dsi_detach(dsi);
262*4882a593Smuzhiyun if (ret < 0)
263*4882a593Smuzhiyun dev_err(&dsi->dev, "Failed to detach from DSI host: %d\n", ret);
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun drm_panel_remove(&ctx->panel);
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun return 0;
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun static const struct of_device_id s6e88a0_ams452ef01_of_match[] = {
271*4882a593Smuzhiyun { .compatible = "samsung,s6e88a0-ams452ef01" },
272*4882a593Smuzhiyun { /* sentinel */ },
273*4882a593Smuzhiyun };
274*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, s6e88a0_ams452ef01_of_match);
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun static struct mipi_dsi_driver s6e88a0_ams452ef01_driver = {
277*4882a593Smuzhiyun .probe = s6e88a0_ams452ef01_probe,
278*4882a593Smuzhiyun .remove = s6e88a0_ams452ef01_remove,
279*4882a593Smuzhiyun .driver = {
280*4882a593Smuzhiyun .name = "panel-s6e88a0-ams452ef01",
281*4882a593Smuzhiyun .of_match_table = s6e88a0_ams452ef01_of_match,
282*4882a593Smuzhiyun },
283*4882a593Smuzhiyun };
284*4882a593Smuzhiyun module_mipi_dsi_driver(s6e88a0_ams452ef01_driver);
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun MODULE_AUTHOR("Michael Srba <Michael.Srba@seznam.cz>");
287*4882a593Smuzhiyun MODULE_DESCRIPTION("MIPI-DSI based Panel Driver for AMS452EF01 AMOLED LCD with a S6E88A0 controller");
288*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
289