1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Novatek NT39016 TFT LCD panel driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2017, Maarten ter Huurne <maarten@treewalker.org>
6*4882a593Smuzhiyun * Copyright (C) 2019, Paul Cercueil <paul@crapouillou.net>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/delay.h>
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
12*4882a593Smuzhiyun #include <linux/media-bus-format.h>
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/of.h>
15*4882a593Smuzhiyun #include <linux/of_device.h>
16*4882a593Smuzhiyun #include <linux/regmap.h>
17*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
18*4882a593Smuzhiyun #include <linux/spi/spi.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include <drm/drm_modes.h>
21*4882a593Smuzhiyun #include <drm/drm_panel.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun enum nt39016_regs {
24*4882a593Smuzhiyun NT39016_REG_SYSTEM,
25*4882a593Smuzhiyun NT39016_REG_TIMING,
26*4882a593Smuzhiyun NT39016_REG_OP,
27*4882a593Smuzhiyun NT39016_REG_DATA_IN,
28*4882a593Smuzhiyun NT39016_REG_SRC_TIMING_DELAY,
29*4882a593Smuzhiyun NT39016_REG_GATE_TIMING_DELAY,
30*4882a593Smuzhiyun NT39016_REG_RESERVED,
31*4882a593Smuzhiyun NT39016_REG_INITIAL_FUNC,
32*4882a593Smuzhiyun NT39016_REG_CONTRAST,
33*4882a593Smuzhiyun NT39016_REG_BRIGHTNESS,
34*4882a593Smuzhiyun NT39016_REG_HUE_SATURATION,
35*4882a593Smuzhiyun NT39016_REG_RB_SUBCONTRAST,
36*4882a593Smuzhiyun NT39016_REG_R_SUBBRIGHTNESS,
37*4882a593Smuzhiyun NT39016_REG_B_SUBBRIGHTNESS,
38*4882a593Smuzhiyun NT39016_REG_VCOMDC,
39*4882a593Smuzhiyun NT39016_REG_VCOMAC,
40*4882a593Smuzhiyun NT39016_REG_VGAM2,
41*4882a593Smuzhiyun NT39016_REG_VGAM34,
42*4882a593Smuzhiyun NT39016_REG_VGAM56,
43*4882a593Smuzhiyun NT39016_REG_VCOMDC_TRIM = 0x1e,
44*4882a593Smuzhiyun NT39016_REG_DISPLAY_MODE = 0x20,
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #define NT39016_SYSTEM_RESET_N BIT(0)
48*4882a593Smuzhiyun #define NT39016_SYSTEM_STANDBY BIT(1)
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun struct nt39016_panel_info {
51*4882a593Smuzhiyun const struct drm_display_mode *display_modes;
52*4882a593Smuzhiyun unsigned int num_modes;
53*4882a593Smuzhiyun u16 width_mm, height_mm;
54*4882a593Smuzhiyun u32 bus_format, bus_flags;
55*4882a593Smuzhiyun };
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun struct nt39016 {
58*4882a593Smuzhiyun struct drm_panel drm_panel;
59*4882a593Smuzhiyun struct regmap *map;
60*4882a593Smuzhiyun struct regulator *supply;
61*4882a593Smuzhiyun const struct nt39016_panel_info *panel_info;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun struct gpio_desc *reset_gpio;
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun
to_nt39016(struct drm_panel * panel)66*4882a593Smuzhiyun static inline struct nt39016 *to_nt39016(struct drm_panel *panel)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun return container_of(panel, struct nt39016, drm_panel);
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun #define RV(REG, VAL) { .reg = (REG), .def = (VAL), .delay_us = 2 }
72*4882a593Smuzhiyun static const struct reg_sequence nt39016_panel_regs[] = {
73*4882a593Smuzhiyun RV(NT39016_REG_SYSTEM, 0x00),
74*4882a593Smuzhiyun RV(NT39016_REG_TIMING, 0x00),
75*4882a593Smuzhiyun RV(NT39016_REG_OP, 0x03),
76*4882a593Smuzhiyun RV(NT39016_REG_DATA_IN, 0xCC),
77*4882a593Smuzhiyun RV(NT39016_REG_SRC_TIMING_DELAY, 0x46),
78*4882a593Smuzhiyun RV(NT39016_REG_GATE_TIMING_DELAY, 0x05),
79*4882a593Smuzhiyun RV(NT39016_REG_RESERVED, 0x00),
80*4882a593Smuzhiyun RV(NT39016_REG_INITIAL_FUNC, 0x00),
81*4882a593Smuzhiyun RV(NT39016_REG_CONTRAST, 0x08),
82*4882a593Smuzhiyun RV(NT39016_REG_BRIGHTNESS, 0x40),
83*4882a593Smuzhiyun RV(NT39016_REG_HUE_SATURATION, 0x88),
84*4882a593Smuzhiyun RV(NT39016_REG_RB_SUBCONTRAST, 0x88),
85*4882a593Smuzhiyun RV(NT39016_REG_R_SUBBRIGHTNESS, 0x20),
86*4882a593Smuzhiyun RV(NT39016_REG_B_SUBBRIGHTNESS, 0x20),
87*4882a593Smuzhiyun RV(NT39016_REG_VCOMDC, 0x67),
88*4882a593Smuzhiyun RV(NT39016_REG_VCOMAC, 0xA4),
89*4882a593Smuzhiyun RV(NT39016_REG_VGAM2, 0x04),
90*4882a593Smuzhiyun RV(NT39016_REG_VGAM34, 0x24),
91*4882a593Smuzhiyun RV(NT39016_REG_VGAM56, 0x24),
92*4882a593Smuzhiyun RV(NT39016_REG_DISPLAY_MODE, 0x00),
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun #undef RV
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun static const struct regmap_range nt39016_regmap_no_ranges[] = {
98*4882a593Smuzhiyun regmap_reg_range(0x13, 0x1D),
99*4882a593Smuzhiyun regmap_reg_range(0x1F, 0x1F),
100*4882a593Smuzhiyun };
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun static const struct regmap_access_table nt39016_regmap_access_table = {
103*4882a593Smuzhiyun .no_ranges = nt39016_regmap_no_ranges,
104*4882a593Smuzhiyun .n_no_ranges = ARRAY_SIZE(nt39016_regmap_no_ranges),
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun static const struct regmap_config nt39016_regmap_config = {
108*4882a593Smuzhiyun .reg_bits = 6,
109*4882a593Smuzhiyun .pad_bits = 2,
110*4882a593Smuzhiyun .val_bits = 8,
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun .max_register = NT39016_REG_DISPLAY_MODE,
113*4882a593Smuzhiyun .wr_table = &nt39016_regmap_access_table,
114*4882a593Smuzhiyun .write_flag_mask = 0x02,
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun .cache_type = REGCACHE_FLAT,
117*4882a593Smuzhiyun };
118*4882a593Smuzhiyun
nt39016_prepare(struct drm_panel * drm_panel)119*4882a593Smuzhiyun static int nt39016_prepare(struct drm_panel *drm_panel)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun struct nt39016 *panel = to_nt39016(drm_panel);
122*4882a593Smuzhiyun int err;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun err = regulator_enable(panel->supply);
125*4882a593Smuzhiyun if (err) {
126*4882a593Smuzhiyun dev_err(drm_panel->dev, "Failed to enable power supply: %d\n", err);
127*4882a593Smuzhiyun return err;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun /*
131*4882a593Smuzhiyun * Reset the NT39016.
132*4882a593Smuzhiyun * The documentation says the reset pulse should be at least 40 us to
133*4882a593Smuzhiyun * pass the glitch filter, but when testing I see some resets fail and
134*4882a593Smuzhiyun * some succeed when using a 70 us delay, so we use 100 us instead.
135*4882a593Smuzhiyun */
136*4882a593Smuzhiyun gpiod_set_value_cansleep(panel->reset_gpio, 1);
137*4882a593Smuzhiyun usleep_range(100, 1000);
138*4882a593Smuzhiyun gpiod_set_value_cansleep(panel->reset_gpio, 0);
139*4882a593Smuzhiyun udelay(2);
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun /* Init all registers. */
142*4882a593Smuzhiyun err = regmap_multi_reg_write(panel->map, nt39016_panel_regs,
143*4882a593Smuzhiyun ARRAY_SIZE(nt39016_panel_regs));
144*4882a593Smuzhiyun if (err) {
145*4882a593Smuzhiyun dev_err(drm_panel->dev, "Failed to init registers: %d\n", err);
146*4882a593Smuzhiyun goto err_disable_regulator;
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun return 0;
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun err_disable_regulator:
152*4882a593Smuzhiyun regulator_disable(panel->supply);
153*4882a593Smuzhiyun return err;
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun
nt39016_unprepare(struct drm_panel * drm_panel)156*4882a593Smuzhiyun static int nt39016_unprepare(struct drm_panel *drm_panel)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun struct nt39016 *panel = to_nt39016(drm_panel);
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun gpiod_set_value_cansleep(panel->reset_gpio, 1);
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun regulator_disable(panel->supply);
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun return 0;
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun
nt39016_enable(struct drm_panel * drm_panel)167*4882a593Smuzhiyun static int nt39016_enable(struct drm_panel *drm_panel)
168*4882a593Smuzhiyun {
169*4882a593Smuzhiyun struct nt39016 *panel = to_nt39016(drm_panel);
170*4882a593Smuzhiyun int ret;
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun ret = regmap_write(panel->map, NT39016_REG_SYSTEM,
173*4882a593Smuzhiyun NT39016_SYSTEM_RESET_N | NT39016_SYSTEM_STANDBY);
174*4882a593Smuzhiyun if (ret) {
175*4882a593Smuzhiyun dev_err(drm_panel->dev, "Unable to enable panel: %d\n", ret);
176*4882a593Smuzhiyun return ret;
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun if (drm_panel->backlight) {
180*4882a593Smuzhiyun /* Wait for the picture to be ready before enabling backlight */
181*4882a593Smuzhiyun msleep(150);
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun return 0;
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
nt39016_disable(struct drm_panel * drm_panel)187*4882a593Smuzhiyun static int nt39016_disable(struct drm_panel *drm_panel)
188*4882a593Smuzhiyun {
189*4882a593Smuzhiyun struct nt39016 *panel = to_nt39016(drm_panel);
190*4882a593Smuzhiyun int err;
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun err = regmap_write(panel->map, NT39016_REG_SYSTEM,
193*4882a593Smuzhiyun NT39016_SYSTEM_RESET_N);
194*4882a593Smuzhiyun if (err) {
195*4882a593Smuzhiyun dev_err(drm_panel->dev, "Unable to disable panel: %d\n", err);
196*4882a593Smuzhiyun return err;
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun return 0;
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun
nt39016_get_modes(struct drm_panel * drm_panel,struct drm_connector * connector)202*4882a593Smuzhiyun static int nt39016_get_modes(struct drm_panel *drm_panel,
203*4882a593Smuzhiyun struct drm_connector *connector)
204*4882a593Smuzhiyun {
205*4882a593Smuzhiyun struct nt39016 *panel = to_nt39016(drm_panel);
206*4882a593Smuzhiyun const struct nt39016_panel_info *panel_info = panel->panel_info;
207*4882a593Smuzhiyun struct drm_display_mode *mode;
208*4882a593Smuzhiyun unsigned int i;
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun for (i = 0; i < panel_info->num_modes; i++) {
211*4882a593Smuzhiyun mode = drm_mode_duplicate(connector->dev,
212*4882a593Smuzhiyun &panel_info->display_modes[i]);
213*4882a593Smuzhiyun if (!mode)
214*4882a593Smuzhiyun return -ENOMEM;
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun drm_mode_set_name(mode);
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun mode->type = DRM_MODE_TYPE_DRIVER;
219*4882a593Smuzhiyun if (panel_info->num_modes == 1)
220*4882a593Smuzhiyun mode->type |= DRM_MODE_TYPE_PREFERRED;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun drm_mode_probed_add(connector, mode);
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun connector->display_info.bpc = 8;
226*4882a593Smuzhiyun connector->display_info.width_mm = panel_info->width_mm;
227*4882a593Smuzhiyun connector->display_info.height_mm = panel_info->height_mm;
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun drm_display_info_set_bus_formats(&connector->display_info,
230*4882a593Smuzhiyun &panel_info->bus_format, 1);
231*4882a593Smuzhiyun connector->display_info.bus_flags = panel_info->bus_flags;
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun return panel_info->num_modes;
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun static const struct drm_panel_funcs nt39016_funcs = {
237*4882a593Smuzhiyun .prepare = nt39016_prepare,
238*4882a593Smuzhiyun .unprepare = nt39016_unprepare,
239*4882a593Smuzhiyun .enable = nt39016_enable,
240*4882a593Smuzhiyun .disable = nt39016_disable,
241*4882a593Smuzhiyun .get_modes = nt39016_get_modes,
242*4882a593Smuzhiyun };
243*4882a593Smuzhiyun
nt39016_probe(struct spi_device * spi)244*4882a593Smuzhiyun static int nt39016_probe(struct spi_device *spi)
245*4882a593Smuzhiyun {
246*4882a593Smuzhiyun struct device *dev = &spi->dev;
247*4882a593Smuzhiyun struct nt39016 *panel;
248*4882a593Smuzhiyun int err;
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
251*4882a593Smuzhiyun if (!panel)
252*4882a593Smuzhiyun return -ENOMEM;
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun spi_set_drvdata(spi, panel);
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun panel->panel_info = of_device_get_match_data(dev);
257*4882a593Smuzhiyun if (!panel->panel_info)
258*4882a593Smuzhiyun return -EINVAL;
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun panel->supply = devm_regulator_get(dev, "power");
261*4882a593Smuzhiyun if (IS_ERR(panel->supply)) {
262*4882a593Smuzhiyun dev_err(dev, "Failed to get power supply\n");
263*4882a593Smuzhiyun return PTR_ERR(panel->supply);
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun panel->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
267*4882a593Smuzhiyun if (IS_ERR(panel->reset_gpio)) {
268*4882a593Smuzhiyun dev_err(dev, "Failed to get reset GPIO\n");
269*4882a593Smuzhiyun return PTR_ERR(panel->reset_gpio);
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun spi->bits_per_word = 8;
273*4882a593Smuzhiyun spi->mode = SPI_MODE_3 | SPI_3WIRE;
274*4882a593Smuzhiyun err = spi_setup(spi);
275*4882a593Smuzhiyun if (err) {
276*4882a593Smuzhiyun dev_err(dev, "Failed to setup SPI\n");
277*4882a593Smuzhiyun return err;
278*4882a593Smuzhiyun }
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun panel->map = devm_regmap_init_spi(spi, &nt39016_regmap_config);
281*4882a593Smuzhiyun if (IS_ERR(panel->map)) {
282*4882a593Smuzhiyun dev_err(dev, "Failed to init regmap\n");
283*4882a593Smuzhiyun return PTR_ERR(panel->map);
284*4882a593Smuzhiyun }
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun drm_panel_init(&panel->drm_panel, dev, &nt39016_funcs,
287*4882a593Smuzhiyun DRM_MODE_CONNECTOR_DPI);
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun err = drm_panel_of_backlight(&panel->drm_panel);
290*4882a593Smuzhiyun if (err) {
291*4882a593Smuzhiyun if (err != -EPROBE_DEFER)
292*4882a593Smuzhiyun dev_err(dev, "Failed to get backlight handle\n");
293*4882a593Smuzhiyun return err;
294*4882a593Smuzhiyun }
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun drm_panel_add(&panel->drm_panel);
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun return 0;
299*4882a593Smuzhiyun }
300*4882a593Smuzhiyun
nt39016_remove(struct spi_device * spi)301*4882a593Smuzhiyun static int nt39016_remove(struct spi_device *spi)
302*4882a593Smuzhiyun {
303*4882a593Smuzhiyun struct nt39016 *panel = spi_get_drvdata(spi);
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun drm_panel_remove(&panel->drm_panel);
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun nt39016_disable(&panel->drm_panel);
308*4882a593Smuzhiyun nt39016_unprepare(&panel->drm_panel);
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun return 0;
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun static const struct drm_display_mode kd035g6_display_modes[] = {
314*4882a593Smuzhiyun { /* 60 Hz */
315*4882a593Smuzhiyun .clock = 6000,
316*4882a593Smuzhiyun .hdisplay = 320,
317*4882a593Smuzhiyun .hsync_start = 320 + 10,
318*4882a593Smuzhiyun .hsync_end = 320 + 10 + 50,
319*4882a593Smuzhiyun .htotal = 320 + 10 + 50 + 20,
320*4882a593Smuzhiyun .vdisplay = 240,
321*4882a593Smuzhiyun .vsync_start = 240 + 5,
322*4882a593Smuzhiyun .vsync_end = 240 + 5 + 1,
323*4882a593Smuzhiyun .vtotal = 240 + 5 + 1 + 4,
324*4882a593Smuzhiyun .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
325*4882a593Smuzhiyun },
326*4882a593Smuzhiyun { /* 50 Hz */
327*4882a593Smuzhiyun .clock = 5400,
328*4882a593Smuzhiyun .hdisplay = 320,
329*4882a593Smuzhiyun .hsync_start = 320 + 42,
330*4882a593Smuzhiyun .hsync_end = 320 + 42 + 50,
331*4882a593Smuzhiyun .htotal = 320 + 42 + 50 + 20,
332*4882a593Smuzhiyun .vdisplay = 240,
333*4882a593Smuzhiyun .vsync_start = 240 + 5,
334*4882a593Smuzhiyun .vsync_end = 240 + 5 + 1,
335*4882a593Smuzhiyun .vtotal = 240 + 5 + 1 + 4,
336*4882a593Smuzhiyun .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
337*4882a593Smuzhiyun },
338*4882a593Smuzhiyun };
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun static const struct nt39016_panel_info kd035g6_info = {
341*4882a593Smuzhiyun .display_modes = kd035g6_display_modes,
342*4882a593Smuzhiyun .num_modes = ARRAY_SIZE(kd035g6_display_modes),
343*4882a593Smuzhiyun .width_mm = 71,
344*4882a593Smuzhiyun .height_mm = 53,
345*4882a593Smuzhiyun .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
346*4882a593Smuzhiyun .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
347*4882a593Smuzhiyun };
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun static const struct of_device_id nt39016_of_match[] = {
350*4882a593Smuzhiyun { .compatible = "kingdisplay,kd035g6-54nt", .data = &kd035g6_info },
351*4882a593Smuzhiyun { /* sentinel */ }
352*4882a593Smuzhiyun };
353*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, nt39016_of_match);
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun static struct spi_driver nt39016_driver = {
356*4882a593Smuzhiyun .driver = {
357*4882a593Smuzhiyun .name = "nt39016",
358*4882a593Smuzhiyun .of_match_table = nt39016_of_match,
359*4882a593Smuzhiyun },
360*4882a593Smuzhiyun .probe = nt39016_probe,
361*4882a593Smuzhiyun .remove = nt39016_remove,
362*4882a593Smuzhiyun };
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun module_spi_driver(nt39016_driver);
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun MODULE_AUTHOR("Maarten ter Huurne <maarten@treewalker.org>");
367*4882a593Smuzhiyun MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
368*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
369