xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/panel/panel-lg-lb035q02.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * LG.Philips LB035Q02 LCD Panel Driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2019 Texas Instruments Incorporated
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Based on the omapdrm-specific panel-lgphilips-lb035q02 driver
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * Copyright (C) 2013 Texas Instruments Incorporated
10*4882a593Smuzhiyun  * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
11*4882a593Smuzhiyun  *
12*4882a593Smuzhiyun  * Based on a driver by: Steve Sakoman <steve@sakoman.com>
13*4882a593Smuzhiyun  */
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/spi/spi.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #include <drm/drm_connector.h>
20*4882a593Smuzhiyun #include <drm/drm_modes.h>
21*4882a593Smuzhiyun #include <drm/drm_panel.h>
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun struct lb035q02_device {
24*4882a593Smuzhiyun 	struct drm_panel panel;
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun 	struct spi_device *spi;
27*4882a593Smuzhiyun 	struct gpio_desc *enable_gpio;
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #define to_lb035q02_device(p) container_of(p, struct lb035q02_device, panel)
31*4882a593Smuzhiyun 
lb035q02_write(struct lb035q02_device * lcd,u16 reg,u16 val)32*4882a593Smuzhiyun static int lb035q02_write(struct lb035q02_device *lcd, u16 reg, u16 val)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun 	struct spi_message msg;
35*4882a593Smuzhiyun 	struct spi_transfer index_xfer = {
36*4882a593Smuzhiyun 		.len		= 3,
37*4882a593Smuzhiyun 		.cs_change	= 1,
38*4882a593Smuzhiyun 	};
39*4882a593Smuzhiyun 	struct spi_transfer value_xfer = {
40*4882a593Smuzhiyun 		.len		= 3,
41*4882a593Smuzhiyun 	};
42*4882a593Smuzhiyun 	u8	buffer[16];
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun 	spi_message_init(&msg);
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 	/* register index */
47*4882a593Smuzhiyun 	buffer[0] = 0x70;
48*4882a593Smuzhiyun 	buffer[1] = 0x00;
49*4882a593Smuzhiyun 	buffer[2] = reg & 0x7f;
50*4882a593Smuzhiyun 	index_xfer.tx_buf = buffer;
51*4882a593Smuzhiyun 	spi_message_add_tail(&index_xfer, &msg);
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun 	/* register value */
54*4882a593Smuzhiyun 	buffer[4] = 0x72;
55*4882a593Smuzhiyun 	buffer[5] = val >> 8;
56*4882a593Smuzhiyun 	buffer[6] = val;
57*4882a593Smuzhiyun 	value_xfer.tx_buf = buffer + 4;
58*4882a593Smuzhiyun 	spi_message_add_tail(&value_xfer, &msg);
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun 	return spi_sync(lcd->spi, &msg);
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun 
lb035q02_init(struct lb035q02_device * lcd)63*4882a593Smuzhiyun static int lb035q02_init(struct lb035q02_device *lcd)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun 	/* Init sequence from page 28 of the lb035q02 spec. */
66*4882a593Smuzhiyun 	static const struct {
67*4882a593Smuzhiyun 		u16 index;
68*4882a593Smuzhiyun 		u16 value;
69*4882a593Smuzhiyun 	} init_data[] = {
70*4882a593Smuzhiyun 		{ 0x01, 0x6300 },
71*4882a593Smuzhiyun 		{ 0x02, 0x0200 },
72*4882a593Smuzhiyun 		{ 0x03, 0x0177 },
73*4882a593Smuzhiyun 		{ 0x04, 0x04c7 },
74*4882a593Smuzhiyun 		{ 0x05, 0xffc0 },
75*4882a593Smuzhiyun 		{ 0x06, 0xe806 },
76*4882a593Smuzhiyun 		{ 0x0a, 0x4008 },
77*4882a593Smuzhiyun 		{ 0x0b, 0x0000 },
78*4882a593Smuzhiyun 		{ 0x0d, 0x0030 },
79*4882a593Smuzhiyun 		{ 0x0e, 0x2800 },
80*4882a593Smuzhiyun 		{ 0x0f, 0x0000 },
81*4882a593Smuzhiyun 		{ 0x16, 0x9f80 },
82*4882a593Smuzhiyun 		{ 0x17, 0x0a0f },
83*4882a593Smuzhiyun 		{ 0x1e, 0x00c1 },
84*4882a593Smuzhiyun 		{ 0x30, 0x0300 },
85*4882a593Smuzhiyun 		{ 0x31, 0x0007 },
86*4882a593Smuzhiyun 		{ 0x32, 0x0000 },
87*4882a593Smuzhiyun 		{ 0x33, 0x0000 },
88*4882a593Smuzhiyun 		{ 0x34, 0x0707 },
89*4882a593Smuzhiyun 		{ 0x35, 0x0004 },
90*4882a593Smuzhiyun 		{ 0x36, 0x0302 },
91*4882a593Smuzhiyun 		{ 0x37, 0x0202 },
92*4882a593Smuzhiyun 		{ 0x3a, 0x0a0d },
93*4882a593Smuzhiyun 		{ 0x3b, 0x0806 },
94*4882a593Smuzhiyun 	};
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 	unsigned int i;
97*4882a593Smuzhiyun 	int ret;
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(init_data); ++i) {
100*4882a593Smuzhiyun 		ret = lb035q02_write(lcd, init_data[i].index,
101*4882a593Smuzhiyun 				     init_data[i].value);
102*4882a593Smuzhiyun 		if (ret < 0)
103*4882a593Smuzhiyun 			return ret;
104*4882a593Smuzhiyun 	}
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	return 0;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun 
lb035q02_disable(struct drm_panel * panel)109*4882a593Smuzhiyun static int lb035q02_disable(struct drm_panel *panel)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun 	struct lb035q02_device *lcd = to_lb035q02_device(panel);
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	gpiod_set_value_cansleep(lcd->enable_gpio, 0);
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	return 0;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun 
lb035q02_enable(struct drm_panel * panel)118*4882a593Smuzhiyun static int lb035q02_enable(struct drm_panel *panel)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun 	struct lb035q02_device *lcd = to_lb035q02_device(panel);
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	gpiod_set_value_cansleep(lcd->enable_gpio, 1);
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	return 0;
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun static const struct drm_display_mode lb035q02_mode = {
128*4882a593Smuzhiyun 	.clock = 6500,
129*4882a593Smuzhiyun 	.hdisplay = 320,
130*4882a593Smuzhiyun 	.hsync_start = 320 + 20,
131*4882a593Smuzhiyun 	.hsync_end = 320 + 20 + 2,
132*4882a593Smuzhiyun 	.htotal = 320 + 20 + 2 + 68,
133*4882a593Smuzhiyun 	.vdisplay = 240,
134*4882a593Smuzhiyun 	.vsync_start = 240 + 4,
135*4882a593Smuzhiyun 	.vsync_end = 240 + 4 + 2,
136*4882a593Smuzhiyun 	.vtotal = 240 + 4 + 2 + 18,
137*4882a593Smuzhiyun 	.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
138*4882a593Smuzhiyun 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
139*4882a593Smuzhiyun 	.width_mm = 70,
140*4882a593Smuzhiyun 	.height_mm = 53,
141*4882a593Smuzhiyun };
142*4882a593Smuzhiyun 
lb035q02_get_modes(struct drm_panel * panel,struct drm_connector * connector)143*4882a593Smuzhiyun static int lb035q02_get_modes(struct drm_panel *panel,
144*4882a593Smuzhiyun 			      struct drm_connector *connector)
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun 	struct drm_display_mode *mode;
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	mode = drm_mode_duplicate(connector->dev, &lb035q02_mode);
149*4882a593Smuzhiyun 	if (!mode)
150*4882a593Smuzhiyun 		return -ENOMEM;
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	drm_mode_set_name(mode);
153*4882a593Smuzhiyun 	drm_mode_probed_add(connector, mode);
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	connector->display_info.width_mm = lb035q02_mode.width_mm;
156*4882a593Smuzhiyun 	connector->display_info.height_mm = lb035q02_mode.height_mm;
157*4882a593Smuzhiyun 	/*
158*4882a593Smuzhiyun 	 * FIXME: According to the datasheet pixel data is sampled on the
159*4882a593Smuzhiyun 	 * rising edge of the clock, but the code running on the Gumstix Overo
160*4882a593Smuzhiyun 	 * Palo35 indicates sampling on the negative edge. This should be
161*4882a593Smuzhiyun 	 * tested on a real device.
162*4882a593Smuzhiyun 	 */
163*4882a593Smuzhiyun 	connector->display_info.bus_flags = DRM_BUS_FLAG_DE_HIGH
164*4882a593Smuzhiyun 					  | DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE
165*4882a593Smuzhiyun 					  | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE;
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 	return 1;
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun static const struct drm_panel_funcs lb035q02_funcs = {
171*4882a593Smuzhiyun 	.disable = lb035q02_disable,
172*4882a593Smuzhiyun 	.enable = lb035q02_enable,
173*4882a593Smuzhiyun 	.get_modes = lb035q02_get_modes,
174*4882a593Smuzhiyun };
175*4882a593Smuzhiyun 
lb035q02_probe(struct spi_device * spi)176*4882a593Smuzhiyun static int lb035q02_probe(struct spi_device *spi)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun 	struct lb035q02_device *lcd;
179*4882a593Smuzhiyun 	int ret;
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun 	lcd = devm_kzalloc(&spi->dev, sizeof(*lcd), GFP_KERNEL);
182*4882a593Smuzhiyun 	if (!lcd)
183*4882a593Smuzhiyun 		return -ENOMEM;
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	spi_set_drvdata(spi, lcd);
186*4882a593Smuzhiyun 	lcd->spi = spi;
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	lcd->enable_gpio = devm_gpiod_get(&spi->dev, "enable", GPIOD_OUT_LOW);
189*4882a593Smuzhiyun 	if (IS_ERR(lcd->enable_gpio)) {
190*4882a593Smuzhiyun 		dev_err(&spi->dev, "failed to parse enable gpio\n");
191*4882a593Smuzhiyun 		return PTR_ERR(lcd->enable_gpio);
192*4882a593Smuzhiyun 	}
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 	ret = lb035q02_init(lcd);
195*4882a593Smuzhiyun 	if (ret < 0)
196*4882a593Smuzhiyun 		return ret;
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	drm_panel_init(&lcd->panel, &lcd->spi->dev, &lb035q02_funcs,
199*4882a593Smuzhiyun 		       DRM_MODE_CONNECTOR_DPI);
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun 	drm_panel_add(&lcd->panel);
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	return 0;
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun 
lb035q02_remove(struct spi_device * spi)206*4882a593Smuzhiyun static int lb035q02_remove(struct spi_device *spi)
207*4882a593Smuzhiyun {
208*4882a593Smuzhiyun 	struct lb035q02_device *lcd = spi_get_drvdata(spi);
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 	drm_panel_remove(&lcd->panel);
211*4882a593Smuzhiyun 	drm_panel_disable(&lcd->panel);
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun 	return 0;
214*4882a593Smuzhiyun }
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun static const struct of_device_id lb035q02_of_match[] = {
217*4882a593Smuzhiyun 	{ .compatible = "lgphilips,lb035q02", },
218*4882a593Smuzhiyun 	{ /* sentinel */ },
219*4882a593Smuzhiyun };
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, lb035q02_of_match);
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun static const struct spi_device_id lb035q02_ids[] = {
224*4882a593Smuzhiyun 	{ "lb035q02", 0 },
225*4882a593Smuzhiyun 	{ /* sentinel */ }
226*4882a593Smuzhiyun };
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, lb035q02_ids);
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun static struct spi_driver lb035q02_driver = {
231*4882a593Smuzhiyun 	.probe		= lb035q02_probe,
232*4882a593Smuzhiyun 	.remove		= lb035q02_remove,
233*4882a593Smuzhiyun 	.id_table	= lb035q02_ids,
234*4882a593Smuzhiyun 	.driver		= {
235*4882a593Smuzhiyun 		.name	= "panel-lg-lb035q02",
236*4882a593Smuzhiyun 		.of_match_table = lb035q02_of_match,
237*4882a593Smuzhiyun 	},
238*4882a593Smuzhiyun };
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun module_spi_driver(lb035q02_driver);
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@ti.com>");
243*4882a593Smuzhiyun MODULE_DESCRIPTION("LG.Philips LB035Q02 LCD Panel driver");
244*4882a593Smuzhiyun MODULE_LICENSE("GPL");
245