xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/omapdrm/omap_fb.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
4*4882a593Smuzhiyun  * Author: Rob Clark <rob@ti.com>
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/dma-mapping.h>
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <drm/drm_modeset_helper.h>
10*4882a593Smuzhiyun #include <drm/drm_fourcc.h>
11*4882a593Smuzhiyun #include <drm/drm_gem_framebuffer_helper.h>
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include "omap_dmm_tiler.h"
14*4882a593Smuzhiyun #include "omap_drv.h"
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun /*
17*4882a593Smuzhiyun  * framebuffer funcs
18*4882a593Smuzhiyun  */
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun static const u32 formats[] = {
21*4882a593Smuzhiyun 	/* 16bpp [A]RGB: */
22*4882a593Smuzhiyun 	DRM_FORMAT_RGB565, /* RGB16-565 */
23*4882a593Smuzhiyun 	DRM_FORMAT_RGBX4444, /* RGB12x-4444 */
24*4882a593Smuzhiyun 	DRM_FORMAT_XRGB4444, /* xRGB12-4444 */
25*4882a593Smuzhiyun 	DRM_FORMAT_RGBA4444, /* RGBA12-4444 */
26*4882a593Smuzhiyun 	DRM_FORMAT_ARGB4444, /* ARGB16-4444 */
27*4882a593Smuzhiyun 	DRM_FORMAT_XRGB1555, /* xRGB15-1555 */
28*4882a593Smuzhiyun 	DRM_FORMAT_ARGB1555, /* ARGB16-1555 */
29*4882a593Smuzhiyun 	/* 24bpp RGB: */
30*4882a593Smuzhiyun 	DRM_FORMAT_RGB888,   /* RGB24-888 */
31*4882a593Smuzhiyun 	/* 32bpp [A]RGB: */
32*4882a593Smuzhiyun 	DRM_FORMAT_RGBX8888, /* RGBx24-8888 */
33*4882a593Smuzhiyun 	DRM_FORMAT_XRGB8888, /* xRGB24-8888 */
34*4882a593Smuzhiyun 	DRM_FORMAT_RGBA8888, /* RGBA32-8888 */
35*4882a593Smuzhiyun 	DRM_FORMAT_ARGB8888, /* ARGB32-8888 */
36*4882a593Smuzhiyun 	/* YUV: */
37*4882a593Smuzhiyun 	DRM_FORMAT_NV12,
38*4882a593Smuzhiyun 	DRM_FORMAT_YUYV,
39*4882a593Smuzhiyun 	DRM_FORMAT_UYVY,
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun /* per-plane info for the fb: */
43*4882a593Smuzhiyun struct plane {
44*4882a593Smuzhiyun 	dma_addr_t dma_addr;
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun #define to_omap_framebuffer(x) container_of(x, struct omap_framebuffer, base)
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun struct omap_framebuffer {
50*4882a593Smuzhiyun 	struct drm_framebuffer base;
51*4882a593Smuzhiyun 	int pin_count;
52*4882a593Smuzhiyun 	const struct drm_format_info *format;
53*4882a593Smuzhiyun 	struct plane planes[2];
54*4882a593Smuzhiyun 	/* lock for pinning (pin_count and planes.dma_addr) */
55*4882a593Smuzhiyun 	struct mutex lock;
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun 
omap_framebuffer_dirty(struct drm_framebuffer * fb,struct drm_file * file_priv,unsigned flags,unsigned color,struct drm_clip_rect * clips,unsigned num_clips)58*4882a593Smuzhiyun static int omap_framebuffer_dirty(struct drm_framebuffer *fb,
59*4882a593Smuzhiyun 				  struct drm_file *file_priv,
60*4882a593Smuzhiyun 				  unsigned flags, unsigned color,
61*4882a593Smuzhiyun 				  struct drm_clip_rect *clips,
62*4882a593Smuzhiyun 				  unsigned num_clips)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun 	struct drm_crtc *crtc;
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 	drm_modeset_lock_all(fb->dev);
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun 	drm_for_each_crtc(crtc, fb->dev)
69*4882a593Smuzhiyun 		omap_crtc_flush(crtc);
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 	drm_modeset_unlock_all(fb->dev);
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	return 0;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun static const struct drm_framebuffer_funcs omap_framebuffer_funcs = {
77*4882a593Smuzhiyun 	.create_handle = drm_gem_fb_create_handle,
78*4882a593Smuzhiyun 	.dirty = omap_framebuffer_dirty,
79*4882a593Smuzhiyun 	.destroy = drm_gem_fb_destroy,
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun 
get_linear_addr(struct drm_framebuffer * fb,const struct drm_format_info * format,int n,int x,int y)82*4882a593Smuzhiyun static u32 get_linear_addr(struct drm_framebuffer *fb,
83*4882a593Smuzhiyun 		const struct drm_format_info *format, int n, int x, int y)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun 	struct omap_framebuffer *omap_fb = to_omap_framebuffer(fb);
86*4882a593Smuzhiyun 	struct plane *plane = &omap_fb->planes[n];
87*4882a593Smuzhiyun 	u32 offset;
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 	offset = fb->offsets[n]
90*4882a593Smuzhiyun 	       + (x * format->cpp[n] / (n == 0 ? 1 : format->hsub))
91*4882a593Smuzhiyun 	       + (y * fb->pitches[n] / (n == 0 ? 1 : format->vsub));
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 	return plane->dma_addr + offset;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun 
omap_framebuffer_supports_rotation(struct drm_framebuffer * fb)96*4882a593Smuzhiyun bool omap_framebuffer_supports_rotation(struct drm_framebuffer *fb)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun 	return omap_gem_flags(fb->obj[0]) & OMAP_BO_TILED_MASK;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun /* Note: DRM rotates counter-clockwise, TILER & DSS rotates clockwise */
drm_rotation_to_tiler(unsigned int drm_rot)102*4882a593Smuzhiyun static u32 drm_rotation_to_tiler(unsigned int drm_rot)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun 	u32 orient;
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	switch (drm_rot & DRM_MODE_ROTATE_MASK) {
107*4882a593Smuzhiyun 	default:
108*4882a593Smuzhiyun 	case DRM_MODE_ROTATE_0:
109*4882a593Smuzhiyun 		orient = 0;
110*4882a593Smuzhiyun 		break;
111*4882a593Smuzhiyun 	case DRM_MODE_ROTATE_90:
112*4882a593Smuzhiyun 		orient = MASK_XY_FLIP | MASK_X_INVERT;
113*4882a593Smuzhiyun 		break;
114*4882a593Smuzhiyun 	case DRM_MODE_ROTATE_180:
115*4882a593Smuzhiyun 		orient = MASK_X_INVERT | MASK_Y_INVERT;
116*4882a593Smuzhiyun 		break;
117*4882a593Smuzhiyun 	case DRM_MODE_ROTATE_270:
118*4882a593Smuzhiyun 		orient = MASK_XY_FLIP | MASK_Y_INVERT;
119*4882a593Smuzhiyun 		break;
120*4882a593Smuzhiyun 	}
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	if (drm_rot & DRM_MODE_REFLECT_X)
123*4882a593Smuzhiyun 		orient ^= MASK_X_INVERT;
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	if (drm_rot & DRM_MODE_REFLECT_Y)
126*4882a593Smuzhiyun 		orient ^= MASK_Y_INVERT;
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	return orient;
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun /* update ovl info for scanout, handles cases of multi-planar fb's, etc.
132*4882a593Smuzhiyun  */
omap_framebuffer_update_scanout(struct drm_framebuffer * fb,struct drm_plane_state * state,struct omap_overlay_info * info)133*4882a593Smuzhiyun void omap_framebuffer_update_scanout(struct drm_framebuffer *fb,
134*4882a593Smuzhiyun 		struct drm_plane_state *state, struct omap_overlay_info *info)
135*4882a593Smuzhiyun {
136*4882a593Smuzhiyun 	struct omap_framebuffer *omap_fb = to_omap_framebuffer(fb);
137*4882a593Smuzhiyun 	const struct drm_format_info *format = omap_fb->format;
138*4882a593Smuzhiyun 	u32 x, y, orient = 0;
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	info->fourcc = fb->format->format;
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	info->pos_x      = state->crtc_x;
143*4882a593Smuzhiyun 	info->pos_y      = state->crtc_y;
144*4882a593Smuzhiyun 	info->out_width  = state->crtc_w;
145*4882a593Smuzhiyun 	info->out_height = state->crtc_h;
146*4882a593Smuzhiyun 	info->width      = state->src_w >> 16;
147*4882a593Smuzhiyun 	info->height     = state->src_h >> 16;
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	/* DSS driver wants the w & h in rotated orientation */
150*4882a593Smuzhiyun 	if (drm_rotation_90_or_270(state->rotation))
151*4882a593Smuzhiyun 		swap(info->width, info->height);
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun 	x = state->src_x >> 16;
154*4882a593Smuzhiyun 	y = state->src_y >> 16;
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 	if (omap_gem_flags(fb->obj[0]) & OMAP_BO_TILED_MASK) {
157*4882a593Smuzhiyun 		u32 w = state->src_w >> 16;
158*4882a593Smuzhiyun 		u32 h = state->src_h >> 16;
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 		orient = drm_rotation_to_tiler(state->rotation);
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 		/*
163*4882a593Smuzhiyun 		 * omap_gem_rotated_paddr() wants the x & y in tiler units.
164*4882a593Smuzhiyun 		 * Usually tiler unit size is the same as the pixel size, except
165*4882a593Smuzhiyun 		 * for YUV422 formats, for which the tiler unit size is 32 bits
166*4882a593Smuzhiyun 		 * and pixel size is 16 bits.
167*4882a593Smuzhiyun 		 */
168*4882a593Smuzhiyun 		if (fb->format->format == DRM_FORMAT_UYVY ||
169*4882a593Smuzhiyun 				fb->format->format == DRM_FORMAT_YUYV) {
170*4882a593Smuzhiyun 			x /= 2;
171*4882a593Smuzhiyun 			w /= 2;
172*4882a593Smuzhiyun 		}
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 		/* adjust x,y offset for invert: */
175*4882a593Smuzhiyun 		if (orient & MASK_Y_INVERT)
176*4882a593Smuzhiyun 			y += h - 1;
177*4882a593Smuzhiyun 		if (orient & MASK_X_INVERT)
178*4882a593Smuzhiyun 			x += w - 1;
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 		/* Note: x and y are in TILER units, not pixels */
181*4882a593Smuzhiyun 		omap_gem_rotated_dma_addr(fb->obj[0], orient, x, y,
182*4882a593Smuzhiyun 					  &info->paddr);
183*4882a593Smuzhiyun 		info->rotation_type = OMAP_DSS_ROT_TILER;
184*4882a593Smuzhiyun 		info->rotation = state->rotation ?: DRM_MODE_ROTATE_0;
185*4882a593Smuzhiyun 		/* Note: stride in TILER units, not pixels */
186*4882a593Smuzhiyun 		info->screen_width  = omap_gem_tiled_stride(fb->obj[0], orient);
187*4882a593Smuzhiyun 	} else {
188*4882a593Smuzhiyun 		switch (state->rotation & DRM_MODE_ROTATE_MASK) {
189*4882a593Smuzhiyun 		case 0:
190*4882a593Smuzhiyun 		case DRM_MODE_ROTATE_0:
191*4882a593Smuzhiyun 			/* OK */
192*4882a593Smuzhiyun 			break;
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 		default:
195*4882a593Smuzhiyun 			dev_warn(fb->dev->dev,
196*4882a593Smuzhiyun 				"rotation '%d' ignored for non-tiled fb\n",
197*4882a593Smuzhiyun 				state->rotation);
198*4882a593Smuzhiyun 			break;
199*4882a593Smuzhiyun 		}
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun 		info->paddr         = get_linear_addr(fb, format, 0, x, y);
202*4882a593Smuzhiyun 		info->rotation_type = OMAP_DSS_ROT_NONE;
203*4882a593Smuzhiyun 		info->rotation      = DRM_MODE_ROTATE_0;
204*4882a593Smuzhiyun 		info->screen_width  = fb->pitches[0];
205*4882a593Smuzhiyun 	}
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	/* convert to pixels: */
208*4882a593Smuzhiyun 	info->screen_width /= format->cpp[0];
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 	if (fb->format->format == DRM_FORMAT_NV12) {
211*4882a593Smuzhiyun 		if (info->rotation_type == OMAP_DSS_ROT_TILER) {
212*4882a593Smuzhiyun 			WARN_ON(!(omap_gem_flags(fb->obj[1]) & OMAP_BO_TILED_MASK));
213*4882a593Smuzhiyun 			omap_gem_rotated_dma_addr(fb->obj[1], orient, x/2, y/2,
214*4882a593Smuzhiyun 						  &info->p_uv_addr);
215*4882a593Smuzhiyun 		} else {
216*4882a593Smuzhiyun 			info->p_uv_addr = get_linear_addr(fb, format, 1, x, y);
217*4882a593Smuzhiyun 		}
218*4882a593Smuzhiyun 	} else {
219*4882a593Smuzhiyun 		info->p_uv_addr = 0;
220*4882a593Smuzhiyun 	}
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun /* pin, prepare for scanout: */
omap_framebuffer_pin(struct drm_framebuffer * fb)224*4882a593Smuzhiyun int omap_framebuffer_pin(struct drm_framebuffer *fb)
225*4882a593Smuzhiyun {
226*4882a593Smuzhiyun 	struct omap_framebuffer *omap_fb = to_omap_framebuffer(fb);
227*4882a593Smuzhiyun 	int ret, i, n = fb->format->num_planes;
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 	mutex_lock(&omap_fb->lock);
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun 	if (omap_fb->pin_count > 0) {
232*4882a593Smuzhiyun 		omap_fb->pin_count++;
233*4882a593Smuzhiyun 		mutex_unlock(&omap_fb->lock);
234*4882a593Smuzhiyun 		return 0;
235*4882a593Smuzhiyun 	}
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun 	for (i = 0; i < n; i++) {
238*4882a593Smuzhiyun 		struct plane *plane = &omap_fb->planes[i];
239*4882a593Smuzhiyun 		ret = omap_gem_pin(fb->obj[i], &plane->dma_addr);
240*4882a593Smuzhiyun 		if (ret)
241*4882a593Smuzhiyun 			goto fail;
242*4882a593Smuzhiyun 		omap_gem_dma_sync_buffer(fb->obj[i], DMA_TO_DEVICE);
243*4882a593Smuzhiyun 	}
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	omap_fb->pin_count++;
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun 	mutex_unlock(&omap_fb->lock);
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun 	return 0;
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun fail:
252*4882a593Smuzhiyun 	for (i--; i >= 0; i--) {
253*4882a593Smuzhiyun 		struct plane *plane = &omap_fb->planes[i];
254*4882a593Smuzhiyun 		omap_gem_unpin(fb->obj[i]);
255*4882a593Smuzhiyun 		plane->dma_addr = 0;
256*4882a593Smuzhiyun 	}
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun 	mutex_unlock(&omap_fb->lock);
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun 	return ret;
261*4882a593Smuzhiyun }
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun /* unpin, no longer being scanned out: */
omap_framebuffer_unpin(struct drm_framebuffer * fb)264*4882a593Smuzhiyun void omap_framebuffer_unpin(struct drm_framebuffer *fb)
265*4882a593Smuzhiyun {
266*4882a593Smuzhiyun 	struct omap_framebuffer *omap_fb = to_omap_framebuffer(fb);
267*4882a593Smuzhiyun 	int i, n = fb->format->num_planes;
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 	mutex_lock(&omap_fb->lock);
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	omap_fb->pin_count--;
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	if (omap_fb->pin_count > 0) {
274*4882a593Smuzhiyun 		mutex_unlock(&omap_fb->lock);
275*4882a593Smuzhiyun 		return;
276*4882a593Smuzhiyun 	}
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun 	for (i = 0; i < n; i++) {
279*4882a593Smuzhiyun 		struct plane *plane = &omap_fb->planes[i];
280*4882a593Smuzhiyun 		omap_gem_unpin(fb->obj[i]);
281*4882a593Smuzhiyun 		plane->dma_addr = 0;
282*4882a593Smuzhiyun 	}
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun 	mutex_unlock(&omap_fb->lock);
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun #ifdef CONFIG_DEBUG_FS
omap_framebuffer_describe(struct drm_framebuffer * fb,struct seq_file * m)288*4882a593Smuzhiyun void omap_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun 	int i, n = fb->format->num_planes;
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun 	seq_printf(m, "fb: %dx%d@%4.4s\n", fb->width, fb->height,
293*4882a593Smuzhiyun 			(char *)&fb->format->format);
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun 	for (i = 0; i < n; i++) {
296*4882a593Smuzhiyun 		seq_printf(m, "   %d: offset=%d pitch=%d, obj: ",
297*4882a593Smuzhiyun 				i, fb->offsets[n], fb->pitches[i]);
298*4882a593Smuzhiyun 		omap_gem_describe(fb->obj[i], m);
299*4882a593Smuzhiyun 	}
300*4882a593Smuzhiyun }
301*4882a593Smuzhiyun #endif
302*4882a593Smuzhiyun 
omap_framebuffer_create(struct drm_device * dev,struct drm_file * file,const struct drm_mode_fb_cmd2 * mode_cmd)303*4882a593Smuzhiyun struct drm_framebuffer *omap_framebuffer_create(struct drm_device *dev,
304*4882a593Smuzhiyun 		struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd)
305*4882a593Smuzhiyun {
306*4882a593Smuzhiyun 	const struct drm_format_info *info = drm_get_format_info(dev,
307*4882a593Smuzhiyun 								 mode_cmd);
308*4882a593Smuzhiyun 	unsigned int num_planes = info->num_planes;
309*4882a593Smuzhiyun 	struct drm_gem_object *bos[4];
310*4882a593Smuzhiyun 	struct drm_framebuffer *fb;
311*4882a593Smuzhiyun 	int i;
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun 	for (i = 0; i < num_planes; i++) {
314*4882a593Smuzhiyun 		bos[i] = drm_gem_object_lookup(file, mode_cmd->handles[i]);
315*4882a593Smuzhiyun 		if (!bos[i]) {
316*4882a593Smuzhiyun 			fb = ERR_PTR(-ENOENT);
317*4882a593Smuzhiyun 			goto error;
318*4882a593Smuzhiyun 		}
319*4882a593Smuzhiyun 	}
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun 	fb = omap_framebuffer_init(dev, mode_cmd, bos);
322*4882a593Smuzhiyun 	if (IS_ERR(fb))
323*4882a593Smuzhiyun 		goto error;
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun 	return fb;
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun error:
328*4882a593Smuzhiyun 	while (--i >= 0)
329*4882a593Smuzhiyun 		drm_gem_object_put(bos[i]);
330*4882a593Smuzhiyun 
331*4882a593Smuzhiyun 	return fb;
332*4882a593Smuzhiyun }
333*4882a593Smuzhiyun 
omap_framebuffer_init(struct drm_device * dev,const struct drm_mode_fb_cmd2 * mode_cmd,struct drm_gem_object ** bos)334*4882a593Smuzhiyun struct drm_framebuffer *omap_framebuffer_init(struct drm_device *dev,
335*4882a593Smuzhiyun 		const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos)
336*4882a593Smuzhiyun {
337*4882a593Smuzhiyun 	const struct drm_format_info *format = NULL;
338*4882a593Smuzhiyun 	struct omap_framebuffer *omap_fb = NULL;
339*4882a593Smuzhiyun 	struct drm_framebuffer *fb = NULL;
340*4882a593Smuzhiyun 	unsigned int pitch = mode_cmd->pitches[0];
341*4882a593Smuzhiyun 	int ret, i;
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun 	DBG("create framebuffer: dev=%p, mode_cmd=%p (%dx%d@%4.4s)",
344*4882a593Smuzhiyun 			dev, mode_cmd, mode_cmd->width, mode_cmd->height,
345*4882a593Smuzhiyun 			(char *)&mode_cmd->pixel_format);
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun 	format = drm_get_format_info(dev, mode_cmd);
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(formats); i++) {
350*4882a593Smuzhiyun 		if (formats[i] == mode_cmd->pixel_format)
351*4882a593Smuzhiyun 			break;
352*4882a593Smuzhiyun 	}
353*4882a593Smuzhiyun 
354*4882a593Smuzhiyun 	if (!format || i == ARRAY_SIZE(formats)) {
355*4882a593Smuzhiyun 		dev_dbg(dev->dev, "unsupported pixel format: %4.4s\n",
356*4882a593Smuzhiyun 			(char *)&mode_cmd->pixel_format);
357*4882a593Smuzhiyun 		ret = -EINVAL;
358*4882a593Smuzhiyun 		goto fail;
359*4882a593Smuzhiyun 	}
360*4882a593Smuzhiyun 
361*4882a593Smuzhiyun 	omap_fb = kzalloc(sizeof(*omap_fb), GFP_KERNEL);
362*4882a593Smuzhiyun 	if (!omap_fb) {
363*4882a593Smuzhiyun 		ret = -ENOMEM;
364*4882a593Smuzhiyun 		goto fail;
365*4882a593Smuzhiyun 	}
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun 	fb = &omap_fb->base;
368*4882a593Smuzhiyun 	omap_fb->format = format;
369*4882a593Smuzhiyun 	mutex_init(&omap_fb->lock);
370*4882a593Smuzhiyun 
371*4882a593Smuzhiyun 	/*
372*4882a593Smuzhiyun 	 * The code below assumes that no format use more than two planes, and
373*4882a593Smuzhiyun 	 * that the two planes of multiplane formats need the same number of
374*4882a593Smuzhiyun 	 * bytes per pixel.
375*4882a593Smuzhiyun 	 */
376*4882a593Smuzhiyun 	if (format->num_planes == 2 && pitch != mode_cmd->pitches[1]) {
377*4882a593Smuzhiyun 		dev_dbg(dev->dev, "pitches differ between planes 0 and 1\n");
378*4882a593Smuzhiyun 		ret = -EINVAL;
379*4882a593Smuzhiyun 		goto fail;
380*4882a593Smuzhiyun 	}
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun 	if (pitch % format->cpp[0]) {
383*4882a593Smuzhiyun 		dev_dbg(dev->dev,
384*4882a593Smuzhiyun 			"buffer pitch (%u bytes) is not a multiple of pixel size (%u bytes)\n",
385*4882a593Smuzhiyun 			pitch, format->cpp[0]);
386*4882a593Smuzhiyun 		ret = -EINVAL;
387*4882a593Smuzhiyun 		goto fail;
388*4882a593Smuzhiyun 	}
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun 	for (i = 0; i < format->num_planes; i++) {
391*4882a593Smuzhiyun 		struct plane *plane = &omap_fb->planes[i];
392*4882a593Smuzhiyun 		unsigned int vsub = i == 0 ? 1 : format->vsub;
393*4882a593Smuzhiyun 		unsigned int size;
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun 		size = pitch * mode_cmd->height / vsub;
396*4882a593Smuzhiyun 
397*4882a593Smuzhiyun 		if (size > omap_gem_mmap_size(bos[i]) - mode_cmd->offsets[i]) {
398*4882a593Smuzhiyun 			dev_dbg(dev->dev,
399*4882a593Smuzhiyun 				"provided buffer object is too small! %zu < %d\n",
400*4882a593Smuzhiyun 				bos[i]->size - mode_cmd->offsets[i], size);
401*4882a593Smuzhiyun 			ret = -EINVAL;
402*4882a593Smuzhiyun 			goto fail;
403*4882a593Smuzhiyun 		}
404*4882a593Smuzhiyun 
405*4882a593Smuzhiyun 		fb->obj[i]    = bos[i];
406*4882a593Smuzhiyun 		plane->dma_addr  = 0;
407*4882a593Smuzhiyun 	}
408*4882a593Smuzhiyun 
409*4882a593Smuzhiyun 	drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd);
410*4882a593Smuzhiyun 
411*4882a593Smuzhiyun 	ret = drm_framebuffer_init(dev, fb, &omap_framebuffer_funcs);
412*4882a593Smuzhiyun 	if (ret) {
413*4882a593Smuzhiyun 		dev_err(dev->dev, "framebuffer init failed: %d\n", ret);
414*4882a593Smuzhiyun 		goto fail;
415*4882a593Smuzhiyun 	}
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun 	DBG("create: FB ID: %d (%p)", fb->base.id, fb);
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun 	return fb;
420*4882a593Smuzhiyun 
421*4882a593Smuzhiyun fail:
422*4882a593Smuzhiyun 	kfree(omap_fb);
423*4882a593Smuzhiyun 
424*4882a593Smuzhiyun 	return ERR_PTR(ret);
425*4882a593Smuzhiyun }
426