1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyunconfig OMAP2_DSS_INIT 3*4882a593Smuzhiyun bool 4*4882a593Smuzhiyun 5*4882a593Smuzhiyunconfig OMAP_DSS_BASE 6*4882a593Smuzhiyun tristate 7*4882a593Smuzhiyun 8*4882a593Smuzhiyunmenuconfig OMAP2_DSS 9*4882a593Smuzhiyun tristate "OMAP2+ Display Subsystem support" 10*4882a593Smuzhiyun select OMAP_DSS_BASE 11*4882a593Smuzhiyun select VIDEOMODE_HELPERS 12*4882a593Smuzhiyun select OMAP2_DSS_INIT 13*4882a593Smuzhiyun select HDMI 14*4882a593Smuzhiyun help 15*4882a593Smuzhiyun OMAP2+ Display Subsystem support. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyunif OMAP2_DSS 18*4882a593Smuzhiyun 19*4882a593Smuzhiyunconfig OMAP2_DSS_DEBUG 20*4882a593Smuzhiyun bool "Debug support" 21*4882a593Smuzhiyun default n 22*4882a593Smuzhiyun help 23*4882a593Smuzhiyun This enables printing of debug messages. Alternatively, debug messages 24*4882a593Smuzhiyun can also be enabled by setting CONFIG_DYNAMIC_DEBUG and then setting 25*4882a593Smuzhiyun appropriate flags in <debugfs>/dynamic_debug/control. 26*4882a593Smuzhiyun 27*4882a593Smuzhiyunconfig OMAP2_DSS_DEBUGFS 28*4882a593Smuzhiyun bool "Debugfs filesystem support" 29*4882a593Smuzhiyun depends on DEBUG_FS 30*4882a593Smuzhiyun default n 31*4882a593Smuzhiyun help 32*4882a593Smuzhiyun This enables debugfs for OMAPDSS at <debugfs>/omapdss. This enables 33*4882a593Smuzhiyun querying about clock configuration and register configuration of dss, 34*4882a593Smuzhiyun dispc, dsi, hdmi and rfbi. 35*4882a593Smuzhiyun 36*4882a593Smuzhiyunconfig OMAP2_DSS_COLLECT_IRQ_STATS 37*4882a593Smuzhiyun bool "Collect DSS IRQ statistics" 38*4882a593Smuzhiyun depends on OMAP2_DSS_DEBUGFS 39*4882a593Smuzhiyun default n 40*4882a593Smuzhiyun help 41*4882a593Smuzhiyun Collect DSS IRQ statistics, printable via debugfs. 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun The statistics can be found from 44*4882a593Smuzhiyun <debugfs>/omapdss/dispc_irq for DISPC interrupts, and 45*4882a593Smuzhiyun <debugfs>/omapdss/dsi_irq for DSI interrupts. 46*4882a593Smuzhiyun 47*4882a593Smuzhiyunconfig OMAP2_DSS_DPI 48*4882a593Smuzhiyun bool "DPI support" 49*4882a593Smuzhiyun default y 50*4882a593Smuzhiyun help 51*4882a593Smuzhiyun DPI Interface. This is the Parallel Display Interface. 52*4882a593Smuzhiyun 53*4882a593Smuzhiyunconfig OMAP2_DSS_VENC 54*4882a593Smuzhiyun bool "VENC support" 55*4882a593Smuzhiyun default y 56*4882a593Smuzhiyun help 57*4882a593Smuzhiyun OMAP Video Encoder support for S-Video and composite TV-out. 58*4882a593Smuzhiyun 59*4882a593Smuzhiyunconfig OMAP2_DSS_HDMI_COMMON 60*4882a593Smuzhiyun bool 61*4882a593Smuzhiyun 62*4882a593Smuzhiyunconfig OMAP4_DSS_HDMI 63*4882a593Smuzhiyun bool "HDMI support for OMAP4" 64*4882a593Smuzhiyun default y 65*4882a593Smuzhiyun select OMAP2_DSS_HDMI_COMMON 66*4882a593Smuzhiyun help 67*4882a593Smuzhiyun HDMI support for OMAP4 based SoCs. 68*4882a593Smuzhiyun 69*4882a593Smuzhiyunconfig OMAP4_DSS_HDMI_CEC 70*4882a593Smuzhiyun bool "Enable HDMI CEC support for OMAP4" 71*4882a593Smuzhiyun depends on OMAP4_DSS_HDMI 72*4882a593Smuzhiyun select CEC_CORE 73*4882a593Smuzhiyun default y 74*4882a593Smuzhiyun help 75*4882a593Smuzhiyun When selected the HDMI transmitter will support the CEC feature. 76*4882a593Smuzhiyun 77*4882a593Smuzhiyunconfig OMAP5_DSS_HDMI 78*4882a593Smuzhiyun bool "HDMI support for OMAP5" 79*4882a593Smuzhiyun default n 80*4882a593Smuzhiyun select OMAP2_DSS_HDMI_COMMON 81*4882a593Smuzhiyun help 82*4882a593Smuzhiyun HDMI Interface for OMAP5 and similar cores. This adds the High 83*4882a593Smuzhiyun Definition Multimedia Interface. See http://www.hdmi.org/ for HDMI 84*4882a593Smuzhiyun specification. 85*4882a593Smuzhiyun 86*4882a593Smuzhiyunconfig OMAP2_DSS_SDI 87*4882a593Smuzhiyun bool "SDI support" 88*4882a593Smuzhiyun default n 89*4882a593Smuzhiyun help 90*4882a593Smuzhiyun SDI (Serial Display Interface) support. 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun SDI is a high speed one-way display serial bus between the host 93*4882a593Smuzhiyun processor and a display. 94*4882a593Smuzhiyun 95*4882a593Smuzhiyunconfig OMAP2_DSS_DSI 96*4882a593Smuzhiyun bool "DSI support" 97*4882a593Smuzhiyun default n 98*4882a593Smuzhiyun help 99*4882a593Smuzhiyun MIPI DSI (Display Serial Interface) support. 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun DSI is a high speed half-duplex serial interface between the host 102*4882a593Smuzhiyun processor and a peripheral, such as a display or a framebuffer chip. 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun See http://www.mipi.org/ for DSI specifications. 105*4882a593Smuzhiyun 106*4882a593Smuzhiyunconfig OMAP2_DSS_MIN_FCK_PER_PCK 107*4882a593Smuzhiyun int "Minimum FCK/PCK ratio (for scaling)" 108*4882a593Smuzhiyun range 0 32 109*4882a593Smuzhiyun default 0 110*4882a593Smuzhiyun help 111*4882a593Smuzhiyun This can be used to adjust the minimum FCK/PCK ratio. 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun With this you can make sure that DISPC FCK is at least 114*4882a593Smuzhiyun n x PCK. Video plane scaling requires higher FCK than 115*4882a593Smuzhiyun normally. 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun If this is set to 0, there's no extra constraint on the 118*4882a593Smuzhiyun DISPC FCK. However, the FCK will at minimum be 119*4882a593Smuzhiyun 2xPCK (if active matrix) or 3xPCK (if passive matrix). 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun Max FCK is 173MHz, so this doesn't work if your PCK 122*4882a593Smuzhiyun is very high. 123*4882a593Smuzhiyun 124*4882a593Smuzhiyunconfig OMAP2_DSS_SLEEP_AFTER_VENC_RESET 125*4882a593Smuzhiyun bool "Sleep 20ms after VENC reset" 126*4882a593Smuzhiyun default y 127*4882a593Smuzhiyun help 128*4882a593Smuzhiyun There is a 20ms sleep after VENC reset which seemed to fix the 129*4882a593Smuzhiyun reset. The reason for the bug is unclear, and it's also unclear 130*4882a593Smuzhiyun on what platforms this happens. 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun This option enables the sleep, and is enabled by default. You can 133*4882a593Smuzhiyun disable the sleep if it doesn't cause problems on your platform. 134*4882a593Smuzhiyun 135*4882a593Smuzhiyunendif 136