xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvc0_fence.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright 2012 Red Hat Inc.
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Permission is hereby granted, free of charge, to any person obtaining a
5*4882a593Smuzhiyun  * copy of this software and associated documentation files (the "Software"),
6*4882a593Smuzhiyun  * to deal in the Software without restriction, including without limitation
7*4882a593Smuzhiyun  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*4882a593Smuzhiyun  * and/or sell copies of the Software, and to permit persons to whom the
9*4882a593Smuzhiyun  * Software is furnished to do so, subject to the following conditions:
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * The above copyright notice and this permission notice shall be included in
12*4882a593Smuzhiyun  * all copies or substantial portions of the Software.
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*4882a593Smuzhiyun  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17*4882a593Smuzhiyun  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*4882a593Smuzhiyun  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*4882a593Smuzhiyun  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*4882a593Smuzhiyun  * OTHER DEALINGS IN THE SOFTWARE.
21*4882a593Smuzhiyun  *
22*4882a593Smuzhiyun  * Authors: Ben Skeggs
23*4882a593Smuzhiyun  */
24*4882a593Smuzhiyun #include "nouveau_drv.h"
25*4882a593Smuzhiyun #include "nouveau_dma.h"
26*4882a593Smuzhiyun #include "nouveau_fence.h"
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #include "nv50_display.h"
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #include <nvif/push906f.h>
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #include <nvhw/class/cl906f.h>
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun static int
nvc0_fence_emit32(struct nouveau_channel * chan,u64 virtual,u32 sequence)35*4882a593Smuzhiyun nvc0_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun 	struct nvif_push *push = chan->chan.push;
38*4882a593Smuzhiyun 	int ret = PUSH_WAIT(push, 6);
39*4882a593Smuzhiyun 	if (ret == 0) {
40*4882a593Smuzhiyun 		PUSH_MTHD(push, NV906F, SEMAPHOREA,
41*4882a593Smuzhiyun 			  NVVAL(NV906F, SEMAPHOREA, OFFSET_UPPER, upper_32_bits(virtual)),
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun 					SEMAPHOREB, lower_32_bits(virtual),
44*4882a593Smuzhiyun 					SEMAPHOREC, sequence,
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 					SEMAPHORED,
47*4882a593Smuzhiyun 			  NVDEF(NV906F, SEMAPHORED, OPERATION, RELEASE) |
48*4882a593Smuzhiyun 			  NVDEF(NV906F, SEMAPHORED, RELEASE_WFI, EN) |
49*4882a593Smuzhiyun 			  NVDEF(NV906F, SEMAPHORED, RELEASE_SIZE, 16BYTE),
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun 					NON_STALL_INTERRUPT, 0);
52*4882a593Smuzhiyun 		PUSH_KICK(push);
53*4882a593Smuzhiyun 	}
54*4882a593Smuzhiyun 	return ret;
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun static int
nvc0_fence_sync32(struct nouveau_channel * chan,u64 virtual,u32 sequence)58*4882a593Smuzhiyun nvc0_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun 	struct nvif_push *push = chan->chan.push;
61*4882a593Smuzhiyun 	int ret = PUSH_WAIT(push, 5);
62*4882a593Smuzhiyun 	if (ret == 0) {
63*4882a593Smuzhiyun 		PUSH_MTHD(push, NV906F, SEMAPHOREA,
64*4882a593Smuzhiyun 			  NVVAL(NV906F, SEMAPHOREA, OFFSET_UPPER, upper_32_bits(virtual)),
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 					SEMAPHOREB, lower_32_bits(virtual),
67*4882a593Smuzhiyun 					SEMAPHOREC, sequence,
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 					SEMAPHORED,
70*4882a593Smuzhiyun 			  NVDEF(NV906F, SEMAPHORED, OPERATION, ACQ_GEQ) |
71*4882a593Smuzhiyun 			  NVDEF(NV906F, SEMAPHORED, ACQUIRE_SWITCH, ENABLED));
72*4882a593Smuzhiyun 		PUSH_KICK(push);
73*4882a593Smuzhiyun 	}
74*4882a593Smuzhiyun 	return ret;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun static int
nvc0_fence_context_new(struct nouveau_channel * chan)78*4882a593Smuzhiyun nvc0_fence_context_new(struct nouveau_channel *chan)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun 	int ret = nv84_fence_context_new(chan);
81*4882a593Smuzhiyun 	if (ret == 0) {
82*4882a593Smuzhiyun 		struct nv84_fence_chan *fctx = chan->fence;
83*4882a593Smuzhiyun 		fctx->base.emit32 = nvc0_fence_emit32;
84*4882a593Smuzhiyun 		fctx->base.sync32 = nvc0_fence_sync32;
85*4882a593Smuzhiyun 	}
86*4882a593Smuzhiyun 	return ret;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun int
nvc0_fence_create(struct nouveau_drm * drm)90*4882a593Smuzhiyun nvc0_fence_create(struct nouveau_drm *drm)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun 	int ret = nv84_fence_create(drm);
93*4882a593Smuzhiyun 	if (ret == 0) {
94*4882a593Smuzhiyun 		struct nv84_fence_priv *priv = drm->fence;
95*4882a593Smuzhiyun 		priv->base.context_new = nvc0_fence_context_new;
96*4882a593Smuzhiyun 	}
97*4882a593Smuzhiyun 	return ret;
98*4882a593Smuzhiyun }
99