1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2012 Red Hat Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a
5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"),
6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation
7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the
9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions:
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in
12*4882a593Smuzhiyun * all copies or substantial portions of the Software.
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE.
21*4882a593Smuzhiyun *
22*4882a593Smuzhiyun * Authors: Ben Skeggs <bskeggs@redhat.com>
23*4882a593Smuzhiyun */
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #include <nvif/os.h>
26*4882a593Smuzhiyun #include <nvif/class.h>
27*4882a593Smuzhiyun #include <nvif/cl0002.h>
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #include "nouveau_drv.h"
30*4882a593Smuzhiyun #include "nouveau_dma.h"
31*4882a593Smuzhiyun #include "nv10_fence.h"
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #include "nv50_display.h"
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun static int
nv50_fence_context_new(struct nouveau_channel * chan)36*4882a593Smuzhiyun nv50_fence_context_new(struct nouveau_channel *chan)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun struct nv10_fence_priv *priv = chan->drm->fence;
39*4882a593Smuzhiyun struct nv10_fence_chan *fctx;
40*4882a593Smuzhiyun struct ttm_resource *reg = &priv->bo->bo.mem;
41*4882a593Smuzhiyun u32 start = reg->start * PAGE_SIZE;
42*4882a593Smuzhiyun u32 limit = start + reg->size - 1;
43*4882a593Smuzhiyun int ret;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
46*4882a593Smuzhiyun if (!fctx)
47*4882a593Smuzhiyun return -ENOMEM;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun nouveau_fence_context_new(chan, &fctx->base);
50*4882a593Smuzhiyun fctx->base.emit = nv10_fence_emit;
51*4882a593Smuzhiyun fctx->base.read = nv10_fence_read;
52*4882a593Smuzhiyun fctx->base.sync = nv17_fence_sync;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun ret = nvif_object_ctor(&chan->user, "fenceCtxDma", NvSema,
55*4882a593Smuzhiyun NV_DMA_IN_MEMORY,
56*4882a593Smuzhiyun &(struct nv_dma_v0) {
57*4882a593Smuzhiyun .target = NV_DMA_V0_TARGET_VRAM,
58*4882a593Smuzhiyun .access = NV_DMA_V0_ACCESS_RDWR,
59*4882a593Smuzhiyun .start = start,
60*4882a593Smuzhiyun .limit = limit,
61*4882a593Smuzhiyun }, sizeof(struct nv_dma_v0),
62*4882a593Smuzhiyun &fctx->sema);
63*4882a593Smuzhiyun if (ret)
64*4882a593Smuzhiyun nv10_fence_context_del(chan);
65*4882a593Smuzhiyun return ret;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun int
nv50_fence_create(struct nouveau_drm * drm)69*4882a593Smuzhiyun nv50_fence_create(struct nouveau_drm *drm)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun struct nv10_fence_priv *priv;
72*4882a593Smuzhiyun int ret = 0;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
75*4882a593Smuzhiyun if (!priv)
76*4882a593Smuzhiyun return -ENOMEM;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun priv->base.dtor = nv10_fence_destroy;
79*4882a593Smuzhiyun priv->base.resume = nv17_fence_resume;
80*4882a593Smuzhiyun priv->base.context_new = nv50_fence_context_new;
81*4882a593Smuzhiyun priv->base.context_del = nv10_fence_context_del;
82*4882a593Smuzhiyun spin_lock_init(&priv->lock);
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun ret = nouveau_bo_new(&drm->client, 4096, 0x1000,
85*4882a593Smuzhiyun NOUVEAU_GEM_DOMAIN_VRAM,
86*4882a593Smuzhiyun 0, 0x0000, NULL, NULL, &priv->bo);
87*4882a593Smuzhiyun if (!ret) {
88*4882a593Smuzhiyun ret = nouveau_bo_pin(priv->bo, NOUVEAU_GEM_DOMAIN_VRAM, false);
89*4882a593Smuzhiyun if (!ret) {
90*4882a593Smuzhiyun ret = nouveau_bo_map(priv->bo);
91*4882a593Smuzhiyun if (ret)
92*4882a593Smuzhiyun nouveau_bo_unpin(priv->bo);
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun if (ret)
95*4882a593Smuzhiyun nouveau_bo_ref(NULL, &priv->bo);
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun if (ret) {
99*4882a593Smuzhiyun nv10_fence_destroy(drm);
100*4882a593Smuzhiyun return ret;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun nouveau_bo_wr32(priv->bo, 0x000, 0x00000000);
104*4882a593Smuzhiyun return ret;
105*4882a593Smuzhiyun }
106